CN113690352B - Light-emitting diode chip with current blocking layer and preparation method thereof - Google Patents
Light-emitting diode chip with current blocking layer and preparation method thereof Download PDFInfo
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- CN113690352B CN113690352B CN202110743760.1A CN202110743760A CN113690352B CN 113690352 B CN113690352 B CN 113690352B CN 202110743760 A CN202110743760 A CN 202110743760A CN 113690352 B CN113690352 B CN 113690352B
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- 230000000903 blocking effect Effects 0.000 title claims abstract description 114
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 68
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 239000002390 adhesive tape Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229920006267 polyester film Polymers 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000006185 dispersion Substances 0.000 abstract description 5
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 26
- 239000000463 material Substances 0.000 description 13
- 229910002704 AlGaN Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The disclosure provides a light-emitting diode chip with a current blocking layer and a preparation method thereof, belonging to the field of light-emitting diode manufacturing. The epitaxial wafer comprises a substrate, an n-type layer, a light-emitting layer, a p-type layer, a current blocking layer and an indium tin oxide layer which are sequentially laminated on the substrate, wherein the current blocking layer is provided with electrode holes communicated with the p-type layer, electrode grooves communicated with the p-type layer and uniformly distributed along the circumferential direction of the electrode holes, the electrode grooves are spaced from the electrode holes, and the indium tin oxide layer on the current blocking layer is provided with avoidance holes. The p electrode is positioned on the current blocking layer and covers the avoidance hole, the electrode hole and the electrode groove, and the current density of the p electrode can be dispersed into the electrode hole and the uniformly distributed electrode groove and enter the p-type layer in a relatively uniform and relatively dispersed manner so that the LED chip can emit light normally. The concentration degree of the current is reduced, the dispersion degree is improved, the possibility of current breakdown caused by over concentration of the current is reduced, and the service life of the light-emitting diode chip is prolonged.
Description
Technical Field
The present disclosure relates to the field of light emitting diode fabrication, and in particular, to a light emitting diode chip with a current blocking layer and a method for manufacturing the same.
Background
A light emitting diode is a semiconductor electronic device capable of emitting light. As a novel efficient, environment-friendly and green solid-state lighting source, the solid-state lighting source is rapidly and widely applied to traffic lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlights and the like, and the improvement of the luminous efficiency of chips is a continuously pursued goal of light-emitting diodes.
The light-emitting diode chip is a basic structure for preparing a light-emitting diode, and at least comprises an n electrode, a p electrode and an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, and an n-type layer, a light-emitting layer, a p-type layer, a current blocking layer and an indium tin oxide layer which are laminated on the substrate. The current blocking layer is provided with a groove extending to the n-type layer, and the n-electrode is positioned on the surface of the n-type layer exposed by the groove; the current blocking layer is provided with a through hole, a part of the indium tin oxide layer is positioned in the through hole, and the indium tin oxide layer is communicated with the p-type layer and the p-electrode. partial current between the p electrode and the p type layer is directly transmitted through the through hole, so that the current at the through hole is easily concentrated, and the service life of the light emitting diode chip is influenced due to current breakdown.
Disclosure of Invention
The embodiment of the disclosure provides a light-emitting diode chip with a current blocking layer and a preparation method thereof, which can disperse current and reduce the possibility of current breakdown so as to prolong the service life of the light-emitting diode chip. The technical scheme is as follows:
the embodiment of the disclosure provides a light-emitting diode chip with a current blocking layer, the light-emitting diode chip comprises an n electrode, a p electrode and an epitaxial wafer, the epitaxial wafer comprises a substrate, and an n-type layer, a light-emitting layer, a p-type layer, a current blocking layer and an indium tin oxide layer which are sequentially laminated on the substrate, the p-type layer is provided with a groove extending to the n-type layer,
the current blocking layer is laminated on part of the surface of the p-type layer, the current blocking layer is provided with electrode holes communicated with the p-type layer, the current blocking layer is provided with a plurality of electrode grooves communicated with the p-type layer, which are uniformly distributed along the circumferential direction of the electrode holes, the electrode grooves are mutually spaced from the electrode holes,
the indium tin oxide layer is laminated on the current blocking layer and the p-type layer, the indium tin oxide layer is provided with an avoidance hole communicated with the electrode hole and the electrode groove, the avoidance hole comprises a round part coaxial with the electrode hole and a plurality of strip-shaped parts corresponding to the electrode grooves one by one, the orthographic projection of the strip-shaped parts on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate,
the n-electrode is positioned on the surface of the n-type layer exposed by the groove, the p-electrode is positioned on the current blocking layer and covers the electrode holes and the circular portions, and a blank area is formed between the side wall of each strip-shaped portion and the peripheral wall of the p-electrode.
Optionally, the orthographic projection of each electrode groove on the surface of the substrate is strip-shaped, and the length direction of the strip-shaped is parallel to one diameter of the electrode hole.
Optionally, the ratio of the length of the strip to the width of the strip is 1:1-2:1.
Optionally, the length of the electrode groove is 15-25 um.
Optionally, the minimum distance between the electrode hole and the electrode groove is 1 um-5 um.
The embodiment of the disclosure provides a preparation method of a light emitting diode chip with a current blocking layer, which comprises the following steps:
providing a substrate;
sequentially growing an n-type layer, a light-emitting layer and a p-type layer on the substrate;
forming a groove extending to the n-type layer on the p-type layer;
growing a current blocking layer on the p-type layer, the current blocking layer having electrode holes communicated to the p-type layer, the current blocking layer having a plurality of electrode grooves communicated to the p-type layer uniformly distributed along a circumferential direction of the electrode holes, the plurality of electrode grooves being spaced apart from the electrode holes;
forming an indium tin oxide layer on the current blocking layer and the p-type layer, wherein the indium tin oxide layer is provided with an avoidance hole communicated with the electrode hole and the electrode groove, the avoidance hole comprises a round part coaxial with the electrode hole and a plurality of strip-shaped parts in one-to-one correspondence with the electrode grooves, and the orthographic projection of the strip-shaped parts on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate;
forming an n electrode on a surface of the n-type layer exposed by the groove;
and forming a p electrode on the current blocking layer and part of the p-type layer, wherein the p electrode is positioned on the current blocking layer and covers the electrode holes and the round parts, and a blank area is formed between the side wall of each strip-shaped part and the peripheral wall of the p electrode.
Optionally, the p electrode is formed by magnetron sputtering.
Optionally, the magnetron sputtering temperature of the p electrode is 20-60 ℃, and the magnetron sputtering pressure of the p electrode is 1E -6 mtorr～8E -7 mtorr。
Optionally, forming a p-electrode on the current blocking layer and part of the p-type layer includes:
coating photoresist on the surfaces of the indium tin oxide layer, the current blocking layer and the p-type layer exposed;
forming electrode pattern holes on the surface of the photoresist;
forming a p electrode in the electrode pattern hole by magnetron sputtering and forming a metal layer on the surface of the photoresist;
adhering and removing the metal layer by using an adhesive tape;
and removing the photoresist to obtain the p electrode.
Optionally, the adhesive tape is a transparent polyester film having adhesive force.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the epitaxial wafer comprises a substrate, and an n-type layer, a light-emitting layer, a p-type layer, a current blocking layer and an indium tin oxide layer which are sequentially laminated on the substrate, wherein the p-type layer is provided with a groove extending to the n-type layer so as to facilitate the growth of an n electrode on the n-type layer. The current blocking layer covers part of the surface of the p-type layer, the current blocking layer is used for growing a p-electrode, an electrode hole communicated with the p-type layer is formed in the current blocking layer, the current blocking layer is also provided with a plurality of electrode grooves communicated with the p-type layer, the electrode grooves are uniformly distributed along the circumferential direction of the electrode hole, the electrode grooves are spaced from the electrode hole, the avoidance hole of the indium tin oxide layer on the current blocking layer comprises a circular part coaxial with the electrode hole and a plurality of strip-shaped parts corresponding to the electrode grooves one by one, the circular part can ensure that the p-electrode grows into the circular part and the electrode hole to realize normal flow of current, and the indium tin oxide layer can also realize current expansion; the orthographic projection of the strip-shaped part on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate, and a blank area can be formed between the side wall of the strip-shaped part and the peripheral wall of the p electrode, and the blank area is not conductive and can further effectively disperse current. The current density of the p-electrode can be dispersed into the electrode holes and the uniformly distributed electrode grooves, so that the current can enter the p-type layer uniformly and dispersedly to enable the light-emitting diode chip to emit light normally. The concentration degree of the current is reduced, the dispersion degree is improved, the possibility of current breakdown caused by over concentration of the current is reduced, and the service life of the light-emitting diode chip is prolonged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a light emitting diode chip with a current blocking layer according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a current blocking layer and an indium tin oxide layer provided by embodiments of the present disclosure;
FIG. 3 is a schematic diagram of an indium tin oxide layer and a p-electrode provided in an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another light emitting diode chip according to an embodiment of the disclosure;
fig. 5 is a flowchart of a light emitting diode chip with a current blocking layer and a method for manufacturing the same according to an embodiment of the present disclosure;
fig. 6 is a flowchart of another light emitting diode chip with a current blocking layer and a method for manufacturing the same according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
For ease of understanding, fig. 1 is a schematic structural diagram of a light emitting diode chip with a current blocking layer provided in an embodiment of the present disclosure, and referring to fig. 1, it can be seen that the embodiment of the present disclosure provides a light emitting diode chip with a current blocking layer 35, the light emitting diode chip includes an n electrode 1, a p electrode 2 and an epitaxial wafer 3, the epitaxial wafer 3 includes a substrate 31, and an n-type layer 32, a light emitting layer 33, a p-type layer 34, a current blocking layer 35 and an indium tin oxide layer 36 sequentially stacked on the substrate 31, and the p-type layer 34 has a recess S extending to the n-type layer 32.
The current blocking layer 35 is laminated on a part of the surface of the p-type layer 34, the current blocking layer 35 has electrode holes 351 connected to the p-type layer 34, the current blocking layer 35 has a plurality of electrode grooves 352 connected to the p-type layer 34 uniformly distributed along the circumferential direction of the electrode holes 351, and the plurality of electrode grooves 352 are spaced apart from the electrode holes 351.
The indium tin oxide layer 36 is laminated on the current blocking layer 35 and the p-type layer 34, the indium tin oxide layer 36 has a relief hole 361 communicating with the electrode hole 351 and the electrode groove 352, the relief hole 361 includes a circular portion 3611 coaxial with the electrode hole 351 and a plurality of stripe portions 3612 in one-to-one correspondence with the plurality of electrode grooves 352, and an orthographic projection of the stripe portions 3612 on the surface of the substrate 31 is located in an orthographic projection of the electrode groove 352 on the surface of the substrate.
The n-electrode 1 is located on the surface of the n-type layer 32 exposed by the groove S, the p-electrode 2 is located on the current blocking layer 35 and the p-electrode 2 covers the escape hole 361, the electrode hole 351, and the electrode groove 352, and a blank area C is formed between the side wall of each stripe-shaped portion 3612 and the peripheral wall of the p-electrode 2.
The epitaxial wafer 3 includes a substrate 31, an n-type layer 32, a light emitting layer 33, a p-type layer 34, a current blocking layer 35, and an indium tin oxide layer 36 sequentially stacked on the substrate 31, the p-type layer 34 having a groove S extending to the n-type layer 32 so as to grow an n-electrode 1 on the n-type layer 32. The current blocking layer 35 covers part of the surface of the p-type layer 34, the current blocking layer 35 is used for growing the p-electrode 2, the current blocking layer 35 is provided with electrode holes 351 communicated with the p-type layer 34, the current blocking layer 35 is also provided with electrode grooves 352 communicated with the p-type layer 34, the electrode grooves 352 are spaced from the electrode holes 351, the avoidance holes 361 of the indium tin oxide layer 36 on the current blocking layer 35 can ensure that the p-electrode 2 grows into the electrode grooves 352 and the electrode holes 351, and the indium tin oxide layer 36 can realize current expansion. The p-electrode 2 is located on the current blocking layer 35, the p-electrode 2 covers the avoiding hole 361, the electrode hole 351 and the electrode groove 352, the p-electrode 2 can be communicated to the p-type layer 34 through the electrode hole 351 and the electrode groove 352, and the current density of the p-electrode 2 can be dispersed into the electrode hole 351 and the uniformly distributed electrode groove 352, so that the p-type layer 34 can be more uniformly and more dispersedly led into the light emitting diode chip to emit light normally. The concentration degree of the current is reduced, the dispersion degree is improved, the possibility of current breakdown caused by over concentration of the current is reduced, and the service life of the light-emitting diode chip is prolonged.
And the existence of the blank area C can reduce the overall growth cost to a certain extent.
The blank area C is filled with the passivation layer 39. The blank area C is covered by the passivation layer 39 only, so that light absorption of light at and above the blank area C can be reduced, and light extraction efficiency can be improved.
The electrode hole 351 is a columnar hole, and the orthographic projections of the electrode hole 351 and the electrode groove 352 on the surface of the substrate 31 are located in the orthographic projection region of the relief hole 361 of the indium tin oxide layer 36 on the surface of the substrate 31. An electrode groove 352 is provided on the side wall of the current blocking layer 35.
Illustratively, the number of electrode slots 352 may be 3-6.
The current of the p electrode 2 can be effectively dispersed and expanded, so that the current can enter the chip of the light-emitting diode more uniformly, the light-emitting uniformity of the finally obtained epitaxial wafer 3 is improved, and the possibility of current breakdown of the light-emitting diode chip is reduced. The number of the electrode grooves 352 in fig. 1 and 2 may be 4, so as to ensure the quality of the finally obtained led chip and reduce the possibility of the chip being broken down by current.
Alternatively, each electrode groove 352 is orthographic projected on the surface of the substrate 31 in a stripe shape, and the length direction of the stripe shape is parallel to one diameter of the electrode hole 351.
The orthographic projection of each electrode groove 352 on the surface of the substrate 31 is in a strip shape, the length direction of the strip shape is parallel to one diameter of the electrode hole 351, the electrode grooves 352 can provide more flowing areas of the p electrode 2, the current dispersing effect is good, and breakdown is not easy to occur.
The surface of the substrate 31 is a surface of the substrate 31 for stacking epitaxial materials. The epitaxial material includes an epitaxial layer such as an n-type layer 32 and a light-emitting layer 33.
Illustratively, the inner wall of the electrode slot 352 proximate to one end of the electrode aperture 351 is arcuate in a direction parallel to the surface of the substrate 31.
In the direction parallel to the surface of the substrate 31, the inner wall of the electrode groove 352 near one end of the electrode hole 351 is arc-shaped, so that the dispersion effect of the electrode groove 352 on the p-electrode 2 can be ensured, and the adhesion between the electrode groove 352 and the p-electrode 2 is good. The inner wall of the electrode groove 352 near one end of the electrode hole 351 is projected in an arc on the surface of the substrate 31.
Optionally, the ratio of the length of the stripe to the width of the stripe is 1:1 to 2:1 on the premise that the orthographic projection of the electrode groove 352 on the surface of the substrate 31 is the stripe.
When the length of the stripe shape and the width of the stripe shape are within the above range, the p-electrode 2 can be grown well in the electrode groove 352, and the distribution of the current transmitted by the p-electrode 2 is also more uniform, and the current of the p-electrode 2 is not excessively concentrated. The cost of the current blocking layer 35 and the p electrode 2 is controlled, and meanwhile, the problem of possible current breakdown of the light emitting diode chip is effectively reduced.
Illustratively, the electrode slots 352 have a length of 15um to 25um.
When the length of the electrode groove 352 is within the above range, it is ensured that the expansion range of the current of the p-electrode 2 to be finally obtained is sufficient, and the current breakdown is not likely to occur.
Alternatively, the width of the electrode groove 352 is 10um to 20um.
When the width of the electrode groove 352 is within the above range, the growth quality of the p-electrode 2 in the electrode groove 352 is good, and the current of the p-electrode 2 can be effectively expanded, so that the possibility of current breakdown of the light emitting diode chip is reduced.
In other implementations provided by the present disclosure, the orthographic projection of the electrode grooves 352 on the surface of the substrate 31 may also be rectangular, circular, or other irregular shape, as the present disclosure is not limited in this regard. The length or width of the electrode groove 352 may also be different from the above range, which is not limited by the present disclosure.
Alternatively, the minimum distance between the electrode hole 351 and the electrode groove 352 is 1um to 5um.
The minimum distance between the electrode hole 351 and the electrode groove 352 is within the above range, and the p-electrode 2 is relatively compact in structure and the effect of current dispersion of the p-electrode 2 is good.
The minimum distance between the electrode hole 351 and the electrode groove 352 is the minimum distance between the electrode hole 351 and the electrode groove 352 in the direction parallel to the surface of the substrate 31.
The height of the current blocking layer 35 is, for example, 0.08um to 0.5um.
The height of the current blocking layer 35 is within the above range, and effective diffusion of current can be ensured.
In implementations provided by the present disclosure, the material of the current blocking layer 35 may be silicon oxide. In other implementations provided by the present disclosure, the material of the current blocking layer 35 may also be a material such as aluminum oxide, which is not limited by the present disclosure.
Alternatively, the height of the indium tin oxide layer 36 is 0.02um to 0.24um. The indium tin oxide layer 36 itself has a good quality while ensuring the expansion of the current.
The height is a height in a direction perpendicular to the surface of the substrate 31.
Fig. 2 is a schematic diagram of a current blocking layer and an indium tin oxide layer provided by an embodiment of the present disclosure, and fig. 3 is a schematic diagram of an indium tin oxide layer and a p-electrode provided by an embodiment of the present disclosure, referring to fig. 2 and 3, it can be seen that a diameter of a circular portion 3611 of the dodging hole 361 may be larger than a diameter of the electrode hole 351, a diameter of the p-electrode 2 may be larger than a diameter of the circular portion 3611 and a diameter of the p-electrode 2 is smaller than a maximum distance between two stripe portions 3612, where the maximum distance is a maximum distance between the two stripe portions 3612 in a direction parallel to a surface of the substrate 31.
The formation and growth of the avoiding holes 361 and the p-electrode 2 can be facilitated, and the stable contact between the p-electrode 2 and the indium tin oxide layer 36 can be ensured, so that the finally obtained current conduction effect and the overall quality are both good.
Illustratively, the forward projected outer contour of the p-electrode 2 on the surface of the substrate 31 is located within the forward projected outer contour of the current blocking layer 35 on the surface of the substrate 31. And there is a superposition of the orthographic projection of the current blocking layer 35 on the surface of the substrate 31 and the orthographic projection of the indium tin oxide layer 36 on the surface of the substrate 31.
Good contact between the p-electrode 2 and the indium tin oxide layer 36 can be ensured, and meanwhile, the p-electrode 2 can be stably prepared on the current blocking layer 35, so that the inside of the epitaxial wafer 3 is protected.
The surface of the current blocking layer 35 not covered by the p-electrode 2 may be covered with the indium tin oxide layer 36, and the inner walls of the escape holes 361 of the indium tin oxide layer 36 may be fixed to the outer peripheral wall of the p-electrode 2. The epitaxial wafer 3 has a good internal quality, and the adhesion between the p-electrode 2 and the indium tin oxide layer 36 is good.
Fig. 4 is a schematic structural diagram of another light emitting diode chip according to an embodiment of the disclosure, and referring to fig. 4, it can be seen that in another implementation manner of the disclosure, the light emitting diode chip includes an n-electrode 1, a p-electrode 2 and an epitaxial wafer 3, the epitaxial wafer 3 includes a substrate 31, and a buffer layer 37, an n-type layer 32, a light emitting layer 33, an AlGaN electron blocking layer 38, a p-type layer 34, a current blocking layer 35 and an indium tin oxide layer 36 sequentially stacked on the substrate 31, and the p-type layer 34 has a recess S extending to the n-type layer 32.
The current blocking layer 35 is laminated on a part of the surface of the p-type layer 34, the current blocking layer 35 has electrode holes 351 connected to the p-type layer 34, the current blocking layer 35 has electrode grooves 352 connected to the p-type layer 34 uniformly distributed along the circumferential direction of the electrode holes 351, and the electrode grooves 352 are spaced apart from the electrode holes 351.
The indium tin oxide layer 36 is stacked on the current blocking layer 35 and the p-type layer 34, and the indium tin oxide layer 36 has a relief hole 361 communicating with the electrode hole 351 and the electrode groove 352.
The n-electrode 1 is located on the surface of the n-type layer 32 exposed by the recess S, the p-electrode 2 is located on the current blocking layer 35 and the p-electrode 2 covers the escape hole 361, the electrode hole 351, and the electrode groove 352.
Note that the structure of the current blocking layer 35, the structure of the indium tin oxide layer 36, and the structure of the p-electrode 2 shown in fig. 4 are the same as the structure of the current blocking layer 35, the structure of the indium tin oxide layer 36, and the structure of the p-electrode 2 shown in fig. 1, respectively, and thus will not be described again here.
Alternatively, the substrate 31 may be a sapphire substrate 31. Easy to manufacture and obtain.
Illustratively, the buffer layer 37 may include a GaN buffer layer sequentially stacked on the substrate 31. Lattice mismatch can be effectively relieved.
In other implementations provided by the present disclosure, buffer layer 37 may also be one of aluminum nitride, aluminum gallium nitride, or aluminum indium gallium nitride. The present disclosure is not limited in this regard.
Alternatively, the n-type layer 32 may be an n-type GaN layer. The doping element of the n-type GaN layer may be Si, and the doping concentration of the Si element may be 1×10 18 ～1×10 19 cm -3 . The overall quality of the n-type GaN layer is good.
Illustratively, the thickness of the n-type GaN layer may be 1-5 μm. The overall quality of the obtained n-type GaN layer is good.
In one implementation provided by the present disclosure, the thickness of the n-type GaN layer may be 3 μm. The present disclosure is not limited in this regard.
Illustratively, the light emitting layer 33 includes a plurality of InGaN well layers and GaN barrier layers alternately stacked, and the InGaN well layers may have a thickness of 2 to 5nm and the GaN barrier layers may have a thickness of 8 to 20nm.
Illustratively, the overall thickness of the light emitting layer 33 may be 50 to 130nm, with an in molar content of 13 to 25%.
Alternatively, the Al composition in AlGaN electron barrier layer 38 may be 0.15 to 0.25. The effect of blocking electrons is good.
Alternatively, the AlGaN electron blocking layer 38 may have a thickness of 20-100 nm. The quality of the resulting AlGaN electron blocking layer 38 is better.
Can provide enough holes and ensure that the overall cost of the light-emitting diode chip is not excessively high.
Alternatively, the p-type layer 34 may be a p-type GaN layer. The thickness of the p-type GaN layer may be 80-300 nm. Sufficient holes can be provided.
Illustratively, the material of the current blocking layer 35 is silicon oxide, and the thickness of the current blocking layer 35 is 2-3 um. It is possible to effectively prevent current from directly striking the p-type layer 34 and damaging the p-type layer 34.
Alternatively, the indium tin oxide layer 36 is made of indium tin oxide material, and the thickness of the indium tin oxide layer 36 may be 0.5-1.5 um. The quality of the obtained light-emitting diode chip is better.
Alternatively, the n-electrode 1 and the p-electrode 2 may be made of at least one material selected from gold, aluminum, chromium, nickel, platinum, and titanium.
Illustratively, the material of passivation layer 39 is silicon oxide, and the thickness of passivation layer 39 is 2-3 um. The quality of the obtained light-emitting diode chip is better.
The epitaxial wafer 3 structure shown in fig. 4 is a structure in which a buffer layer 37 is added between the substrate 31 and the n-type GaN layer, and an AlGaN electron blocking layer 38 for preventing electrons from overflowing is added between the multiple quantum well layer and the p-type composite layer, compared with the epitaxial wafer 3 structure shown in fig. 1. And the luminous uniformity is ensured. The quality and luminous efficiency of the epitaxial wafer 3 obtained as a whole are better.
It should be noted that, in other implementations provided in the present disclosure, the light emitting diode chip may also include other hierarchies, which is not limited in this disclosure. In addition, the main material of the led chip provided by the present disclosure is gallium nitride, and in other implementations provided by the present disclosure, the main material of the led chip may be aluminum gallium arsenide or aluminum gallium indium phosphide, which is not limited herein.
Fig. 5 is a flowchart of a method for preparing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 5, the method for preparing an led chip with a current blocking layer and the method for preparing the same may include:
s101: a substrate is provided.
S102: an n-type layer, a light emitting layer, and a p-type layer are sequentially grown on a substrate.
S103: a recess is formed in the p-type layer extending to the n-type layer.
S104: and growing a current blocking layer on the p-type layer, wherein the current blocking layer is provided with electrode holes communicated with the p-type layer, and a plurality of electrode grooves communicated with the p-type layer and uniformly distributed along the circumferential direction of the electrode holes, and the electrode grooves are mutually spaced from the electrode holes.
S105: and forming an indium tin oxide layer on the current blocking layer and the p-type layer, wherein the indium tin oxide layer is provided with an avoidance hole communicated with the electrode hole and the electrode groove, the avoidance hole comprises a round part coaxial with the electrode hole and a plurality of strip-shaped parts in one-to-one correspondence with the electrode grooves, and the orthographic projection of the strip-shaped parts on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate.
S106: an n-electrode is formed on the surface of the n-type layer exposed by the recess.
S107: and forming a p electrode on the current blocking layer and part of the p-type layer, wherein the p electrode is positioned on the current blocking layer and covers the electrode hole and the circular part, and a blank area is formed between each strip-shaped part and the peripheral wall of the p electrode.
Step S107 may include: the p-electrode is formed by magnetron sputtering.
The p-electrode is formed by adopting a magnetron sputtering mode, the temperature and the reflecting materials are relatively stable in the magnetron sputtering process, and the possibility of deformation of photoresist, a metal layer and the like for preparing the p-electrode is small, so that the shape and the quality of the finally obtained p-electrode are relatively good, and the stable use of the p-electrode and the light-emitting diode chip is ensured.
Optionally, the magnetron sputtering temperature of the p electrode is 20-60 ℃, and the magnetron sputtering pressure of the p electrode is 1E -6 mtorr～8E -7 mtorr。
When the magnetron sputtering temperature and the sputtering pressure of the p electrode are in the above ranges, the p electrode with better quality can be obtained, and the service life of the finally obtained light-emitting diode is prolonged.
Illustratively, in step S107, forming a p-electrode over the current blocking layer and a portion of the p-type layer includes:
coating photoresist on the exposed surfaces of the indium tin oxide layer, the current blocking layer and the p-type layer; forming electrode pattern holes on the surface of the photoresist; forming a p electrode in the electrode pattern hole by magnetron sputtering and forming a metal layer on the surface of the photoresist; adhering and removing the metal layer by using an adhesive tape; and removing the photoresist to obtain the p electrode.
Before removing the photoresist, an adhesive tape can be used, after the metal layer is adhered, the adhesive tape and the adhered metal layer are lifted off the photoresist together so as to separate the metal layer from the photoresist, thereby reducing the influence of the metal layer residue on the surface of the epitaxial wafer in the process of removing the photoresist and ensuring the integrity of the surface of the epitaxial wafer.
The electrode pattern hole on the photoresist can be obtained by sequentially exposing, developing and etching the photoresist.
The photoresist may be removed using an organic solution such as N-methylpyrrolidone. The etching of the photoresist may be physical etching or chemical etching, which is not limited in this disclosure.
In the process of magnetron sputtering the electrode, a part of metal may be sputtered onto the surface of the photoresist to form a metal layer, and both the metal layer and the photoresist may need to be removed.
Alternatively, the adhesive tape is a transparent polyester film having adhesive force. The metal layer can be effectively removed while the acquisition is convenient.
The technical effects of the preparation method after the execution of step S107 in fig. 5 may refer to the technical effects corresponding to the light emitting diode chip shown in fig. 1, so that the technical effects of the preparation method in fig. 5 will not be described herein.
Fig. 6 is a flowchart of another light emitting diode chip with a current blocking layer and a method for manufacturing the same according to an embodiment of the present disclosure, as shown in fig. 6, the light emitting diode chip and the method for manufacturing the same include:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: the surface of the substrate is treated for 6-10 min under the hydrogen atmosphere.
Illustratively, the temperature of the reaction chamber may be 1000-1200 ℃ and the pressure of the reaction chamber may be 200-500 Torr when treating the surface of the substrate.
In one implementation provided by the present disclosure, when the substrate is processed, the temperature of the reaction chamber may also be 1100 ℃, and the duration of processing the surface of the substrate may be 8 minutes.
Step S201 may further include: nitriding the surface of the substrate, and paving a layer of nitrogen atoms on the surface of the substrate. The rapid growth of gallium nitride material can be facilitated.
S202: a buffer layer is grown on the substrate.
Optionally, the temperature of the reaction cavity is controlled to be 950-1200 ℃, the pressure of the reaction cavity is controlled to be 200-500 torr, and the GaN buffer layer is grown. Obtaining the buffer layer with better quality.
S203: an n-type layer is grown on the buffer layer.
Alternatively, the n-type layer is an n-type GaN layer, the growth temperature of the n-type GaN layer can be 950 ℃ to 1200 ℃, and the growth pressure of the n-type GaN layer can be 200Torr to 500Torr.
S204: a light emitting layer is grown on the n-type layer.
In step S204, the light emitting layer includes InGaN well layers and GaN barrier layers alternately grown.
Alternatively, the growth temperature and the growth pressure of the InGaN well layer are respectively 700-800 ℃ and 100-300 torr, and the growth temperature and the growth pressure of the GaN barrier layer are respectively 700-900 ℃ and 100-300 torr. The quality of the obtained multi-quantum well layer is good.
Alternatively, the thickness of the InGaN well layer is 2-4 nm, and the thickness of the GaN barrier layer is 5-10 nm. The quality of the obtained multi-quantum well layer is good.
S205: and growing an AlGaN electron blocking layer on the light emitting layer.
The growth temperature of the AlGaN electron blocking layer may be 600-1000 ℃, and the growth pressure of the AlGaN electron blocking layer may be 100-300 Torr. The AlGaN electron blocking layer grown under the condition has better quality, and is beneficial to improving the luminous efficiency of the light-emitting diode.
S206: a p-type layer is grown on the AlGaN electron blocking layer.
Alternatively, the p-type layer is a p-type GaN layer, the growth temperature of the p-type GaN layer can be 900-1200 ℃, and the growth pressure of the p-type GaN layer can be 100-300 Torr.
S207: a recess is formed on the p-type layer extending to a surface of the n-type layer.
Alternatively, the recesses on the p-type layer may be realized by a photolithographic process. Is convenient for the preparation and the forming of the groove.
S208: and growing a current blocking layer on the p-type layer, wherein the current blocking layer is provided with electrode holes communicated with the p-type layer, and a plurality of electrode grooves communicated with the p-type layer and uniformly distributed along the circumferential direction of the electrode holes, and the electrode grooves are mutually spaced from the electrode holes.
Optionally, the current blocking layer and the indium tin oxide layer can be grown in a physical vapor deposition mode, the deposition temperature of the current blocking layer is 200-300 ℃, and the deposition pressure of the current blocking layer is 70-120 PA. A current blocking layer with better quality can be obtained.
It should be noted that the current blocking layer and the indium tin oxide layer only cover a part of the surface of the p-type layer, so that the preparation of the grooves on the p-type layer is not affected.
After the preparation of the current blocking layer is completed, the electrode hole and the electrode groove can be prepared on the current blocking layer through a photoetching process.
S209: and forming an indium tin oxide layer on the current blocking layer and the p-type layer, wherein the indium tin oxide layer is provided with an avoidance hole communicated with the electrode hole and the electrode groove, the avoidance hole comprises a round part coaxial with the electrode hole and a plurality of strip-shaped parts in one-to-one correspondence with the electrode grooves, and the orthographic projection of the strip-shaped parts on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate.
Illustratively, the deposition temperature of the indium tin oxide layer is 250-350 ℃, and the deposition pressure of the indium tin oxide layer is less than or equal to 6 x 10 -6 Torr can obtain an indium tin oxide layer with good quality. The relief holes may also be obtained by a photolithographic process and are therefore not described in detail herein.
S210: an n-electrode is formed on the surface of the n-type layer exposed by the recess.
In step S210, photoresist may be coated on the surface of the n-type layer; forming n electrode holes on the photoresist through a photoetching process; forming an n electrode in the n electrode hole; and finally removing the photoresist. The n-electrode formation is easy to realize.
S211: and forming a p electrode on the current blocking layer and part of the p-type layer, wherein the p electrode is positioned on the current blocking layer and covers the electrode hole and the circular part, and a blank area is formed between each strip-shaped part and the peripheral wall of the p electrode.
Step S211 may refer to step S107 in fig. 5, and thus will not be described herein.
The structure of the led chip after the execution of step S211 can be seen in fig. 4.
It should be noted that, in the embodiment of the present disclosure, the growth method of the light emitting diode is implemented using a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition ) apparatus. Adopts high-purity H 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH 4) as N-type dopant, trimethylaluminum (TMAL) as aluminum source, magnesium-cyclopentadienyl (CP 2 Mg) as P-type dopant.
The foregoing disclosure is not intended to be limited to any form of embodiment, but is not intended to limit the disclosure, and any simple modification, equivalent changes and adaptations of the embodiments according to the technical principles of the disclosure are intended to be within the scope of the disclosure, as long as the modifications or equivalent embodiments are possible using the technical principles of the disclosure without departing from the scope of the disclosure.
Claims (9)
1. A method for manufacturing a light emitting diode chip having a current blocking layer, the method comprising:
providing a substrate;
sequentially growing an n-type layer, a light-emitting layer and a p-type layer on the substrate;
forming a groove extending to the n-type layer on the p-type layer;
growing a current blocking layer on the p-type layer, the current blocking layer having electrode holes communicated to the p-type layer, the current blocking layer having a plurality of electrode grooves communicated to the p-type layer uniformly distributed along a circumferential direction of the electrode holes, the plurality of electrode grooves being spaced apart from the electrode holes;
forming an indium tin oxide layer on the current blocking layer and the p-type layer, wherein the indium tin oxide layer is provided with an avoidance hole communicated with the electrode hole and the electrode groove, the avoidance hole comprises a round part coaxial with the electrode hole and a plurality of strip-shaped parts in one-to-one correspondence with the electrode grooves, and the orthographic projection of the strip-shaped parts on the surface of the substrate is positioned in the orthographic projection of the electrode groove on the surface of the substrate;
forming an n electrode on a surface of the n-type layer exposed by the groove;
and forming a p electrode on the current blocking layer and part of the p-type layer, wherein the p electrode is positioned on the current blocking layer and covers the electrode holes and the round parts, and a blank area is formed between the side wall of each strip-shaped part and the peripheral wall of the p electrode.
2. The method of claim 1, wherein the p-electrode is formed by magnetron sputtering.
3. The method according to claim 2, wherein the magnetron sputtering temperature of the p-electrode is 20-60 ℃, and the magnetron sputtering pressure of the p-electrode is 1E -6 mtorr～8E -7 mtorr。
4. A method of manufacturing according to any one of claims 1 to 3, wherein forming a p-electrode on the current blocking layer and part of the p-type layer comprises:
coating photoresist on the surfaces of the indium tin oxide layer, the current blocking layer and the p-type layer exposed;
forming electrode pattern holes on the surface of the photoresist;
forming a p electrode in the electrode pattern hole by magnetron sputtering and forming a metal layer on the surface of the photoresist;
adhering and removing the metal layer by using an adhesive tape;
and removing the photoresist to obtain the p electrode.
5. The method of claim 4, wherein the adhesive tape is a transparent polyester film having adhesive force.
6. The method of claim 1, wherein each of the electrode grooves has a strip shape in front projection on the surface of the substrate, and a length direction of the strip shape is parallel to a diameter of the electrode hole.
7. The method of claim 6, wherein the ratio of the length of the strip to the width of the strip is 1:1 to 2:1.
8. The method according to claim 6 or 7, wherein the electrode groove has a length of 15um to 25um.
9. The method of claim 6 or 7, wherein the minimum distance between the electrode hole and the electrode groove is 1um to 5um.
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