CN113688085A

CN113688085A - A server interface management structure and method of a PCI-E device

Info

Publication number: CN113688085A
Application number: CN202110873300.0A
Authority: CN
Inventors: 韩瑞龙
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2021-11-23

Abstract

The invention discloses a server interface management structure and method for a PCI-E device, wherein the server interface management structure includes: an adapter board for connecting to a PCI-E device, wherein the adapter board includes a PCI-E slot and ID identification module; ID identification module for identifying PCI‑E devices connected to PCI‑E slots and generating board ID signals; baseboard management controller connected to the adapter board for identifying boards generated by the ID module The card ID signal generates a delay policy corresponding to the PCI-E device; the CPLD electrically connected to the baseboard management controller is used for generating and sending a delay reset signal corresponding to the PCI-E device to the PCI-E slot according to the delay policy. The technical solution of the present invention can solve the problem in the prior art that the server hardware interface is difficult to adapt to PCI-E devices with different reset delays.

Description

Server interface management structure and method of PCI-E equipment

Technical Field

The present invention relates to the field of server technologies, and in particular, to a server interface management structure and method for a PCI-E device

Background

With the development of cloud computing and big data technologies, the demand of related fields for server system resources is gradually increased. In order to meet the demand, processor suppliers upgrade system resources by means of improving the computing capacity of the processor, upgrading a multi-path processor platform and the like, so that the data processing capacity of the whole system is greatly improved, but the number of external interfaces of the server is increased, and accordingly a large number of server interface standards exist.

Among many interface standards for servers, PCI-E (Peripheral Component Interconnect Express) is the latest bus and interface standard. Because the data transmission rate of the PCI-E bus and interface standard is high and has considerable development potential, and the PCI-E has various specifications, the requirement of low-speed and high-speed equipment in the present and future foreseeable time can be met, and in addition, the PCI-E bus and interface standard is compatible with the present PCI technology and equipment on the software level and supports the initialization of the PCI equipment and the memory module, therefore, the PCI-E becomes the mainstream of the external connection interface of the server.

At present, most servers in the market are provided with PCI-E slots to expand external interfaces, and more intelligent network cards developed based on PCI-E specifications are widely applied to the servers. Compared with the standard PCI-E card, the reset signal delay of part of the intelligent network card is different. Specifically, the more complex the function of the intelligent network card is, the longer the power-on preparation time is, so that the time required for delaying the reset signal that must be reset after power-on is completed is longer, even longer by more than 10 times, and the reset signal delay of the intelligent network cards of different manufacturers has diversity. However, the conventional server interface management structure cannot identify the reset delay specification of the back-end PCI-E device, and further cannot perform dynamic adaptive configuration management, which finally results in that the external interface of the server hardware design cannot be compatible with PCI-E devices with different reset delays.

Disclosure of Invention

The invention provides a server interface management structure of PCI-E equipment, aiming at solving the problem that a server hardware interface in the prior art cannot be compatible with PCI-E equipment with different reset delays.

According to a first aspect of the present invention, the present invention provides a server interface management structure of a PCI-E device, comprising:

the adapter plate is used for accessing PCI-E equipment, and comprises a PCI-E slot and an ID identification module; the ID identification module is used for identifying PCI-E equipment connected with the PCI-E slot and generating a board card ID signal;

the base plate management controller is connected with the adapter plate and used for generating a delay strategy corresponding to the PCI-E equipment according to the plate card ID signal generated by the ID identification module;

and the CPLD is electrically connected with the baseboard management controller and used for generating and sending a delay reset signal corresponding to the PCI-E equipment to the PCI-E slot according to the delay strategy.

Preferably, the ID identification module includes:

the ID identification chip is connected with the PCI-E slot and is used for identifying the PCI-E equipment connected with the PCI-E slot;

and the IO pin is also electrically connected with the substrate management controller and is used for generating a board card ID signal and sending the board card ID signal to the substrate management controller.

Preferably, in the server interface management structure, the patch panel further includes a conductive contact electrically connected to the PCI-E slot and the ID identification module, respectively;

the adapter plate connector is electrically connected with the adapter plate through the conductive contact piece, wherein the adapter plate connector is also electrically connected with the substrate management controller.

Preferably, the server interface management structure further includes: the single-pole double-throw switch is electrically connected with the CPLD and comprises:

the delay gating switch interface is electrically connected with the delay strategy register of the CPLD and is used for gating the corresponding delay reset signal interface according to the delay gating signal sent by the CPLD;

the first delay reset signal interface is electrically connected with the standard delay signal generator of the CPLD;

a second delay reset signal interface electrically connected to the standard delay signal generator through the delay generating circuit;

and the delayed reset signal output port is electrically connected with the first delayed reset signal interface and the second delayed reset signal interface respectively, and is also electrically connected with the PCI-E slot.

Preferably, the delay generation circuit includes:

an RC delay line electrically connected to the standard delay signal generator;

and the delay reset signal trigger is connected with the RC delay line, and is also electrically connected with the second delay reset signal interface.

Preferably, the RC delay line includes:

a delay voltage converter electrically connected to the standard delay signal generator;

and the delay voltage generator is electrically connected with the delay voltage converter and is also electrically connected with the delay reset signal trigger.

Preferably, the server interface management structure further includes: and the mainboard is fixed with an adapter plate, a substrate management controller and a CPLD.

Preferably, the server interface management structure further includes: and the power supply is respectively and electrically connected with the adapter plate, the substrate management controller and the CPLD.

According to a second aspect of the present invention, the present invention further provides a server interface management method for a PCI-E device, where the method is used in the server interface management structure according to any one of the above technical solutions, and the server interface management method includes:

identifying PCI-E equipment connected with a PCI-E slot and generating a board card ID signal;

generating a delay strategy corresponding to the PCI-E equipment according to the board card ID signal;

and generating and sending a delay reset signal corresponding to the PCI-E equipment to the PCI-E slot according to the delay strategy.

According to the server interface management scheme of the PCI-E equipment, the PCI-E equipment is used through the ID identification module, a board card ID signal corresponding to the PCI-E equipment is generated, then the substrate management controller generates a delay strategy corresponding to the PCI-E equipment according to the board card ID signal, the complex programmable logic device CPLD generates and sends a delay reset signal corresponding to the PCI-E equipment to the PCI-E slot according to the delay strategy, and therefore the server interface management structure of the PCI-E equipment can distinguish different PCI-E equipment, identify the reset delay specification of the PCI-E equipment, conduct reset delay management of the PCI-E equipment in a dynamic self-adaptive mode, and is compatible with the PCI-E equipment with different reset delay specifications.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic diagram of a server interface management structure of a PCI-E device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a delay generation circuit provided in the embodiment of FIG. 1;

fig. 3 is a flowchart illustrating a method for managing a server interface of a PCI-E device according to an embodiment of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Reference numerals	Name (R)	Reference numerals	Name (R)
				1	Adapter plate	2	Baseboard management controller
3	CPLD	4	Adapter plate connector
				5	Single-pole double-throw switch	6	Delay generating circuit
7	Main board	8	Power supply
				101	PCI-E slot	102	ID identification module
103	Conductive contact piece	301	Delay strategy register
				302	Standard delay signal generator	501	Delay gated switch interface
B1	First delayed reset signal interface	B2	Second delayed reset signal interface
				A	Delayed reset signal output port	601	RC delay line
602	Delayed reset signal flip-flop	6011	Delay voltage converter
				6012	Delay voltage generator

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The main technical problems of the embodiment of the invention are as follows:

most servers in the market at present are provided with PCI-E slots to expand external interfaces, and more intelligent network cards developed based on PCI-E specifications are widely applied to the servers. Compared with the standard PCI-E card, the delay time of the reset signals of part of the intelligent network cards is different. Specifically, the more complex the function of the intelligent network card is, the longer the power-on preparation time is, so that the time required for delaying the reset signal that must be reset after power-on is completed is longer, even longer by more than 10 times, and the reset signal delay of the intelligent network cards of different manufacturers has diversity. However, the conventional server interface management structure cannot identify the reset delay specification of the back-end PCI-E device, and further cannot perform dynamic adaptive configuration management, which finally results in that the external interface of the server hardware design cannot be compatible with PCI-E devices with different reset delays.

In order to solve the above problem, referring to fig. 1 in particular, fig. 1 is a schematic diagram of a server interface management structure of a PCI-E device according to an embodiment of the present invention, as shown in fig. 1, the server interface management structure of the PCI-E device includes:

the adapter plate 1 is used for accessing PCI-E equipment, wherein the adapter plate 1 comprises a PCI-E slot 101 and an ID identification module 102; and the ID identification module 102 is configured to identify a PCI-E device connected to the PCI-E slot 101, and generate a board ID signal. The ID identification module 102 may uniformly design an 8-bit BOARD ID, and is formed by an IO pin of a PCA9554 chip, so that different PCI-E devices, such as a standard BOARD and an intelligent network card, can be distinguished by the BOARD ID signal corresponding to the PCI-E devices.

As a preferred embodiment, the ID identification module 102 includes:

an ID identification chip (not labeled in the figure) connected to the PCI-E slot 101, for identifying the PCI-E device connected to the PCI-E slot 101; and the IO pin (not marked in the figure) is connected with the ID identification chip and is also electrically connected with the substrate management controller 2, and is used for generating a board card ID signal and sending the board card ID signal to the substrate management controller 2.

The ID identification module 102 of the PCI-E device may design an 8-bit boss ID on the adapter card in a unified manner, and is formed by an IO pin of a PCA9554 chip, and the BMC I2C (Inter-Integrated Circuit, two-wire serial bus) in the PCI-E standard interface may obtain information of a specific device (e.g., an intelligent network card) through the boss ID. After the board ID signal is obtained, the board ID signal is sent to a baseboard management controller BMC, and the BMC can identify different PCI-E devices according to the board ID signal, so that different delay reset strategies are executed on the PCI-E devices of different types.

As shown in fig. 1, the server interface management structure of the PCI-E device further includes:

and the substrate management controller 2 connected to the patch panel 1 is configured to generate a delay policy corresponding to the PCI-E device according to the board ID signal generated by the ID identification module 102. The reset delay strategies corresponding to different IDs are stored in the register of the baseboard management controller 2, so that the reset delay strategies corresponding to the ID signals of the board cards are identified, the reset delay of the PCI-E equipment connected with the PCI-E slot 101 can be controlled according to the reset delay strategies, and a more flexible interface management mode is provided.

The CPLD3 electrically connected to the baseboard management controller 2 is configured to generate and send a delayed reset signal corresponding to the PCI-E device to the PCI-E slot 101 according to the delay policy. The CPLD3 is in communication connection with the BMC through a system management bus, and can switch the delay reset signals corresponding to different PCI-E devices through the single-pole double-throw switch 5.

According to the server interface management scheme of the PCI-E equipment, the ID identification module 102 is used for generating a board ID signal corresponding to the PCI-E equipment, then the substrate management controller 2 generates a delay strategy corresponding to the PCI-E equipment according to the board ID signal, and the complex programmable logic device CPLD3 generates and sends a delay reset signal corresponding to the PCI-E equipment to the PCI-E slot 101 according to the delay strategy, so that the server interface management structure of the PCI-E equipment can distinguish different PCI-E equipment, identify the reset delay specification of the PCI-E equipment, dynamically and adaptively perform reset delay management on the PCI-E equipment, and is compatible with the PCI-E equipment with different reset delay specifications.

As a preferred embodiment, as shown in fig. 1, the patch panel 1 further includes conductive contacts 103 electrically connected to the PCI-E slot 101 and the ID identification module 102, respectively; the board ID identified by the ID identification module 102 can be transmitted to the baseboard management controller 2 through the conductive contact 103, and the delayed reset signal generated by the CPLD3 can be sent to the PCI-E device accessed by the PCI-E slot 101 through the conductive contact 103, so as to implement reset delay management on different types of PCI-E devices.

And the adapter plate connector 4 is electrically connected with the adapter plate 1 through the conductive contact pieces 103, wherein the adapter plate connector 4 is also electrically connected with the substrate management controller 2. The patch panel connector 4 is connected to the conductive contacts 103 of the patch panel 1 so that the CPLD3 and the BMC can access the patch panel 1 through the patch panel connector 4.

As a preferred embodiment, as shown in fig. 1, the server interface management structure further includes: a single pole double throw switch 5 electrically connected to the CPLD3, the single pole double throw switch 5 comprising:

and the delay gating switch interface 501 is electrically connected with the delay strategy register 301 of the CPLD3 and is used for gating a corresponding delay reset signal interface according to the delay gating signal sent by the CPLD 3. After acquiring the board ID signal, the CPLD3 matches the board ID signal with a delay policy in its own register, and sends a corresponding delay strobe signal to the delay strobe switch interface 501 of the single-pole double-throw switch 5 according to the delay policy, and gates the corresponding delay reset signal interface, thereby sending delay reset signals with different delays.

And a first delayed reset signal interface B1 electrically connected to the standard delayed signal generator 302 of the CPLD 3. The first delay reset signal interface B1 is directly connected to the CPLD3 standard delay signal generator 302, and is configured to receive a standard delay signal sent by the CPLD3, where the standard delay signal corresponds to a standard PCI-E device and has a delay time of 100ms, and the standard delay signal is used to perform interface management on the standard PCI-E device connected to the PCI-E slot 101.

And a second delayed reset signal interface B2 electrically connected to the standard delayed signal generator 302 through the delay generating circuit 6. The second delay reset signal interface B2 is electrically connected to the standard delay signal generator 302 through the delay generating circuit 6, and the delay generating circuit 6 can change the delay time of the standard delay signal sent by the standard delay signal generator 302, so as to adapt to PCI-E devices with different delays, thereby implementing delay management of PCI-E devices with different delays.

And a delayed reset signal output port a electrically connected to the first delayed reset signal interface B1 and the second delayed reset signal interface B2, respectively, the delayed reset signal output port a being further electrically connected to the PCI-E slot 101.

The delayed reset signal output port a is connected to the first delayed reset signal interface B1 and the second delayed reset signal interface B2, respectively, so that the delayed reset signal can output delayed reset signals with different delays under the control of the delayed strobe switch interface 501, and thus the delayed reset signal output port outputs the delayed reset signals to the PCI-E slot 101, thereby implementing interface management of PCI-E devices of different types connected to the slot.

Specifically, for the adapter card where the standard PCI-E card is located, the ID is defined as [00000000], the BMC reads the card ID information on the PCA9554 chip on the adapter board 1 through I2C, and when the PCI-E card is identified to be the standard PCI-E card requiring 100ms RESET delay, the BMC sends the 100ms delay policy to the CPLD3 through the SGPMI interface, and the register in the CPLD3 receives the signal to trigger the CPLD _ RESET _ SEL to output the delay gating signal, so that the gating SEL pin of the single-pole double-throw switch 5 is at a low position. By searching a truth table of the single-pole double-throw switch, at the moment, a gating delay reset signal output port A is connected to a first delay reset signal interface B1, a CPLD3 outputs a reset signal meeting the 100ms delay of standard PCI-E card insertion reset to enter a B1, and then the reset signal is output to a PCI-E slot from A, and then the standard PCI-E protocol time sequence is provided. It should be noted that, as the CPU set resources are increasing, the reset signals of the same CPU are up to 40, and their timings are consistent. In order to ensure the timing sequence of all interfaces to be uniform and save the pin resources of the CPLD3, a separate CPLD3 pin is not generally used for outputting all delay RESET signals, but is distributed to a plurality of external sockets in a buffer-expansion manner, wherein only one RESET signal is shown in the figure.

For the intelligent card interface with delay 1s, we define the ID as [11111111], and the baseboard management controller BMC reads the ID information on the PCA9554 on the patch panel 1 through I2C. When the BMC recognizes that the PCI-E card connected with the adapter card is an intelligent network card needing special RESET delay, the BMC sends a delay strategy of 1s to the CPLD3 through the SGPMI interface, a register in the CPLD3 receives the signal, the triggering interface CPLD _ RESET _ SEL outputs a delay gating signal to enable the position of a gating SEL pin of the single-pole double-throw switch 5 to be high, the RESET signal output port A of the delay resetting signal is gated to the second delay resetting signal interface B2 by searching a truth table of the single-pole double-throw switch, the RESET signal which is output by the CPLD3 and meets the 100ms delay of standard PCI-E card resetting enters the delay resetting signal interface B2 through a delay line and is output to the PCI-E slot through the delay signal output port A, and then the intelligent network card resetting time sequence of PERST delay 1s is provided.

As a preferred embodiment, as shown in fig. 2, a delay generating circuit 6 provided in an embodiment of the present application includes:

an RC delay line 601 electrically connected to the standard delay signal generator 302; the RC delay line 601 can change the delay time by capacitance and resistance, thereby implementing different delay strategies for different PCI-E devices; a delayed reset signal flip-flop 602 connected to the RC delay line 601, wherein the delayed reset signal flip-flop 602 is further electrically connected to the second delayed reset signal interface. The delay reset signal flip-flop 602 can generate a corresponding delay reset signal according to the delay time changed by the RC delay line 601, thereby performing delay management on PCI-E devices with different delays. In the embodiment of the application, a Schmitt trigger can be selected to shape the delay reset signal.

As a preferred embodiment, as shown in fig. 2, the RC delay line 601 includes:

a delay voltage converter 6011 electrically connected to the standard delay signal generator 302;

a delay voltage generator 6012 electrically connected to the delay voltage converter 6011, the delay voltage generator 6012 being further electrically connected to the delayed reset signal flip-flop 602.

Among them, in the embodiments of the present application, R1 ═ 806Kohm, C1 ═ 1uF, and C2 ═ 1uF are selected. The delay time of a PCI-E device can be derived from t ═ R × C × ln ((E-V)/E); wherein: the resistor R and the capacitor C are connected in series, the unit of R is ohm, and the unit of C is F; e is the voltage between the series resistor and the capacitor, and V is the voltage to be achieved between the capacitors. The Schmitt trigger is selected to be the SN74LVC1G17DCKR of TI. By providing the delay voltage generator 6012, the delay voltage converter 6011 is changed, which can change the voltage E between the series resistance and the capacitance, thereby changing the delay time t.

As a preferred embodiment, the server interface management structure further includes: and a mainboard 7 fixed with the adapter board 1, the baseboard management controller 2 and the CPLD 3.

As a preferred embodiment, the server interface management structure further includes: and the power supply 8 is electrically connected with the adapter board 1, the substrate management controller 2 and the CPLD3 respectively.

In addition, as shown in fig. 3, the present invention further provides a server interface management method for a PCI-E device, where the method is used in the server interface management structure according to any of the foregoing embodiments, and as shown in fig. 3, the server interface management method includes:

s110: identifying PCI-E equipment connected with a PCI-E slot and generating a board card ID signal;

s120: generating a delay strategy corresponding to the PCI-E equipment according to the board card ID signal;

s130: and generating and sending a delay reset signal corresponding to the PCI-E equipment to the PCI-E slot according to the delay strategy.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. a server interface management structure of PCI-E equipment, is characterized in that, comprises:

An adapter board (1) for accessing a PCI-E device, wherein the adapter board (1) includes a PCI-E slot (101) and an ID identification module (102); the ID identification module (102) ), for identifying the PCI-E device connected by the PCI-E slot (101), and generating the board ID signal;

A baseboard management controller (2) connected to the adapter board (1), for generating a delay policy corresponding to the PCI-E device according to the board ID signal generated by the ID identification module (102);

The CPLD (3) electrically connected to the baseboard management controller (2) is configured to generate and send the delay corresponding to the PCI-E device to the PCI-E slot (101) according to the delay policy reset signal.

2. The server interface management structure according to claim 1, wherein the ID identification module (102) comprises:

an ID identification chip connected to the PCI-E slot (101) for identifying the PCI-E device connected to the PCI-E slot (101);

An IO pin connected to the ID identification chip, the IO pin is also electrically connected to the baseboard management controller (2) for generating a board card ID signal and sending it to the baseboard management controller (2) .

3. The server interface management structure according to claim 1, characterized in that, the adapter board (1) further comprises an electrical connection with the PCI-E slot (101) and the ID identification module (102) respectively. connected conductive contacts (103);

An adapter board connector (4) electrically connected to the adapter board (1) through the conductive contacts (103), wherein the adapter board connector (4) is also connected to the baseboard management controller (2) Electrical connection.

4. The server interface management structure according to claim 1, characterized in that further comprising a SPDT switch (5) electrically connected to the CPLD (3), the SPDT switch (5) comprising:

A delay gating switch interface (501) electrically connected to the delay strategy register (301) of the CPLD (3), for gating the corresponding delay reset signal interface according to the delay gating signal sent by the CPLD (3) ;

a first delay reset signal interface electrically connected to the standard delay signal generator (302) of the CPLD (3);

A second delay reset signal interface electrically connected to the standard delay signal generator (302) through a delay generating circuit (6);

and a delayed reset signal output port electrically connected to the first delayed reset signal interface and the second delayed reset signal interface respectively, and the delayed reset signal output port is also electrically connected to the PCI-E slot (101) connect.

5. The server interface management structure according to claim 4, wherein the delay generating circuit (6) comprises:

an RC delay line (601) electrically connected to the standard delay signal generator (302);

A delayed reset signal flip-flop (602) connected to the RC delay line (601), wherein the delayed reset signal flip-flop (602) is also electrically connected to the second delayed reset signal interface.

6. The server interface management structure according to claim 1, wherein the RC delay line (601) comprises:

a delay voltage converter (6011) electrically connected to the standard delay signal generator (302);

A delay voltage generator (6012) electrically connected to the delay voltage converter (6011), the delay voltage generator (6012) is also electrically connected to a delay reset signal flip-flop (602).

7. The server interface management structure according to claim 1, further comprising:

The adapter board (1), the baseboard management controller (2) and the main board (7) of the CPLD (3) are fixed.

8. The server interface management structure according to claim 1, characterized in that, further comprising: respectively electrically connected to the adapter board (1), the baseboard management controller (2) and the CPLD (3) power supply (8).

9. A server interface management method of a PCI-E device, wherein the method is used in the server interface management structure described in any one of claims 1-8, and the server interface management method comprises:

Identify PCI-E devices connected to PCI-E slots and generate board ID signals;

Generate a delay policy corresponding to the PCI-E device according to the board ID signal;

According to the delay policy, a delayed reset signal corresponding to the PCI-E device is generated and sent to the PCI-E slot.