CN113676185A - Virtual second-order delta-sigma modulator circuit based on differential difference amplifier - Google Patents
Virtual second-order delta-sigma modulator circuit based on differential difference amplifier Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
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Abstract
A virtual second-order delta-sigma modulator circuit based on a differential difference amplifier relates to the technical field of integrated circuits and mainly comprises a differential difference operational amplifier A1, feedback capacitors C9, C10, C11 and C12, sampling capacitors C1, C2, C5 and C6, integrating capacitors C3, C4, C7 and C8, switches S1-S48 and a comparator. By adopting an amplifier multiplexing technology, the function of the two-stage integrator can be realized by using the two-stage integrator to share the same amplifier, and the power consumption and the area of the circuit are optimized. However, the charge injection effect can generate errors between the integrating capacitors C3 and C7, so that noise and harmonic components are increased, therefore, the invention proposes to replace the traditional amplifier in the amplifier multiplexing circuit by adopting a differential difference amplifier, and realizes mutual isolation between the sharing input ports of the integrating capacitors and the multiplexing amplifier in the integrator under the control of a certain logic signal, thereby reducing the influence of the charge injection effect and improving the circuit precision.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a virtual second-order delta-sigma modulator circuit based on a differential difference amplifier.
Background
An analog-to-digital converter (ADC) is a key for connecting the analog domain and the digital domain and mainly comprises a modulator and a down-sampling decimation filter. The delta-sigma modulator has oversampling and noise shaping characteristics, and is mainly applied to the fields of low speed and high precision, such as high-quality audio equipment, precision instrument equipment, sensor interfaces, biological signal measurement and the like. The power consumption of the delta-sigma modulator mainly comes from the amplifier module in each stage of the integrator, and the large power consumption means a larger area.
Fig. 1 shows a conventional second-order switched capacitor delta-sigma modulator circuit, which is composed of two operational amplifiers a1, a2, sampling capacitors C1, C2, C5, C6, integrating capacitors C3, C4, C7, C8, feedback capacitors C9, C10, C11, C12, switches S1 to S36, and a comparator. C1-C2-Cs 1, C3-C4-Ci 1, C5-C6-Cs 2, C7-C8-Ci 2, C9-C10-Cfb 1, and C11-C12-Cfb 2. The circuit signal includes: the differential signal Vip and Vin are input, the feedback reference signal is Vrefp, Vrefn, Vrefp is equal to a power supply voltage, Vrefn is equal to a ground voltage, the common mode signal is VCM and is equal to one half of the power supply voltage, the two-phase nonoverlapping clock control signal is clk1, clk1d, clk2, clk2d (frequency is Fs and duty ratio is 50%), the feedback clock signal is clk1n, clk1p, and the digital output signal is Dop and Don. The input clock mainly controls the working state of the circuit, the feedback clock signal is realized by output signals Dop, Don and a clock signal clk1 through a certain logic relationship, when the signal is high, the switch is in a connected state, and when the signal is low, the switch is in an disconnected state.
The clock timing relationship of fig. 2 and the circuit connection relationship of fig. 1 show that:
when clk1, clk1d are high and clk2, clk2d are low, the input signal Vip is sampled by the sampling capacitor C1, and the charge of the sampling capacitor C1 may be represented as QC1,clk1Cs1(Vip-VCM), when clk2, clk2d are high and clk1, clk1d are low, the charge of sampling capacitor C1 may be represented as QC1,clk2Cs1(VCM-VCM), the charge transferred from the sampling capacitor C1 to the integrating capacitor C3 is therefore Δ Q — QC1,clk1-QC1,clk2Thus, the voltage variation at the Vop terminal can be expressed as
Similarly, the voltage variation at Von terminal can be expressed as
Thus, the differential output voltage variation of the first stage integrator can be expressed as
After the sampling capacitor C1 of the first stage integrator transfers charges to the integrating capacitor C3, when clk1, clk1d are high and clk2, clk2d are low, the sampling capacitor C5 samples the output signal Vop of the first stage integrator, and the charge of the sampling capacitor C5 can be represented as Q5C5,clk1Cs2 (Vop-VCM); when clk2, clk2d are high and clk1, clk1d are low, the charge on C5 on the sampling capacitance may be represented as QC5,clk2Cs2(VCM-VCM), the charge transferred from the sampling capacitor C5 to the integrating capacitor C7 is therefore Δ Q — QC5,clk1-QC5,clk2The voltage variation at Vop1 terminal can be expressed as
Similarly, the voltage variation of the available Von1 terminal can be expressed as
Thus, the differential output voltage variation of the second stage integrator can be expressed as
The comparator compares the output signals (Vop1, Von1) of the second-stage integrator, outputs digital signals and drives the feedback clock to feed back. To achieve higher accuracy, the capacitance needs to be increased to reduce noise, but the amplifier needs to consume more power to drive the capacitance.
Disclosure of Invention
The invention provides a virtual second-order delta-sigma modulator circuit based on a differential difference amplifier. Therefore, by adopting an amplifier multiplexing technology, the function of the two-stage integrator can be realized by using the two-stage integrator to share the same amplifier, and the power consumption and the area of the circuit are optimized. However, the charge injection effect can generate errors between the integrating capacitors C3 and C7, so that noise and harmonic components are increased, therefore, the invention proposes to replace the traditional amplifier in the amplifier multiplexing circuit by adopting a differential difference amplifier, and realizes mutual isolation between the sharing input ports of the integrating capacitors and the multiplexing amplifier in the integrator under the control of a certain logic signal, thereby reducing the influence of the charge injection effect and improving the circuit precision.
In order to achieve the purpose, the invention adopts the technical scheme that:
a virtual second-order delta-sigma modulator circuit based on a differential difference amplifier is mainly composed of a differential difference operational amplifier A1, sampling capacitors C1, C2, C5 and C6, integrating capacitors C3, C4, C7 and C8, feedback capacitors C9, C10, C11 and C12, switches S1-S48 and a comparator Comp; the signals of the circuit include: the differential input signals are Vip and Vin, the feedback reference signals are Vrefp and Vrefn, the Vrefp is equal to a power supply voltage, the Vrefn is equal to a ground voltage of a circuit, the common-mode signal is VCM and is equal to one half of the power supply voltage, the two non-overlapped clock signals are clk1, clk1d, clk2 and clk2d, the feedback clock signals are clk1n, clk2n, clk1p and clk2p, and the digital output signals are Dop and Don; the working state of the clock control circuit is input, the feedback clock signal is realized by certain logic relation between output signals Dop and Don and clock signals clk1 and clk2, when the signal is high, the switch is in a connected state, and when the signal is low, the switch is in an disconnected state.
In the circuit of the present invention, C1-C2-Cs 1, C3-C4-Ci 1, C5-C6-Cs 2, C7-C8-Ci 2, C9-C10-Cfb 1, and C11-C12-Cfb 2.
Furthermore, one end of a first-stage integrator sampling capacitor C1 is connected with the switches S1 and S3, and the other end of the sampling capacitor C1 is connected with the switches S5 and S7; one end of a first-stage integrator sampling capacitor C2 is connected with the switches S2 and S4, and the other end of the sampling capacitor C2 is connected with the switches S6 and S8; one end of a second-stage integrator sampling capacitor C5 is connected with the switches S15 and S17, and the other end of the sampling capacitor C5 is connected with the switches S19 and S21; one end of a second-stage integrator sampling capacitor C6 is connected with the switches S16 and S18, and the other end of the sampling capacitor C6 is connected with the switches S20 and S22.
Furthermore, one end of the integrating capacitor C3 of the first stage integrator is connected with the switch S11, and the other end of the integrating capacitor C3 is connected with the switch S13; one end of the first-stage integrator integrating capacitor C4 is connected with the switch S12, and the other end of the integrating capacitor C4 is connected with the switch S14; one end of an integrating capacitor C7 of the second-stage integrator is connected with a switch S25, and the other end of the integrating capacitor C7 is connected with a switch S27 and the positive input end of the comparator; one end of the second stage integrator integrating capacitor C8 is connected with the switch S26, and the other end of the integrating capacitor C8 is connected with the switch S28 and the inverting input end of the comparator.
Furthermore, one end of the first stage integrator feedback capacitor C9 is connected to the switches S29, S31 and S33, and the other end of the feedback capacitor C9 is connected to the switches S35 and S37; one end of a first-stage integrator feedback capacitor C10 is connected with switches S30, S32 and S34, and the other end of the feedback capacitor C10 is connected with switches S36 and S38; one end of a second-stage integrator feedback capacitor C11 is connected with switches S39, S41 and S43, and the other end of an integrating capacitor C11 is connected with switches S45 and S47; one end of the second stage integrator feedback capacitor C12 is connected with the switches S40, S42 and S44, and the other end of the integrating capacitor C12 is connected with the switches S46 and S48.
Furthermore, an input end vpp1 of the differential operational amplifier a1 is connected to the switches S7, S9, S11 and S37, an input end vpn1 of the differential operational amplifier a1 is connected to the switches S8, S10, S12 and S38, an input end vpn1 of the differential operational amplifier a1 is connected to the switches S21, S23, S25 and S47, an input end vnn1 of the differential operational amplifier a1 is connected to the switches S22, S24, S26 and S48, a negative output end of the differential operational amplifier a1 is connected to the switches S13 and S27, and a positive output end of the differential operational amplifier a1 is connected to the switches S14 and S28.
Furthermore, the positive input end of the comparator is connected with the right end of the capacitor C7 and the switch S27, and the negative input end of the comparator is connected with the right end of the capacitor C8 and the switch S28.
Further, the two non-overlapping clock signals clk1, clk1d, clk2 and clk2d have a frequency Fs and a duty cycle of 50%.
The invention has the technical effects that: the second-order delta-sigma modulator provided by the invention adopts an amplifier multiplexing technology, realizes the function of a second-order integrator by adopting one amplifier, realizes the mutual isolation between an integrating capacitor in the integrator and a shared input port of a multiplexing amplifier by adopting a differential difference amplifier to replace the traditional amplifier, eliminates the non-ideal factors introduced by the amplifier multiplexing to a certain extent, improves the circuit precision and reduces the power consumption and the area of the circuit.
Drawings
Fig. 1 shows a conventional second-order delta-sigma modulator circuit in the background art.
Fig. 2 is a timing diagram illustrating the operation of a conventional second-order delta-sigma modulator in the prior art.
Fig. 3 is a circuit of a virtual second-order delta-sigma modulator based on a differential difference amplifier according to the present invention.
Fig. 4 is a timing diagram illustrating the operation of the second order delta-sigma modulator according to the present invention.
Fig. 5 is a differential difference amplifier circuit used in the present invention.
Fig. 6 shows the FFT simulation result of the second order modulator designed by the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
fig. 3 shows a differential amplifier-based virtual second-order delta-sigma modulator circuit, which is mainly composed of a differential operational amplifier a1, sampling capacitors C1, C2, C5, C6, integrating capacitors C3, C4, C7, C8 feedback capacitors C9, C10, C11, C12, switches S1 to S48, and a comparator. C1-C2-Cs 1, C3-C4-Ci 1, C5-C6-Cs 2, C7-C8-Ci 2, C9-C10-Cfb 1, and C11-C12-Cfb 2. The signals of the circuit include: the differential input signal is Vip, Vin, the feedback reference signal is Vrefp, Vrefn, Vrefp is equal to the power voltage, Vrefn is equal to the ground voltage of the circuit, the common mode signal is VCM, and is equal to one half of the power voltage, the two-term non-overlapping clock signals are clk1, clk1d, clk2, clk2d (frequency is Fs, duty ratio is 50%), the feedback clock signals are clk1n, clk2n, clk1p, clk2p, and the digital output signal is Dop, Don. The input clock mainly controls the working state of the circuit, the feedback clock signal is realized by certain logic relation between the output signals Dop and Don and the clock signals clk1 and clk2, when the signal is high, the switch is in a connected state, and when the signal is low, the switch is in an disconnected state.
The connection relationship of the virtual second-order delta-sigma modulator circuit based on the differential difference amplifier provided by the invention in figure 3 is as follows: one end of a first-stage integrator sampling capacitor C1 is connected with the switches S1 and S3, and the other end of the sampling capacitor C1 is connected with the switches S5 and S7. One end of a first-stage integrator sampling capacitor C2 is connected with the switches S2 and S4, and the other end of the sampling capacitor C2 is connected with the switches S6 and S8. One end of the first-stage integrator integrating capacitor C3 is connected with the switch S11, and the other end of the integrating capacitor C3 is connected with the switch S13. One end of the first-stage integrator integrating capacitor C4 is connected with the switch S12, and the other end of the integrating capacitor C4 is connected with the switch S14. One end of a second-stage integrator sampling capacitor C5 is connected with the switches S15 and S17, and the other end of the sampling capacitor C5 is connected with the switches S19 and S21. One end of a second-stage integrator sampling capacitor C6 is connected with the switches S16 and S18, and the other end of the sampling capacitor C6 is connected with the switches S20 and S22. One end of the second stage integrator integrating capacitor C7 is connected with the switch S25, and the other end of the integrating capacitor C7 is connected with the switch S27 and the positive input end of the comparator. One end of the second stage integrator integrating capacitor C8 is connected with the switch S26, and the other end of the integrating capacitor C8 is connected with the switch S28 and the inverting input end of the comparator. One end of the first stage integrator feedback capacitor C9 is connected with the switches S29, S31 and S33, and the other end of the feedback capacitor C9 is connected with the switches S35 and S37. One end of the first stage integrator feedback capacitor C10 is connected with the switches S30, S32 and S34, and the other end of the feedback capacitor C10 is connected with the switches S36 and S38. One end of the second stage integrator feedback capacitor C11 is connected with the switches S39, S41 and S43, and the other end of the integrating capacitor C11 is connected with the switches S45 and S47. One end of the second stage integrator feedback capacitor C12 is connected with the switches S40, S42 and S44, and the other end of the integrating capacitor C12 is connected with the switches S46 and S48. An input end vpp1 of the differential operational difference amplifier A1 is connected with the switches S7, S9, S11 and S37, an input end vpn1 of the differential operational difference amplifier A1 is connected with the switches S8, S10, S12 and S38, an input end vpn1 of the differential operational difference amplifier A1 is connected with the switches S21, S23, S25 and S47, an input end vnn1 of the differential operational difference amplifier A1 is connected with the switches S22, S24, S26 and S48, a negative output end of the differential operational difference amplifier A1 is connected with the switches S13 and S27, and a positive output end of the differential operational difference amplifier A1 is connected with the switches S14 and S28. The positive input end of the comparator is connected with the right end of the capacitor C7 and the switch S27, and the negative input end of the comparator is connected with the right end of the capacitor C8 and the switch S28. The switch S1 has one end connected to the input signal Vip and the other end connected to the switch S3 and the capacitor C1. The switch S2 has one end connected to the input signal Vin and the other end connected to the switch S4 and the capacitor C2. One end of the switch S3 is connected to the common mode signal VCM, and the other end is connected to the switch S1 and the capacitor C1. One end of the switch S4 is connected to the common mode signal VCM, and the other end is connected to the switch S2 and the capacitor C2. One end of the switch S5 is connected to the common mode signal VCM, and the other end is connected to the switch S7 and the capacitor C1. One end of the switch S6 is connected to the common mode signal VCM, and the other end is connected to the switch S8 and the capacitor C2. The switch S7 has one end connected to the switch S5 and the capacitor C1 and the other end connected to the switches S9, S11, S37 and the amplifier input Vpp 1. The switch S8 has one end connected to the switch S6 and the capacitor C2 and the other end connected to the switches S10, S12, S38 and the amplifier input Vpn 1. The switch S9 has one end connected to the common mode signal VCM and the other end connected to the switches S7, S11, S37 and the amplifier input Vpp 1. The switch S10 has one end connected to the common mode signal VCM and the other end connected to the switches S8, S12, S38 and the amplifier input terminal Vpn 1. The switch S11 has one end connected to the switches S7, S9, and S37 and the amplifier input Vpp1, and the other end connected to the capacitor C3. The switch S12 has one end connected to the switches S8, S10, and S38 and the amplifier input terminal Vpn1, and the other end connected to the capacitor C4. One end of the switch S13 is connected with the capacitor C3, and the other end is connected with the switch S27 and the negative output end of the amplifier. One end of the switch S14 is connected with the capacitor C4, and the other end is connected with the switch S28 and the positive output end of the amplifier. One end of the switch S15 is connected with the negative output end of the amplifier, and the other end is connected with the switch S17 and the capacitor C5. One end of the switch S16 is connected with the positive output end of the amplifier, and the other end is connected with the switch S18 and the capacitor C6. One end of the switch S17 is connected to the common mode signal VCM, and the other end is connected to the switch S15 and the capacitor C5. One end of the switch S18 is connected to the common mode signal VCM, and the other end is connected to the switch S16 and the capacitor C6. One end of the switch S19 is connected to the common mode signal VCM, and the other end is connected to the switch S21 and the capacitor C5. One end of the switch S20 is connected to the common mode signal VCM, and the other end is connected to the switch S22 and the capacitor C6. The switch S21 has one end connected to the switch S19 and the capacitor C5, and the other end connected to the switch S23, the switch S25, the switch S47, and the amplifier input Vnp 1. The switch S22 has one end connected to the switch S20 and the capacitor C6, and the other end connected to the switch S24, the switch S26, the switch S48, and the amplifier input Vnn 1. Switch S23 has one end connected to common mode signal VCM and the other end connected to switch S21, switch S25, switch S47 and amplifier input Vnp 1. Switch S24 has one end connected to common mode signal VCM and the other end connected to switch S22, switch S26, switch S48 and amplifier input Vnn 1. The switch S25 has one end connected to the switch S21, the switch S23, the switch S47, and the amplifier input Vnp1, and the other end connected to the capacitor C7. One end of the switch S26 is connected with S22, the switch S24, the switch S48 and the amplifier input end Vnn1, and the other end is connected with the capacitor C8. One end of the switch S27 is connected with the S13 and the negative output end of the amplifier, and the other end is connected with the capacitor C7 and the positive input end of the comparator. One end of the switch S28 is connected with the S14 and the positive output end of the amplifier, and the other end is connected with the capacitor C8 and the negative input end of the comparator. The switch S29 has one end connected to the feedback signal Vrefp and the other end connected to the switch S31, the switch S33 and the capacitor C9. The switch S30 has one end connected to the feedback signal Vrefp and the other end connected to the switch S32, the switch S34 and the capacitor C10. The switch S31 has one end connected to the feedback signal Vrefn and the other end connected to the switch S29, the switch S33 and the capacitor C9. The switch S32 has one end connected to the feedback signal Vrefn and the other end connected to the switch S30, the switch S34 and the capacitor C10. One end of the switch S33 is connected to the common mode signal VCM, and the other end is connected to the switch S29, the switch S31 and the capacitor C9. One end of the switch S34 is connected to the common mode signal VCM, and the other end is connected to the switch S30, the switch S32 and the capacitor C10. One end of the switch S35 is connected to the common mode signal VCM, and the other end is connected to the switch S37 and the capacitor C9. One end of the switch S36 is connected to the common mode signal VCM, and the other end is connected to the switch S38 and the capacitor C10. The switch S37 has one end connected to the switch S35 and the capacitor C9 and the other end connected to the switches S7, S9, S11 and the amplifier input Vpp 1. The switch S38 has one end connected to the switch S36 and the capacitor C10 and the other end connected to the switches S8, S10, S12 and the amplifier input Vpn 1. The switch S39 has one end connected to the feedback signal Vrefp and the other end connected to the switches S41, S43 and the capacitor C11. The switch S40 has one end connected to the feedback signal Vrefp and the other end connected to the switches S42, S44 and the capacitor C12. The switch S41 has one end connected to the feedback signal Vrefn and the other end connected to the switches S39, S43 and the capacitor C11. The switch S42 has one end connected to the feedback signal Vrefn and the other end connected to the switches S40, S44 and the capacitor C12. One end of the switch S43 is connected to the common mode signal VCM, and the other end is connected to the switches S39, S41 and the capacitor C11. One end of the switch S44 is connected to the common mode signal VCM, and the other end is connected to the switches S40, S42 and the capacitor C12. One end of the switch S45 is connected to the common mode signal VCM, and the other end is connected to the switch S47 and the capacitor C11. One end of the switch S46 is connected to the common mode signal VCM, and the other end is connected to the switch S48 and the capacitor C12. The switch S47 has one end connected to the switch S45 and the capacitor C11, and the other end connected to the switches S21, S23, S25 and the amplifier input Vnp 1. The switch S48 has one end connected to the switch S46 and the capacitor C12 and the other end connected to the switches S22, S24, S26 and the amplifier input Vnn 1.
The difference between the circuit of the invention and the circuit of the background art is that:
(1) compared with the circuit in the prior art, the circuit adopts an amplifier multiplexing technology to realize the circuit structure of the second-order modulator of a single amplifier.
(2) The invention adopts the differential difference amplifier to replace the traditional amplifier in the amplifier multiplexing circuit, and realizes the high-resolution second-order modulator structure through a certain logic control relation.
From the clock timing relationship of fig. 4 and the circuit connection relationship of fig. 3, it can be seen that:
when clk1, clk1d are high and clk2, clk2d are low, the input signal Vip is sampled by the sampling capacitor C1, and the charge on the sampling capacitor C1 may be represented as QC1,clk1When clk2, clk2d are high and clk1, clk1d are low, the charge on the sampling capacitor C1 may be represented as Q1 (Vip-VCM)C1,clk2Cs1(VCM-VCM), the charge C3 transferred from the sampling capacitor C1 to the integrating capacitor is therefore Δ Q — QC1,clk1-QC1,clk2Therefore, the voltage variation at the Vop1 terminal can be tabulatedShown as
Similarly, the voltage variation at Von1 terminal can be expressed as
Thus, the differential output voltage variation of the first stage integrator can be expressed as
While the first stage integrator sampling capacitor C1 is transferring charge to the integrating capacitor C3, the second stage integrator sampling capacitor C5 samples the output of the first stage integrator, so when clk2, clk2d are high and clk1, clk1d are low, the charge on the sampling capacitor C5 can be represented as QC5,clk2Cs2(Vop 1-VCM). When clk1, clk1d are high and clk2, clk2d are low, the charge on the sampling capacitor C5 may be represented as QC5,clk1Cs2 (VCM-VCM). Therefore, the charge transferred from the sampling capacitor C5 to the integrating capacitor C7 is Δ Q ═ QC5,clk2-QC5,clk1The voltage variation at Vop2 terminal can be expressed as
Similarly, the voltage variation at Von2 terminal can be expressed as
Thus, the differential output voltage variation of the second stage integrator can be expressed as
The comparator compares the second stage integrator differential output signals (Vop2, Von2), outputs digital signals and drives the feedback clock for feedback. Therefore, under the control of a simple two-phase non-overlapping clock, the working logic of the circuit is adjusted, and the function of a second-order integrator can be realized by only using one operational amplifier.
As shown in fig. 5, the differential difference amplifier used in the present invention has two pairs of differential inputs VIP, VIN and VIP1, VIN1, VDD, VSS being power and ground, respectively, VB1 and VB2 being bias signals, VCMFB being common mode feedback signals, VOP, VON being output signals. When one of the integrators is in an integration state, the input end of the other integrator is controlled to be a common-mode level VCM, so that mutual isolation between an integration capacitor in the integrator and a shared input port of the multiplexing amplifier is realized, errors generated between the integration capacitors C3 and C7 due to charge injection are avoided, noise and harmonic components are reduced, and the multiplexing influence of the amplifier is eliminated to a certain extent.
Fig. 6 shows the FFT simulation result of the second-order modulator designed in the present invention, when the input signal frequency is 73.2421875Hz, the sampling frequency is 200K Hz, the number of sampling points is 16384, and the bandwidth is 250Hz, the signal-to-noise-and-distortion ratio SNDR obtained by simulation is 86dB, and the effective number ENOB is 14 bits.
Claims (9)
1. A virtual second-order delta-sigma modulator circuit based on a differential difference amplifier is characterized in that: the differential operational amplifier mainly comprises a differential operational amplifier A1, sampling capacitors C1, C2, C5 and C6, integrating capacitors C3, C4, C7 and C8, feedback capacitors C9, C10, C11 and C12, switches S1-S48 and a comparator Comp; the signals of the circuit include: the differential input signals are Vip and Vin, the feedback reference signals are Vrefp and Vrefn, the Vrefp is equal to a power supply voltage, the Vrefn is equal to a ground voltage of a circuit, the common-mode signal is VCM and is equal to one half of the power supply voltage, the two non-overlapped clock signals are clk1, clk1d, clk2 and clk2d, the feedback clock signals are clk1n, clk2n, clk1p and clk2p, and the digital output signals are Dop and Don; the working state of the clock control circuit is input, the feedback clock signal is realized by certain logic relation between output signals Dop and Don and clock signals clk1 and clk2, when the signal is high, the switch is in a connected state, and when the signal is low, the switch is in an disconnected state.
2. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: one end of a first-stage integrator sampling capacitor C1 is connected with the switches S1 and S3, and the other end of the sampling capacitor C1 is connected with the switches S5 and S7; one end of a first-stage integrator sampling capacitor C2 is connected with the switches S2 and S4, and the other end of the sampling capacitor C2 is connected with the switches S6 and S8; one end of a second-stage integrator sampling capacitor C5 is connected with the switches S15 and S17, and the other end of the sampling capacitor C5 is connected with the switches S19 and S21; one end of a second-stage integrator sampling capacitor C6 is connected with the switches S16 and S18, and the other end of the sampling capacitor C6 is connected with the switches S20 and S22.
3. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: one end of the first-stage integrator integrating capacitor C3 is connected with the switch S11, and the other end of the integrating capacitor C3 is connected with the switch S13; one end of the first-stage integrator integrating capacitor C4 is connected with the switch S12, and the other end of the integrating capacitor C4 is connected with the switch S14; one end of an integrating capacitor C7 of the second-stage integrator is connected with a switch S25, and the other end of the integrating capacitor C7 is connected with a switch S27 and the positive input end of the comparator; one end of the second stage integrator integrating capacitor C8 is connected with the switch S26, and the other end of the integrating capacitor C8 is connected with the switch S28 and the inverting input end of the comparator.
4. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: one end of a first-stage integrator feedback capacitor C9 is connected with switches S29, S31 and S33, and the other end of the feedback capacitor C9 is connected with switches S35 and S37; one end of a first-stage integrator feedback capacitor C10 is connected with switches S30, S32 and S34, and the other end of the feedback capacitor C10 is connected with switches S36 and S38; one end of a second-stage integrator feedback capacitor C11 is connected with switches S39, S41 and S43, and the other end of an integrating capacitor C11 is connected with switches S45 and S47; one end of the second stage integrator feedback capacitor C12 is connected with the switches S40, S42 and S44, and the other end of the integrating capacitor C12 is connected with the switches S46 and S48.
5. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: an input end vpp1 of the differential operational difference amplifier A1 is connected with the switches S7, S9, S11 and S37, an input end vpn1 of the differential operational difference amplifier A1 is connected with the switches S8, S10, S12 and S38, an input end vpn1 of the differential operational difference amplifier A1 is connected with the switches S21, S23, S25 and S47, an input end vnn1 of the differential operational difference amplifier A1 is connected with the switches S22, S24, S26 and S48, a negative output end of the differential operational difference amplifier A1 is connected with the switches S13 and S27, and a positive output end of the differential operational difference amplifier A1 is connected with the switches S14 and S28.
6. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: the positive input end of the comparator is connected with the right end of the capacitor C7 and the switch S27, and the negative input end of the comparator is connected with the right end of the capacitor C8 and the switch S28.
7. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: one end of the switch S1 is connected with the input signal Vip, and the other end is connected with the switch S3 and the capacitor C1; one end of the switch S2 is connected with the input signal Vin, and the other end is connected with the switch S4 and the capacitor C2; one end of the switch S3 is connected with the common-mode signal VCM, and the other end is connected with the switch S1 and the capacitor C1; one end of the switch S4 is connected with the common-mode signal VCM, and the other end is connected with the switch S2 and the capacitor C2; one end of the switch S5 is connected with the common-mode signal VCM, and the other end is connected with the switch S7 and the capacitor C1; one end of the switch S6 is connected with the common-mode signal VCM, and the other end is connected with the switch S8 and the capacitor C2; one end of the switch S7 is connected with the switch S5 and the capacitor C1, and the other end is connected with the switches S9, S11, S37 and the amplifier input end Vpp 1; one end of the switch S8 is connected with the switch S6 and the capacitor C2, and the other end is connected with the switches S10, S12, S38 and the amplifier input end Vpn 1; one end of the switch S9 is connected with the common-mode signal VCM, and the other end is connected with the switches S7, S11 and S37 and the amplifier input end Vpp 1; one end of the switch S10 is connected with the common-mode signal VCM, and the other end is connected with the switches S8, S12 and S38 and the amplifier input end Vpn 1; one end of the switch S11 is connected with the switches S7, S9 and S37 and the amplifier input end Vpp1, and the other end is connected with the capacitor C3; one end of the switch S12 is connected with the switches S8, S10 and S38 and the amplifier input end Vpn1, and the other end is connected with the capacitor C4; one end of the switch S13 is connected with the capacitor C3, and the other end is connected with the switch S27 and the negative output end of the amplifier; one end of the switch S14 is connected with the capacitor C4, and the other end is connected with the switch S28 and the positive output end of the amplifier; one end of the switch S15 is connected with the negative output end of the amplifier, and the other end is connected with the switch S17 and the capacitor C5; one end of the switch S16 is connected with the positive output end of the amplifier, and the other end is connected with the switch S18 and the capacitor C6; one end of the switch S17 is connected with the common-mode signal VCM, and the other end is connected with the switch S15 and the capacitor C5; one end of the switch S18 is connected with the common-mode signal VCM, and the other end is connected with the switch S16 and the capacitor C6; one end of the switch S19 is connected with the common-mode signal VCM, and the other end is connected with the switch S21 and the capacitor C5; one end of the switch S20 is connected with the common-mode signal VCM, and the other end is connected with the switch S22 and the capacitor C6; one end of the switch S21 is connected with the switch S19 and the capacitor C5, and the other end is connected with the switch S23, the switch S25, the switch S47 and the amplifier input end Vnp 1; one end of the switch S22 is connected with the switch S20 and the capacitor C6, and the other end is connected with the switch S24, the switch S26, the switch S48 and the amplifier input end Vnn 1; one end of the switch S23 is connected with the common-mode signal VCM, and the other end is connected with the switch S21, the switch S25, the switch S47 and the amplifier input end Vnp 1; one end of the switch S24 is connected with the common-mode signal VCM, and the other end is connected with the switch S22, the switch S26, the switch S48 and the amplifier input end Vnn 1; one end of the switch S25 is connected with the S21, the switch S23, the switch S47 and the amplifier input end Vnp1, and the other end is connected with the capacitor C7; one end of the switch S26 is connected with the S22, the switch S24, the switch S48 and the amplifier input end Vnn1, and the other end is connected with the capacitor C8; one end of the switch S27 is connected with the negative output end of the amplifier S13, and the other end is connected with the capacitor C7 and the positive input end of the comparator; one end of the switch S28 is connected with the S14 and the positive output end of the amplifier, and the other end is connected with the capacitor C8 and the negative input end of the comparator; one end of the switch S29 is connected with a feedback signal Vrefp, and the other end is connected with a switch S31, a switch S33 and a capacitor C9; one end of the switch S30 is connected with a feedback signal Vrefp, and the other end is connected with a switch S32, a switch S34 and a capacitor C10; one end of the switch S31 is connected with a feedback signal Vrefn, and the other end is connected with a switch S29, a switch S33 and a capacitor C9; one end of the switch S32 is connected with a feedback signal Vrefn, and the other end is connected with a switch S30, a switch S34 and a capacitor C10; one end of the switch S33 is connected with the common-mode signal VCM, and the other end is connected with the switch S29, the switch S31 and the capacitor C9; one end of the switch S34 is connected with the common-mode signal VCM, and the other end is connected with the switch S30, the switch S32 and the capacitor C10; one end of the switch S35 is connected with the common-mode signal VCM, and the other end is connected with the switch S37 and the capacitor C9; one end of the switch S36 is connected with the common-mode signal VCM, and the other end is connected with the switch S38 and the capacitor C10; one end of the switch S37 is connected with the switch S35 and the capacitor C9, and the other end is connected with the switches S7, S9, S11 and the amplifier input end Vpp 1; one end of the switch S38 is connected with the switch S36 and the capacitor C10, and the other end is connected with the switches S8, S10, S12 and the amplifier input end Vpn 1; one end of the switch S39 is connected with a feedback signal Vrefp, and the other end is connected with switches S41, S43 and a capacitor C11; one end of the switch S40 is connected with a feedback signal Vrefp, and the other end is connected with switches S42, S44 and a capacitor C12; one end of the switch S41 is connected with a feedback signal Vrefn, and the other end is connected with switches S39, S43 and a capacitor C11; one end of the switch S42 is connected with a feedback signal Vrefn, and the other end is connected with switches S40, S44 and a capacitor C12; one end of the switch S43 is connected with the common-mode signal VCM, and the other end is connected with the switches S39, S41 and the capacitor C11; one end of the switch S44 is connected with the common-mode signal VCM, and the other end is connected with the switches S40, S42 and the capacitor C12; one end of the switch S45 is connected with the common-mode signal VCM, and the other end is connected with the switch S47 and the capacitor C11; one end of the switch S46 is connected with the common-mode signal VCM, and the other end is connected with the switch S48 and the capacitor C12; one end of the switch S47 is connected with the switch S45 and the capacitor C11, and the other end is connected with the switches S21, S23 and S25 and an amplifier input end Vnp 1; the switch S48 has one end connected to the switch S46 and the capacitor C12 and the other end connected to the switches S22, S24, S26 and the amplifier input Vnn 1.
8. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: C1-C2-Cs 1, C3-C4-Ci 1, C5-C6-Cs 2, C7-C8-Ci 2, C9-C10-Cfb 1, and C11-C12-Cfb 2.
9. The differential difference amplifier based virtual second order delta-sigma modulator circuit of claim 1, wherein: the two non-overlapping clock signals clk1, clk1d, clk2, clk2d have a frequency Fs and a duty cycle of 50%.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114487615A (en) * | 2022-04-06 | 2022-05-13 | 基合半导体（宁波）有限公司 | Capacitance measuring circuit and capacitance measuring method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055477A (en) * | 2010-11-29 | 2011-05-11 | 复旦大学 | Amplitude-interleaving analog digital composite signal processing circuit |
| CN102270991A (en) * | 2010-06-07 | 2011-12-07 | 中国人民解放军国防科学技术大学 | Second-order time sharing multiplexing Delta-Sigma modulator |
| US20150123829A1 (en) * | 2013-11-06 | 2015-05-07 | Samsung Electronics Co., Ltd. | Apparatuses and method of switched-capacitor integrator |
| CN204831564U (en) * | 2013-09-05 | 2015-12-02 | 艾尔默斯半导体股份公司 | A device for moving passive form infrared detector |
| CN105634495A (en) * | 2014-11-13 | 2016-06-01 | 微电子中心德累斯顿有限公司 | Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters |
| CN106469974A (en) * | 2015-08-14 | 2017-03-01 | 英特希尔美国公司 | Reinforced switching type capacitor filter compensation in DC DC transducer |
| CN109787633A (en) * | 2018-12-24 | 2019-05-21 | 哈尔滨工程大学 | The Σ Δ ADC suitable for mixed type ADC structure with chopped wave stabilizing |
-
2021
- 2021-09-08 CN CN202111050470.5A patent/CN113676185B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270991A (en) * | 2010-06-07 | 2011-12-07 | 中国人民解放军国防科学技术大学 | Second-order time sharing multiplexing Delta-Sigma modulator |
| CN102055477A (en) * | 2010-11-29 | 2011-05-11 | 复旦大学 | Amplitude-interleaving analog digital composite signal processing circuit |
| CN204831564U (en) * | 2013-09-05 | 2015-12-02 | 艾尔默斯半导体股份公司 | A device for moving passive form infrared detector |
| US20150123829A1 (en) * | 2013-11-06 | 2015-05-07 | Samsung Electronics Co., Ltd. | Apparatuses and method of switched-capacitor integrator |
| CN105634495A (en) * | 2014-11-13 | 2016-06-01 | 微电子中心德累斯顿有限公司 | Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters |
| CN106469974A (en) * | 2015-08-14 | 2017-03-01 | 英特希尔美国公司 | Reinforced switching type capacitor filter compensation in DC DC transducer |
| CN109787633A (en) * | 2018-12-24 | 2019-05-21 | 哈尔滨工程大学 | The Σ Δ ADC suitable for mixed type ADC structure with chopped wave stabilizing |
Non-Patent Citations (2)
| Title |
|---|
| CLEMENS M. ZIERHOFER: "Analysis of a Switched-Capacitor SecondOrder Delta–Sigma Modulator Using Integrator Multiplexing" * |
| 徐肯;蔡敏;贺小勇;: "应用于宽带Δ-∑ ADC的多级运算放大器" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114487615A (en) * | 2022-04-06 | 2022-05-13 | 基合半导体（宁波）有限公司 | Capacitance measuring circuit and capacitance measuring method |
| CN114487615B (en) * | 2022-04-06 | 2022-08-30 | 基合半导体（宁波）有限公司 | Capacitance measuring circuit and capacitance measuring method |
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