CN113675094A - Inner lead layered manufacturing method of semiconductor frame - Google Patents
Inner lead layered manufacturing method of semiconductor frame Download PDFInfo
- Publication number
- CN113675094A CN113675094A CN202110891364.3A CN202110891364A CN113675094A CN 113675094 A CN113675094 A CN 113675094A CN 202110891364 A CN202110891364 A CN 202110891364A CN 113675094 A CN113675094 A CN 113675094A
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- Prior art keywords
- cutting
- wafer
- frame
- lead
- purity
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000005520 cutting process Methods 0.000 claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 18
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052709 silver Inorganic materials 0.000 claims abstract description 16
- 239000004332 silver Substances 0.000 claims abstract description 16
- 239000000084 colloidal system Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000465 moulding Methods 0.000 claims abstract description 12
- 238000007747 plating Methods 0.000 claims abstract description 12
- 239000000741 silica gel Substances 0.000 claims abstract description 12
- 229910002027 silica gel Inorganic materials 0.000 claims abstract description 12
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 11
- 239000010432 diamond Substances 0.000 claims abstract description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims abstract description 6
- 238000000576 coating method Methods 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 6
- 238000004140 cleaning Methods 0.000 claims description 27
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 5
- 239000001569 carbon dioxide Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 238000002791 soaking Methods 0.000 claims description 5
- 230000003068 static effect Effects 0.000 claims description 5
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 5
- 239000012498 ultrapure water Substances 0.000 claims description 5
- 238000005406 washing Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 238000003980 solgel method Methods 0.000 claims 1
- 238000007711 solidification Methods 0.000 claims 1
- 230000008023 solidification Effects 0.000 claims 1
- 239000005022 packaging material Substances 0.000 description 6
- VVTSZOCINPYFDP-UHFFFAOYSA-N [O].[Ar] Chemical compound [O].[Ar] VVTSZOCINPYFDP-UHFFFAOYSA-N 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
Abstract
The invention discloses a method for manufacturing an inner lead of a semiconductor frame in a layered manner, which comprises the following steps; step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer; secondly, coating silver colloid in a specified base island area of the lead frame, and mounting the separated crystal grains in the base island area; thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by using a high-purity metal wire through ultrasonic welding; step four, plastic packaging the product by using resin, and curing by using molding silica gel after the plastic packaging; removing redundant flash between the peripheral pins of the tube body after the Molding silica gel; and sixthly, plating a layer of plating layer on the surface of the frame, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent. The invention reduces the packaging difficulty and cost, improves the quality and reliability of products, enlarges the application range and can be applied to various fields.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a method for manufacturing an inner lead of a semiconductor frame in a layered mode.
Background
The semiconductor lead frame packaging is one of the main back-end processing procedures of the whole semiconductor component industrial chain, mainly aims at protecting a semiconductor silicon chip with a surface fully distributed with an integrated circuit from being corroded by external mechanical or chemical factors, and adopts the lead frame as a conducting medium, wherein the lead frame is generally made of copper or iron;
in the current semiconductor packaging process technology, the delamination inside the component is a significant quality defect. The lead frame packaging plastic packaging body is of a non-sealing type and is exposed in the air to easily absorb moisture in the air. When the plastic package body is subjected to high temperature of reflow soldering or wave soldering, the vapor pressure inside the plastic package body increases, and in a specific case, the internal pressure causes internal layers of the package body. Severe delamination causes electrical failure. For the failure, although the industry can manufacture the layering of the silver-plated area of the lead in the frame by adopting the plastic packaging material with high adhesive force, the cost of the plastic packaging material is high, and the mold sticking condition is easily generated in the plastic packaging operation process, so that the mold cleaning period has to be reduced and the mold cleaning cost is increased.
Disclosure of Invention
The invention aims to provide a method for manufacturing an inner lead of a semiconductor frame in a layered manner, which aims to solve the problems that in the prior art, the cost of a plastic package material is high, and the mold sticking condition is easily generated in the plastic package operation process, so that the mold cleaning period has to be reduced and the mold cleaning cost is increased.
In order to achieve the purpose, the invention provides the following technical scheme: a method for manufacturing an inner lead of a semiconductor frame in a layered manner comprises the following steps;
step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer;
secondly, coating silver colloid in a specified base island area of the lead frame, and mounting the separated crystal grains in the base island area;
thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by using a high-purity metal wire through ultrasonic welding;
step four, plastic packaging the product by using resin, and curing by using molding silica gel after the plastic packaging;
removing redundant flash between the peripheral pins of the tube body after the Molding silica gel;
and sixthly, plating a layer of plating layer on the surface of the frame by using a metal and chemical method, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent.
Preferably, in the first step, the cutting process:
s1, removing the debris generated by cutting by using ultrapure water;
and S2, adding carbon dioxide into the pure water to eliminate static electricity generated by the diamond cutter and the silicon wafer during cutting.
Preferably, in the second step, the silver paste process needs to perform a curing treatment of the silver paste.
Preferably, in the third step, the metal wire is any one of a gold wire, a copper wire or an aluminum wire.
Preferably, in the fourth step, a plasma cleaning process is added before the plastic package.
Preferably, the plasma process is: the gas molecules are excited, dissociated or ionized by means of direct current, radio frequency or alternating current, microwaves and the like.
Preferably, in the cleaning step, the surface is roughened by using argon oxygen as a cleaning medium.
Preferably, in the fifth step, the method for removing the excessive flash is weak base soaking and high-pressure water washing.
The invention provides a method for manufacturing an inner lead of a semiconductor frame in a layered manner, which has the beneficial effects that: the invention can effectively improve the anti-layering capability of the packaging body, improve the packaging material, improve the technology of the packaging process, prevent the internal layering of the component, reduce the packaging difficulty and cost, improve the quality and reliability of the product, enlarge the application range and can be applied to various fields by packaging, plastic packaging and increasing the plasma cleaning and cleaning process.
Detailed Description
In the following, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Embodiment 1, the present invention provides a technical solution: a method for manufacturing an inner lead of a semiconductor frame in a layered manner comprises the following steps;
step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer;
cutting process: the chips generated by cutting need to be removed by using ultrapure water; adding carbon dioxide into pure water to eliminate static electricity generated by diamond knife and silicon wafer during cutting
Secondly, coating silver colloid in the appointed base island region of the lead frame, wherein the silver colloid curing treatment is required in the silver colloid processing procedure, and the separated crystal grains are mounted in the base island region;
thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by ultrasonic welding by using a high-purity metal wire, wherein the metal wire is a gold wire; in the cleaning procedure, argon oxygen is used as a cleaning medium to roughen the surface;
step four, plastic packaging the product by using resin, wherein the plastic packaging material needs to adopt low stress, low hygroscopicity and proper adhesiveness, and after plastic packaging, molding silica gel is adopted for curing;
before plastic packaging, a plasma cleaning process can be added, wherein the plasma process comprises the following steps: gas molecules are excited, dissociated or ionized by using direct current, voltage control needs to be done, and certain internal damage is caused to the plastic package body by overhigh electrolytic voltage; in the cleaning step, argon and oxygen are used as a cleaning medium to roughen the surface.
Removing redundant flash between the peripheral pins of the tube body after removing the Molding silica gel, wherein the redundant flash removing method comprises weak base soaking and high-pressure water washing;
and sixthly, plating a layer of plating layer on the surface of the frame by using a metal and chemical method, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent.
Embodiment 2, the present invention provides a technical solution: a method for manufacturing an inner lead of a semiconductor frame in a layered manner comprises the following steps;
step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer;
cutting process: the chips generated by cutting need to be removed by using ultrapure water; adding carbon dioxide into pure water to eliminate static electricity generated by diamond knife and silicon wafer during cutting
Secondly, coating silver colloid in the appointed base island region of the lead frame, wherein the silver colloid curing treatment is required in the silver colloid processing procedure, and the separated crystal grains are mounted in the base island region;
thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by using a high-purity metal wire through ultrasonic welding, wherein the metal wire is a copper wire; in the cleaning procedure, argon oxygen is used as a cleaning medium to roughen the surface;
step four, plastic packaging the product by using resin, wherein the plastic packaging material needs to adopt low stress, low hygroscopicity and proper adhesiveness, and after plastic packaging, molding silica gel is adopted for curing;
before plastic packaging, a plasma cleaning process can be added, wherein the plasma process comprises the following steps: gas molecules are excited, dissociated or ionized by radio frequency or alternating current, voltage control needs to be done, and certain internal damage is caused to the plastic package body by overhigh electrolytic voltage; in the cleaning step, argon and oxygen are used as a cleaning medium to roughen the surface.
Removing redundant flash between the peripheral pins of the tube body after removing the Molding silica gel, wherein the redundant flash removing method comprises weak base soaking and high-pressure water washing;
and sixthly, plating a layer of plating layer on the surface of the frame by using a metal and chemical method, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent.
Embodiment 3, the present invention provides a technical solution: a method for manufacturing an inner lead of a semiconductor frame in a layered manner comprises the following steps;
step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer;
cutting process: the chips generated by cutting need to be removed by using ultrapure water; adding carbon dioxide into pure water to eliminate static electricity generated by diamond knife and silicon wafer during cutting
Secondly, coating silver colloid in the appointed base island region of the lead frame, wherein the silver colloid curing treatment is required in the silver colloid processing procedure, and the separated crystal grains are mounted in the base island region;
thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by using a high-purity metal wire through ultrasonic welding, wherein the metal wire is an aluminum wire; in the cleaning procedure, argon oxygen is used as a cleaning medium to roughen the surface;
step four, plastic packaging the product by using resin, wherein the plastic packaging material needs to adopt low stress, low hygroscopicity and proper adhesiveness, and after plastic packaging, molding silica gel is adopted for curing;
before plastic packaging, a plasma cleaning process can be added, wherein the plasma process comprises the following steps: gas molecules are excited, dissociated or ionized by microwaves, voltage control needs to be done, and a certain internal damage is generated on the plastic package body by an overhigh electrolytic voltage; in the cleaning step, argon and oxygen are used as a cleaning medium to roughen the surface.
Removing redundant flash between the peripheral pins of the tube body after removing the Molding silica gel, wherein the redundant flash removing method comprises weak base soaking and high-pressure water washing;
and sixthly, plating a layer of plating layer on the surface of the frame by using a metal and chemical method, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A method for manufacturing an inner lead of a semiconductor frame in a layered manner is characterized in that: comprises the following steps;
step one, adhering a wafer on a blue film and designing a cutting channel, and cutting the whole wafer into independent crystal grains by using a diamond knife through the designed cutting channel on the wafer;
secondly, coating silver colloid in a specified base island area of the lead frame, and mounting the separated crystal grains in the base island area;
thirdly, connecting the circuit connection point on the crystal grain and the lead frame together by using a high-purity metal wire through ultrasonic welding;
step four, plastic packaging the product by using resin, and curing by using molding silica gel after the plastic packaging;
removing redundant flash between the peripheral pins of the tube body after the Molding silica gel;
and sixthly, plating a layer of plating layer on the surface of the frame by using a metal and chemical method, wherein the lead-free electroplating is carried out by adopting high-purity tin with the purity of more than 99.99 percent.
2. The method of claim 1, wherein the step of layering comprises: in the first step, the cutting process:
s1, removing the debris generated by cutting by using ultrapure water;
and S2, adding carbon dioxide into the pure water to eliminate static electricity generated by the diamond cutter and the silicon wafer during cutting.
3. The method of claim 1, wherein the step of layering comprises: in the second step, the silver colloid process needs to carry out the solidification treatment of the silver colloid.
4. The method of claim 1, wherein the step of layering comprises: in the third step, the metal wire is any one of a gold wire, a copper wire or an aluminum wire.
5. The method of claim 1, wherein the step of layering comprises: in the fourth step, a plasma cleaning process can be added before the plastic package.
6. The method of claim 5, wherein the step of forming the inner lead layer comprises: the plasma process comprises the following steps: the gas molecules are excited, dissociated or ionized by means of direct current, radio frequency or alternating current, microwaves and the like.
7. The method of claim 5, wherein the step of forming the inner lead layer comprises: in the cleaning process, argon and oxygen are used as cleaning media to roughen the surface.
8. The method of claim 1, wherein the step of layering comprises: and step five, the method for removing the redundant flash comprises weak base soaking and high-pressure water washing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110891364.3A CN113675094A (en) | 2021-08-04 | 2021-08-04 | Inner lead layered manufacturing method of semiconductor frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110891364.3A CN113675094A (en) | 2021-08-04 | 2021-08-04 | Inner lead layered manufacturing method of semiconductor frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113675094A true CN113675094A (en) | 2021-11-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110891364.3A Pending CN113675094A (en) | 2021-08-04 | 2021-08-04 | Inner lead layered manufacturing method of semiconductor frame |
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| US20100308449A1 (en) * | 2009-06-03 | 2010-12-09 | Hung-Jen Yang | Semiconductor packages and manufacturing method thereof |
| CN103065930A (en) * | 2011-10-21 | 2013-04-24 | 无锡世一电力机械设备有限公司 | Composite plasma gas cleaning activation method |
| CN107393817A (en) * | 2017-07-25 | 2017-11-24 | 江苏长电科技股份有限公司 | A kind of chip structure and its manufacture method |
| CN109599346A (en) * | 2018-12-11 | 2019-04-09 | 杰群电子科技（东莞）有限公司 | A kind of intelligent power mould group processing technology and power modules |
| CN111009458A (en) * | 2019-12-25 | 2020-04-14 | 北京北方华创微电子装备有限公司 | Wafer cleaning method and wafer cleaning device |
| CN111199942A (en) * | 2018-11-16 | 2020-05-26 | 泰州友润电子科技股份有限公司 | High-insulation lead frame and plastic packaging method |
-
2021
- 2021-08-04 CN CN202110891364.3A patent/CN113675094A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100308449A1 (en) * | 2009-06-03 | 2010-12-09 | Hung-Jen Yang | Semiconductor packages and manufacturing method thereof |
| CN103065930A (en) * | 2011-10-21 | 2013-04-24 | 无锡世一电力机械设备有限公司 | Composite plasma gas cleaning activation method |
| CN107393817A (en) * | 2017-07-25 | 2017-11-24 | 江苏长电科技股份有限公司 | A kind of chip structure and its manufacture method |
| CN111199942A (en) * | 2018-11-16 | 2020-05-26 | 泰州友润电子科技股份有限公司 | High-insulation lead frame and plastic packaging method |
| CN109599346A (en) * | 2018-12-11 | 2019-04-09 | 杰群电子科技（东莞）有限公司 | A kind of intelligent power mould group processing technology and power modules |
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