CN113675076A - Structure for reducing MOS capacitance and manufacturing method thereof - Google Patents
Structure for reducing MOS capacitance and manufacturing method thereof Download PDFInfo
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- CN113675076A CN113675076A CN202110868116.7A CN202110868116A CN113675076A CN 113675076 A CN113675076 A CN 113675076A CN 202110868116 A CN202110868116 A CN 202110868116A CN 113675076 A CN113675076 A CN 113675076A
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- 238000000137 annealing Methods 0.000 claims description 28
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- 229920005591 polysilicon Polymers 0.000 claims description 18
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract
The invention provides a structure for reducing MOS capacitance and a manufacturing method thereof, belonging to the technical field of manufacturing of semiconductor devices, the manufacturing method for reducing MOS capacitance comprises the steps of S1, providing a semiconductor substrate, and forming an epitaxial layer on the upper surface of the semiconductor substrate by using an epitaxial growth method; step S2, selectively etching the upper surface active region of the epitaxial layer to a predetermined depth to form a first doped trench; step S3, injecting P-type impurities and N-type impurities into the first doping groove through an ion injection method to form a P-type body area and an N-type active area; step S4, selectively etching the upper surface of the epitaxial layer and the position between the two N-type active regions to a preset depth to form a second doped groove; the grid oxide layer is processed by the process to be smoother, and the thickness of the grid oxide layer is increased, so that the electric field concentration is not easy to cause, the electric field is further optimized, and the voltage resistance of the device is improved.
Description
Technical Field
The invention belongs to the technical field of manufacturing of semiconductor devices, and particularly relates to a structure for reducing MOS (metal oxide semiconductor) capacitance and a manufacturing method thereof.
Background
As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, and the number of elements included in the integrated circuit is also increased. With the further development of semiconductor integrated circuits, the size of semiconductor elements is also reduced, and the basic structure of a MOS transistor includes three main regions: a source (source), a drain (drain), and a gate electrode (gate). In which the source and drain are formed by high doping, and are classified into n-type doping (NMOS) and p-type doping (PMOS) according to the device type.
During device scaling, the drain voltage does not decrease, which results in an increase in the channel electric field between the source and drain, and under the action of a strong electric field, electrons are accelerated between two collisions to a velocity many times higher than the thermal motion velocity, thereby causing the Hot electron effect (Hot Carrier Issue, HCI). The HCI effect can cause hot electrons to be injected into the gate dielectric layer, so that gate electrode current and substrate current are formed, the reliability of a device and a circuit is influenced, and even the device is broken down and burnt.
In order to overcome the HCI, the prior art has developed various improved methods for MOS transistor structures, such as dual-implant structures, buried-channel structures, discrete-gate structures, buried-drain structures, etc.; one of the more studied and more practical structures is a Lightly Doped Drain (LDD) structure. The LDD structure functions to reduce the channel region electric field, and thus the hot electron effect can be significantly improved.
At present, because the bottom oxide layer of the trench gate MOS structure is thin, and thus has a high gate-drain capacitance Cgd, which can reduce the switching speed and increase the loss of the device, the trench bottom oxide layer of the thickened trench gate MOS structure is usually adopted in the prior art to increase the breakdown voltage and reduce the gate-drain capacitance, however, the thick oxide layer deposited at the bottom of the trench needs to be deposited by High Density Plasma (HDPCVD) and etched by a deep trench oxide layer, the process is complex and the cost is high, on the other hand, on the premise of ensuring low conduction loss, the gate parasitic capacitance is further significantly reduced, and the improvement of the performance of the trench power MOS device to a greater extent becomes the direction of efforts of technicians in the field.
Disclosure of Invention
The embodiment of the invention provides a structure for reducing MOS capacitance and a manufacturing method thereof, aiming at solving the problems that the existing trench gate MOS structure needs to adopt high-density plasma (HDPCVD) deposition and deep trench oxide layer etching to deposit a thick oxide layer at the bottom of a trench, the process is complex, the cost is higher, and on the other hand, the parasitic capacitance of a grid electrode is further remarkably reduced on the premise of ensuring low conduction loss.
In view of the above problems, the technical solution proposed by the present invention is:
a manufacturing method for reducing MOS capacitance comprises the following steps:
step S1, providing a semiconductor substrate, and forming an epitaxial layer on the upper surface of the semiconductor substrate by using an epitaxial growth method;
step S2, selectively etching the upper surface active region of the epitaxial layer to a predetermined depth to form a first doped trench;
step S3, injecting P-type impurities and N-type impurities into the first doping groove through an ion injection method to form a P-type body area and an N-type active area;
step S4, selectively etching the upper surface of the epitaxial layer and between the two N-type active regions to a predetermined depth to form a second doped trench, and simultaneously growing a gate oxide layer with a smooth surface on an inner wall surface of the second doped trench and reserving a third doped trench;
step S5, depositing a metal thin layer in the third doping groove, annealing, and etching the metal thin layer for at least 3 times;
step S6, a conductive polysilicon layer is grown in the metal thin layer by a thermal growth process until the conductive polysilicon layer is flush with the upper surface of the epitaxial layer.
As a preferred technical solution of the present invention, the method further includes step S7, depositing a source dielectric layer on the upper surfaces of the two N-type active regions and the conductive polysilicon layer, etching from top to bottom to form a U-shaped fourth doped trench, filling metal into the fourth doped trench, and etching the metal to form a source metal layer.
As a preferred technical solution of the present invention, the method further includes step S8, depositing an insulating medium on the outer wall surface of the source dielectric layer, and forming an insulating dielectric layer after etching.
As a preferable technical solution of the present invention, the method for manufacturing a reduced MOS capacitor according to claim 1 is characterized in that, in the step S5, three annealing processes are performed, wherein a temperature of the first annealing process is in a range of 200 ° to 300 °, a temperature of the second annealing process is in a range of 300 ° to 400 °, and a temperature of the third annealing process is in a range of 400 ° to 500 °.
In a preferred embodiment of the present invention, the metal thin layer is made of any one of titanium, carbon monoxide, and nickel.
As a preferred embodiment of the present invention, the material of the insulating dielectric layer includes any one of silicon oxide, silicon oxynitride, and silicon nitride.
As a preferred technical scheme of the invention, the thickness range of the gate oxide layer is 5500A-6500A.
In another aspect, the present invention further provides a structure for reducing MoS capacitance, comprising:
the semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an N-type active region, a P-type active region, a second doping groove, a conductive polycrystalline silicon layer, a source electrode dielectric layer, a source electrode metal layer and an insulating dielectric layer, wherein the top of the semiconductor substrate is vertically provided with the epitaxial layer, the upper surface of the epitaxial layer is etched with the first doping grooves from top to bottom, the first doping grooves are symmetrically arranged, P-type impurities and N-type impurities are respectively injected into the first doping grooves to form the N-type active region and the P-type active region, the N-type active region is vertically arranged above the P-type active region, the second doping groove is etched between the two N-type active regions, a grid oxide layer grows on the inner wall surface of the second doping groove, a third doping groove is reserved, and a metal thin layer is formed on the inner wall surface of the third doping groove by deposition and annealing, etching the metal thin layer for at least 3 times, growing the conductive polycrystalline silicon layer into the metal thin layer until the conductive polycrystalline silicon layer is flush with the upper surface of the epitaxial layer, depositing the source electrode dielectric layer on the upper surfaces of the two N-type active regions and the conductive polycrystalline silicon layer, etching the source electrode dielectric layer from top to bottom to form a U-shaped fourth doped groove, filling metal into the fourth doped groove, etching the metal to form the source electrode metal layer, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer, and etching to form the insulating dielectric layer.
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention has the advantage of low conduction loss, and the switching loss of the device is reduced.
(2) The invention leads the conductive polysilicon layer to extend beside the grid oxide layer, thereby reducing the grid charge on the premise of not influencing the on-state resistance, finally realizing the purpose of reducing the value of the device and further optimizing the performance of the device.
(3) The grid oxide layer is processed by the process to be smoother, and the thickness of the grid oxide layer is increased, so that the electric field concentration is not easy to cause, the electric field is further optimized, and the voltage resistance of the device is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Fig. 1 to 9 are schematic structural diagrams of steps S1 to S9 of a method for manufacturing a reduced MOS capacitor according to the present invention;
FIG. 10 is a process flow diagram of a method for fabricating a reduced MOS capacitor according to the present invention.
Description of reference numerals: 100. a semiconductor structure; 110. a semiconductor substrate; 120. an epitaxial layer; 121. a first doping trench; 130. an N-type active region; 140. a P-type active region; 150. a second doping trench; 151. a gate oxide layer; 152. a third doping trench; 153. a thin metal layer; 154. a fourth doping trench; 160. a conductive polysilicon layer; 170. a source electrode dielectric layer; 180. a source metal layer; 190. and an insulating dielectric layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used for convenience of description and simplicity of description, but do not indicate or imply that the referenced apparatus or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first", "second", may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments.
Example one
Referring to the attached drawings 1-10, the invention provides a technical scheme that: a manufacturing method for reducing MOS capacitance comprises the following steps:
step S1, a semiconductor substrate is provided, and an epitaxial layer is formed on the upper surface of the semiconductor substrate by using an epitaxial growth method.
Step S2, selectively etching the active region on the upper surface of the epitaxial layer to a predetermined depth to form a first doped trench.
Step S3, implanting P-type impurity and N-type impurity into the first doping trench by ion implantation to form a P-type body region and an N-type active region.
Step S4, selectively etching the upper surface of the epitaxial layer and between the two N-type active regions to a predetermined depth to form a second doped trench, and simultaneously growing a gate oxide layer with a smooth surface on an inner wall surface of the second doped trench and reserving a third doped trench.
The thickness of the gate oxide layer is 5500A.
Step S5, depositing a metal thin layer in the third doping trench and performing annealing treatment, and performing at least 3 times of etching on the metal thin layer.
In step S5, three annealing processes are performed, wherein the temperature of the first annealing process is 200 °, the temperature of the second annealing process is 300 °, and the temperature range of the third annealing process is 400 °.
Step S6, a conductive polysilicon layer is grown in the metal thin layer by a thermal growth process until the conductive polysilicon layer is flush with the upper surface of the epitaxial layer.
Step S7, depositing a source dielectric layer on the upper surfaces of the two N-type active regions and the conductive polysilicon layer, etching from top to bottom to form a U-shaped fourth doped trench, filling metal into the fourth doped trench, and etching the metal to form a source metal layer.
And step S8, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer and forming an insulating dielectric layer after etching.
Example two
Referring to the attached drawings 1-10, the invention provides a technical scheme that: a manufacturing method for reducing MOS capacitance comprises the following steps:
step S1, a semiconductor substrate is provided, and an epitaxial layer is formed on the upper surface of the semiconductor substrate by using an epitaxial growth method.
Step S2, selectively etching the active region on the upper surface of the epitaxial layer to a predetermined depth to form a first doped trench.
Step S3, implanting P-type impurity and N-type impurity into the first doping trench by ion implantation to form a P-type body region and an N-type active region.
Step S4, selectively etching the upper surface of the epitaxial layer and between the two N-type active regions to a predetermined depth to form a second doped trench, and simultaneously growing a gate oxide layer with a smooth surface on an inner wall surface of the second doped trench and reserving a third doped trench.
The thickness of the grid oxide layer is 6000A.
Step S5, depositing a metal thin layer in the third doping trench and performing annealing treatment, and performing at least 3 times of etching on the metal thin layer.
In step S5, three annealing processes are performed, wherein the temperature of the first annealing process is 250 °, the temperature of the second annealing process is 350 °, and the temperature range of the third annealing process is 450 °.
Step S6, a conductive polysilicon layer is grown in the metal thin layer by a thermal growth process until the conductive polysilicon layer is flush with the upper surface of the epitaxial layer.
Step S7, depositing a source dielectric layer on the upper surfaces of the two N-type active regions and the conductive polysilicon layer, etching from top to bottom to form a U-shaped fourth doped trench, filling metal into the fourth doped trench, and etching the metal to form a source metal layer.
And step S8, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer and forming an insulating dielectric layer after etching.
EXAMPLE III
Referring to the attached drawings 1-10, the invention provides a technical scheme that: a manufacturing method for reducing MOS capacitance comprises the following steps:
step S1, a semiconductor substrate is provided, and an epitaxial layer is formed on the upper surface of the semiconductor substrate by using an epitaxial growth method.
Step S2, selectively etching the active region on the upper surface of the epitaxial layer to a predetermined depth to form a first doped trench.
Step S3, implanting P-type impurity and N-type impurity into the first doping trench by ion implantation to form a P-type body region and an N-type active region.
Step S4, selectively etching the upper surface of the epitaxial layer and between the two N-type active regions to a predetermined depth to form a second doped trench, and simultaneously growing a gate oxide layer with a smooth surface on an inner wall surface of the second doped trench and reserving a third doped trench.
The thickness of the gate oxide layer is 6500A.
And S5, depositing a metal thin layer in the third doping groove, annealing, and etching the metal thin layer for at least 3 times.
In step S5, three annealing processes are performed, wherein the temperature of the first annealing process is 300 °, the temperature of the second annealing process is 400 °, and the temperature range of the third annealing process is 500 °.
Step S6, a conductive polysilicon layer is grown in the metal thin layer by a thermal growth process until the conductive polysilicon layer is flush with the upper surface of the epitaxial layer.
Step S7, depositing a source dielectric layer on the upper surfaces of the two N-type active regions and the conductive polysilicon layer, etching from top to bottom to form a U-shaped fourth doped trench, filling metal into the fourth doped trench, and etching the metal to form a source metal layer.
And step S8, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer and forming an insulating dielectric layer after etching.
In a preferred embodiment of the present invention, the material of the metal thin layer is any one of titanium, carbon monoxide or nickel.
In a preferred embodiment of the present invention, the material of the insulating dielectric layer includes any one of silicon oxide, silicon oxynitride, and silicon nitride.
Example four
Referring to fig. 9, another embodiment of the invention provides a structure for reducing MOS capacitance, including a semiconductor structure:
the semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an N-type active region, a P-type active region, a second doping groove, a conductive polycrystalline silicon layer, a source electrode dielectric layer, a source electrode metal layer and an insulating dielectric layer, wherein the top of the semiconductor substrate is vertically provided with the epitaxial layer, the upper surface of the epitaxial layer is etched with the first doping grooves from top to bottom, the first doping grooves are symmetrically arranged, P-type impurities and N-type impurities are respectively injected into the first doping grooves to form the N-type active region and the P-type active region, the N-type active region is vertically arranged above the P-type active region, the second doping groove is etched between the two N-type active regions, a grid oxide layer grows on the inner wall surface of the second doping groove, a third doping groove is reserved, and a metal thin layer is formed on the inner wall surface of the third doping groove by deposition and annealing, etching the metal thin layer for at least 3 times, growing the conductive polycrystalline silicon layer into the metal thin layer until the conductive polycrystalline silicon layer is flush with the upper surface of the epitaxial layer, depositing the source electrode dielectric layer on the upper surfaces of the two N-type active regions and the conductive polycrystalline silicon layer, etching the source electrode dielectric layer from top to bottom to form a U-shaped fourth doped groove, filling metal into the fourth doped groove, etching the metal to form the source electrode metal layer, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer, and etching to form the insulating dielectric layer.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
(1) the invention has the advantage of low conduction loss, and the switching loss of the device is reduced.
(2) The invention leads the conductive polysilicon layer to extend beside the grid oxide layer, thereby reducing the grid charge on the premise of not influencing the on-state resistance, finally realizing the purpose of reducing the value of the device and further optimizing the performance of the device.
(3) The grid oxide layer is processed by the process to be smoother, and the thickness of the grid oxide layer is increased, so that the electric field concentration is not easy to cause, the electric field is further optimized, and the voltage resistance of the device is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A manufacturing method for reducing MOS capacitance is characterized by comprising the following steps:
step S1, providing a semiconductor substrate, and forming an epitaxial layer on the upper surface of the semiconductor substrate by using an epitaxial growth method;
step S2, selectively etching the upper surface active region of the epitaxial layer to a predetermined depth to form a first doped trench;
step S3, injecting P-type impurities and N-type impurities into the first doping groove through an ion injection method to form a P-type body area and an N-type active area;
step S4, selectively etching the upper surface of the epitaxial layer and between the two N-type active regions to a predetermined depth to form a second doped trench, and simultaneously growing a gate oxide layer with a smooth surface on an inner wall surface of the second doped trench and reserving a third doped trench;
step S5, depositing a metal thin layer in the third doping groove, annealing, and etching the metal thin layer for at least 3 times;
step S6, a conductive polysilicon layer is grown in the metal thin layer by a thermal growth process until the conductive polysilicon layer is flush with the upper surface of the epitaxial layer.
2. The method as claimed in claim 1, further comprising step S7, depositing a source dielectric layer on the upper surfaces of the two N-type active regions and the conductive polysilicon layer, etching from top to bottom to form a U-shaped fourth doped trench, filling metal into the fourth doped trench, and etching the metal to form a source metal layer.
3. The method as claimed in claim 2, further comprising step S8, depositing an insulating dielectric on the outer wall of the source dielectric layer and etching the insulating dielectric to form an insulating dielectric layer.
4. The method as claimed in claim 1, wherein the step S5 is performed by three annealing processes, wherein a first annealing process has a temperature range of 200 ° to 300 °, a second annealing process has a temperature range of 300 ° to 400 °, and a third annealing process has a temperature range of 400 ° to 500 °.
5. The method as claimed in claim 1, wherein the thin metal layer is made of any one of titanium, carbon monoxide and nickel.
6. The method as claimed in claim 3, wherein the insulating dielectric layer is made of silicon oxide, silicon oxynitride or silicon nitride.
7. The method of claim 1, wherein the gate oxide layer has a thickness in a range from 5500A to 6500A.
8. A structure for reducing MOS capacitance, which is applied to the manufacturing method for reducing MOS capacitance as claimed in any one of claims 1 to 7, and comprises a semiconductor structure:
the semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an N-type active region, a P-type active region, a second doping groove, a conductive polycrystalline silicon layer, a source electrode dielectric layer, a source electrode metal layer and an insulating dielectric layer, wherein the top of the semiconductor substrate is vertically provided with the epitaxial layer, the upper surface of the epitaxial layer is etched with the first doping grooves from top to bottom, the first doping grooves are symmetrically arranged, P-type impurities and N-type impurities are respectively injected into the first doping grooves to form the N-type active region and the P-type active region, the N-type active region is vertically arranged above the P-type active region, the second doping groove is etched between the two N-type active regions, a grid oxide layer grows on the inner wall surface of the second doping groove, a third doping groove is reserved, and a metal thin layer is formed on the inner wall surface of the third doping groove by deposition and annealing, etching the metal thin layer for at least 3 times, growing the conductive polycrystalline silicon layer into the metal thin layer until the conductive polycrystalline silicon layer is flush with the upper surface of the epitaxial layer, depositing the source electrode dielectric layer on the upper surfaces of the two N-type active regions and the conductive polycrystalline silicon layer, etching the source electrode dielectric layer from top to bottom to form a U-shaped fourth doped groove, filling metal into the fourth doped groove, etching the metal to form the source electrode metal layer, depositing an insulating medium on the outer wall surface of the source electrode dielectric layer, and etching to form the insulating dielectric layer.
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