CN113674656B

CN113674656B - GOA circuit and electrical aging test method thereof

Info

Publication number: CN113674656B
Application number: CN202110929919.9A
Authority: CN
Inventors: 吕晓文; 袁驰文
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2021-08-13
Filing date: 2021-08-13
Publication date: 2022-07-12
Anticipated expiration: 2041-08-13
Also published as: CN113674656A

Abstract

The application discloses GOA circuit and electricity aging testing method thereof, GOA circuit includes a plurality of cascaded GOA constitutional units, and the GOA unit of Nth level includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor; the first thin film transistor is connected with a pull-up control signal and a grid signal, and the first thin film transistor, the fifth thin film transistor, the second thin film transistor and the third thin film transistor are connected to a first node; the second thin film transistor and the third thin film transistor are both connected to a clock signal, and the third thin film transistor outputs a pull-up control signal; the fourth thin film transistor is connected to the second constant voltage low level signal and the fifth thin film transistor is connected to the first constant voltage low level signal. The voltage difference between the voltage of the first constant voltage low level signal and the voltage of the second constant voltage low level signal is set to be greater than 0 or less than 0, so that the first thin film transistor, the second thin film transistor and the third thin film transistor are subjected to electrical aging.

Description

GOA circuit and electrical aging test method thereof

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit and an electrical aging test method thereof.

Background

The basic concept of a GOA (Gate Driver on Array, Array substrate and row Driver technology) circuit is to integrate a Gate Driver circuit of a TFT-LCD (thin film transistor-liquid crystal display) panel (abbreviated as a liquid crystal panel) on a glass substrate to form a scan drive for the liquid crystal panel. Compared with the conventional driving technology using a Chip On Flex (or) Film (COF), the GOA circuit can greatly save the manufacturing cost, and saves the Bonding process of the Gate COF, which is also very beneficial to the improvement of the productivity. Therefore, the GOA is an important technology for the development of the liquid crystal panel in the future.

FIG. 1 is a conventional GOA circuit structure unit; fig. 2 is a timing diagram of structural units of the GOA circuit in fig. 1.

As shown in fig. 1-2, the GOA circuit requires a smaller and smaller trigger time (falling time) as the resolution and frequency of the screen are increased, and the voltage difference between CK and VSS is generally considered to be increased to decrease the falling time. The larger the voltage difference is, the smaller the Faling time is, but the Ripple (Ripple) of the output terminal Gn is also larger and larger along with the increase of the voltage difference of the single VSS, so that the stability of the GOA circuit is poor, and the display effect is affected.

In addition, in the actual production process, the product is subjected to an electrical Aging test (Aging test) before shipment, so as to achieve the purpose of reducing the leakage current of the transistor. However, the electrical aging method in the prior art needs to directly apply an excessive voltage to the GOA circuit, which may cause damage to the GOA circuit.

Disclosure of Invention

The invention aims to provide a GOA circuit and an electrical aging test method thereof, so as to solve the technical problem of poor stability of the GOA circuit.

To achieve the above object, the present invention provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA structural units, and an nth-stage GOA unit includes: the device comprises a pull-up control unit (1), a pull-up unit (2), a signal downloading unit (3) and a first pull-down maintaining unit (4); wherein N is a positive integer; the pull-up control unit (1) includes a first thin film transistor (T11), the pull-up unit (2) includes a second thin film transistor (T21), and the signal download unit (3) includes a third thin film transistor (T22); the gate and the drain of the first thin film transistor (T11) are respectively connected to an N-6 th level pull-up control signal (ST (N-6)) and an N-6 th level gate signal (G (N-6)), and the source of the first thin film transistor (T11) is connected to the source of the fifth thin film transistor (T42), the gate of the second thin film transistor (T21) and the gate of the third thin film transistor (T22) at a first node (q (N)); the drain electrode of the second thin film transistor (T21) and the drain electrode of the third thin film transistor (T22) are both connected with a clock signal, the source electrode of the third thin film transistor (T22) outputs an Nth-stage pull-up control signal (ST (N)), and the source electrode of the second thin film transistor (T21) is used as the output end of an Nth-stage gate signal (G (N)); a drain of the fourth thin film transistor (T32) is connected to a second constant voltage low level signal (VSSG), a drain of the fifth thin film transistor (T42) is connected to a first constant voltage low level signal (VSSQ), and a source of the fourth thin film transistor (T32) is connected to a source of the second thin film transistor (T21); when the GOA circuit performs an electrical aging test, setting a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) to be greater than 0 or less than 0, so that the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) perform electrical aging.

Further, when the GOA circuit performs an electrical aging test, the voltage of the gate and the source of the first thin film transistor (T11) are both the same as the voltage of the first constant voltage low level signal (VSSQ), and the voltage of the drain of the first thin film transistor (T11) is the same as the voltage of the second constant voltage low level signal (VSSG); a voltage of a gate of the second thin film transistor (T21) is the same as a voltage of the first constant voltage low level signal (VSSQ), and a voltage of a source of the second thin film transistor (T21) is the same as a voltage of the second constant voltage low level signal (VSSG); a gate voltage of the third thin film transistor (T22) is the same as a voltage of the first constant voltage low level signal (VSSQ), and a source voltage of the third thin film transistor (T22) is the same as a voltage of the second constant voltage low level signal (VSSG).

Further, when the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are all N-type thin film transistors, a voltage difference between the voltage of the first constant voltage low level signal (VSSQ) and the voltage of the second constant voltage low level signal (VSSG) is less than 0.

Further, a voltage of the first constant voltage low level signal (VSSQ) is less than a voltage of the second constant voltage low level signal (VSSG); a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) ranges from-10 to-2.

Further, when the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are all P-type thin film transistors, a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) is greater than 0.

Further, the nth level GOA unit further includes: a second pull-down maintaining unit (5), wherein the second pull-down maintaining unit (5) comprises a sixth thin film transistor (T33) and a seventh thin film transistor (T43), the drains of the sixth thin film transistor (T33) and the seventh thin film transistor (T43) are both connected with a constant voltage low level signal, the source of the seventh thin film transistor (T43) is connected with the gate of the third thin film transistor (T22), and the source of the sixth thin film transistor (T33) is connected with the source of the second thin film transistor (T21).

Further, the nth level GOA unit further includes: a first inverter (6) and a second inverter (7); an input terminal of the first inverter (6) is connected to the source of the first thin film transistor (T11), and an output terminal of the first inverter (6) is connected to the gate of the fourth thin film transistor (T32) and the gate of the fifth thin film transistor (T42); an input terminal of the second inverter (7) is connected to the source of the first thin film transistor (T11), and an output terminal of the second inverter (7) is connected to the gate of the sixth thin film transistor (T33) and the gate of the seventh thin film transistor (T43).

Further, the nth level GOA unit further includes: a pull-down unit (8), the pull-down unit (8) including eighteenth and nineteenth thin film transistors (T31, T41); a drain of the eighteenth thin film transistor (T31) and a drain of the nineteenth thin film transistor (T41) are both connected to a constant voltage low level signal, a gate of the eighteenth thin film transistor (T31) and a gate of the nineteenth thin film transistor (T41) are both connected to an N +8 th-order gate signal (G (N +8)), a source of the eighteenth thin film transistor (T31) is connected to a source of the second thin film transistor (T21), and a source of the nineteenth thin film transistor (T41) is connected to a gate of the second thin film transistor (T21) and a gate of the third thin film transistor (T22).

In order to achieve the above object, the present invention further provides a method for testing electrical aging of a GOA circuit, where the GOA circuit is the above-mentioned GOA circuit; the electrical aging test method of the GOA circuit comprises the following steps: setting a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) to be greater than 0 or less than 0, so that the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are electrically aged.

Further, after the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are electrically aged, the method further includes: and respectively setting the voltage of the first constant voltage low level signal (VSSQ) and the voltage of the second constant voltage low level signal (VSSG) as lighting point positions.

The technical effect of the present invention is to provide a GOA circuit and an electrical aging test method thereof, wherein when the GOA circuit performs an electrical aging test, a voltage difference between a voltage of the first constant voltage low level signal VSSQ and a voltage of the second constant voltage low level signal VSSG is set to be greater than 0 or less than 0, so that the thin film transistors T11, T21, and T22 perform electrical aging, thereby effectively preventing a GOA failure problem caused by high temperature leakage and reducing aging (aging) time. Compared with the aging time of a conventional GOA circuit, the aging (aging) time can be shortened by about 60 × 2160 times, the aging test efficiency is greatly improved, the productivity is improved, and the production cost is reduced.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a conventional GOA circuit structure unit.

Fig. 2 is a timing diagram of the structural unit of the GOA circuit in fig. 1.

Fig. 3 is a structural unit of a GOA circuit according to an embodiment of the present disclosure.

FIG. 4 is an enlarged view of the TFT T21/T22 of FIG. 3;

fig. 5 is an enlarged view of the thin film transistor T11 in fig. 3.

Fig. 6 is a timing diagram of the structural unit of the GOA circuit in fig. 4.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 3 provides a structural unit of a GOA circuit according to an embodiment of the present disclosure.

As shown in fig. 3, the present embodiment provides a GOA circuit, which includes a plurality of cascaded GOA structural units, where the nth level GOA unit includes: the pull-up circuit comprises a pull-up control unit 1, a pull-up unit 2, a signal down-transfer unit 3, a first pull-down maintaining unit 4, a second pull-down maintaining unit 5, a first inverter 6, a second inverter 7 and a pull-down unit 8; wherein N is a positive integer.

The pull-up control unit 1 includes a first thin film transistor T11, the pull-up unit 2 includes a second thin film transistor T21, the signal download unit 3 includes a third thin film transistor T22, and the first pull-down sustain unit 4 includes a fourth thin film transistor T32 and a fifth thin film transistor T42.

Specifically, the gate and the drain of the first thin film transistor T11 are respectively connected to an N-6 th level pull-up control signal ST (N-6) and an N-6 th level gate signal G (N-6), and the source of the first thin film transistor T11, the source of the fifth thin film transistor T42, the gate of the second thin film transistor T21 and the gate of the third thin film transistor T22 are connected to a first node q (N).

The drain of the second thin film transistor T21 and the drain of the third thin film transistor T22 both receive a clock signal, the source of the third thin film transistor T22 outputs an nth level pull-up control signal st (N), and the source of the second thin film transistor T21 serves as an output terminal of an nth level gate signal g (N).

It should be noted that the drain of the second thin film transistor T21 of the nth level GOA unit and the drain of the third thin film transistor T22 are connected to the positive phase clock signal ck (N) of the clock signals, and the drain of the second thin film transistor T21 of the nth-1 level GOA unit and the drain of the third thin film transistor T22 are connected to the negative phase clock signal XCK (N-1) of the clock signals, that is, the clock signals connected to the adjacent two levels of GOA units are the positive phase clock signal and the negative phase clock signal.

A drain electrode of the fourth thin film transistor T32 is connected to the second constant voltage low level signal VSSG, a drain electrode of the fifth thin film transistor T42 is connected to the first constant voltage low level signal VSSQ, and a source electrode of the fourth thin film transistor T32 is connected to a source electrode of the second thin film transistor T21.

When the GOA circuit is performing an electrical aging test, setting a voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG to be less than 0, so that the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 perform electrical aging.

It should be noted that, in the electrical aging process, due to the left shift caused by the characteristics of the thin film transistor itself, how to shift the thin film transistor to the right and return to the stable state at a faster speed is an important issue. The skilled person will typically apply a voltage to the thin film transistor, which is under a forward bias voltage (Stress), to solve this problem. However, in general UD products, only (1/60) × (1/2160) is in a forward bias state during one frame time, and thus the time for which the tft is shifted to the right is long.

In order to solve the problem that the tft is shifted to the right for a long time, when performing an electrical aging test, the present embodiment sets a voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG to be less than 0, and sets the voltage of the first constant voltage low level signal (VSSQ) to be less than the voltage of the second constant voltage low level signal (VSSG), so as to accelerate the shift of the first tft T11, the second tft T21, and the third tft T22 to the right. By setting the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG, that is, by setting the aging voltage of the GOA circuit, the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 are all under a forward bias voltage, so that the UD product is under a forward bias state for one frame time, the pressing time is 60 × 2160 times the normal lighting time, and the UD product can be forward biased to the required threshold Vth voltage in a short time.

After the pressurization (Stress) process is completed, the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG are both set to be normal lighting voltages, that is, the voltage of the first constant voltage low level signal VSSQ is less than the voltage of the second constant voltage low level signal VSSG, and the normal VSSQ and VSSG voltages are used for subsequent lighting.

Therefore, the present embodiment provides a GOA circuit, where the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are all N-type thin film transistors, a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) is less than 0, and the voltage of the first constant voltage low level signal (VSSQ) is less than the voltage of the second constant voltage low level signal (VSSG), so as to effectively prevent the GOA failure problem caused by high temperature leakage and reduce aging (aging) time. Compared with the aging time of a conventional GOA circuit, the aging (aging) time can be shortened by about 60 × 2160 times, the aging test efficiency is greatly improved, the productivity is improved, and the production cost is reduced.

Preferably, a voltage difference of the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) ranges from-10 to-2, i.e., VSSQ-10-2.

FIG. 4 is an enlarged view of the TFT T21/T22 of the present embodiment; fig. 5 is an enlarged view of the thin film transistor T11 provided in the present embodiment.

As shown in fig. 3 to 5, when the GOA circuit performs an electrical aging test, the voltages of the gate and the source of the first thin film transistor T11 are both the same as the voltage of the first constant voltage low level signal VSSQ, and the voltage of the drain of the first thin film transistor T11 is the same as the voltage of the second constant voltage low level signal VSSG; a voltage of a gate electrode of the second thin film transistor T21 is the same as a voltage of the first constant voltage low level signal (VSSQ), and a voltage of a source electrode of the second thin film transistor T21 is the same as a voltage of the second constant voltage low level signal VSSG; the gate voltage of the third thin film transistor T22 is the same as the voltage of the first constant voltage low level signal VSSQ, and the source voltage of the third thin film transistor T22 is the same as the voltage of the second constant voltage low level signal VSSG.

The first constant voltage low level signal VSSQ is a turn-off voltage of the nth grade GOA unit, and the second constant voltage low level signal VSSG is a low potential given to an in-plane.

The second pull-down maintaining unit 5 includes a sixth thin film transistor T33 and a seventh thin film transistor T43, the sixth thin film transistor T33 is connected to the second constant voltage low level signal VSSG, the seventh thin film transistor T43 is connected to the first constant voltage low level signal VSSQ, a source of the seventh thin film transistor T43 is connected to a gate of the third thin film transistor T22, and a source of the sixth thin film transistor T33 is connected to a source of the second thin film transistor T21.

In this embodiment, two pull-down maintaining units are arranged to operate alternately, so as to prevent the fourth thin film transistor T32, the fifth thin film transistor T42, the sixth thin film transistor T33, and the seventh thin film transistor T43 from receiving PBS (Positive Bias Stress) for a long time, which causes the Bias Vth of the device to drift forward and seriously cause the failure of the GOA circuit.

An input terminal of the first inverter 6 is connected to the source of the first thin film transistor T11, and an output terminal of the first inverter 6 is connected to the gate of the fourth thin film transistor T32 and the gate of the fifth thin film transistor T42.

An input terminal of the second inverter 7 is connected to the source electrode of the first thin film transistor T11, and an output terminal of the second inverter 8 is connected to the gate electrode of the sixth thin film transistor T33 and the gate electrode of the seventh thin film transistor T43.

The first inverter 6 includes an eighth thin film transistor T51, a ninth thin film transistor T52, a tenth thin film transistor T53, and an eleventh thin film transistor T54.

A gate and a drain of the eighth thin film transistor T51 and a drain of the tenth thin film transistor T53 are connected to a first pull-down control signal LC1, a source of the eighth thin film transistor T51 is connected to the gate of the tenth thin film transistor T53 and the source of the ninth thin film transistor T52, and a source of the tenth thin film transistor T53 is connected to a second node p (n) which is connected to the source of the eleventh thin film transistor T54, the gate of the fourth thin film transistor T32 and the gate of the fifth thin film transistor T42.

A gate of the ninth thin film transistor T52 and a gate of the eleventh thin film transistor T54 are both connected to the source of the first thin film transistor T11, and a drain of the ninth thin film transistor T52 and a drain of the eleventh thin film transistor T54 are both connected to a first constant voltage low level signal VSSQ.

The second inverter 7 includes a twelfth thin film transistor T61, a thirteenth thin film transistor T62, a fourteenth thin film transistor T63, and a fifteenth thin film transistor T64.

A gate and a drain of the twelfth thin film transistor T61 and a drain of the fourteenth thin film transistor T63 are connected to a second pull-down control signal LC2, a source of the twelfth thin film transistor T61 is connected to the gate of the fourteenth thin film transistor T63 and the source of the thirteenth thin film transistor T62, and a source of the fourteenth thin film transistor T63 is connected to the source of the fifteenth thin film transistor T64, the gate of the sixth thin film transistor T33 and the gate of the seventh thin film transistor T43 at a third node k (n).

A gate of the thirteenth thin film transistor T62 and a gate of the fifteenth thin film transistor T64 are both connected to the source of the first thin film transistor T11, and a drain of the thirteenth thin film transistor T62 and a drain of the fifteenth thin film transistor T64 are both connected to a first constant voltage low level signal VSSQ.

The pull-down unit 8 includes eighteenth and nineteenth thin film transistors T31 and T41.

The drain of the eighteenth thin film transistor T31 is connected to the second constant voltage low level signal VSSG, the drain of the nineteenth thin film transistor T41 is connected to the first constant voltage low level signal VSSQ, the gate of the eighteenth thin film transistor T31 and the gate of the nineteenth thin film transistor T41 are both connected to the (N +4) -th gate signal G (N +4), and the source of the eighteenth thin film transistor T31 is connected to the source of the second thin film transistor T21, the source of the nineteenth thin film transistor T41 is connected to the gate of the second thin film transistor T21 and the gate of the third thin film transistor T22.

The drain of the fourth thin film transistor T32 and the drain of the sixth thin film transistor T33 are both connected to a second constant voltage low level signal VSSG.

The nth GOA unit further includes a bootstrap capacitor Cb, and two ends of the bootstrap capacitor Cb are respectively connected to the gate and the source of the second thin film transistor T21.

Fig. 6 is a timing diagram of the structural unit of the GOA circuit in fig. 4.

As shown in fig. 4-6, the present embodiment provides a GOA circuit, which utilizes the characteristics of two VSS (i.e., VSSQ and VSSG) to make the aging voltage of the first constant voltage low level signal VSSQ different from the aging voltage of the second constant voltage low level signal VSSG, i.e., VSSG < VSSQ, so that the tfts T11, T21, and T22 are all under the same forward voltage bias for electrical aging. In the present embodiment, with the potential setting of VSSG < VSSQ, and the potential difference Vgs >0 between the gate and source electrodes of the thin film transistors T11, T21, and T22, the GOA circuit still undergoes electrical aging, which can greatly accelerate the aging speed (see fig. 6 in detail), and can prevent the problem of left bias failure of the thin film transistors in the GOA circuit.

The present embodiment further provides a method for testing electrical aging of a GOA circuit, where the GOA circuit is the above-mentioned GOA circuit; the electrical aging test method of the GOA circuit comprises S1) -S2).

S1) setting a voltage difference between the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG to be less than 0, so that the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 are electrically aged.

In the present embodiment, when the electrical aging test is performed, the voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG is set to be less than 0, so as to accelerate the rightward shift of the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22. By setting the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG, that is, by setting the aging voltage of the GOA circuit, the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 are all under a forward bias voltage, so that the UD product is under a forward bias state for one frame time, the pressing time is 60 × 2160 times the normal lighting time, and the UD product can be forward biased to the required threshold Vth voltage in a short time.

S2) setting the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG as lighting points, respectively.

Therefore, the present embodiment provides an electrical aging test method for a GOA circuit, where the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 are all N-type thin film transistors, and a voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG is less than 0, so as to effectively prevent a GOA failure problem caused by high temperature leakage and reduce aging (aging) time. Compared with the aging time of a conventional GOA circuit, the aging (aging) time can be shortened by about 60 × 2160 times, the aging test efficiency is greatly improved, the productivity is improved, and the production cost is reduced.

Example 2

The present embodiment provides a GOA circuit and an electrical aging testing method thereof, including most technical features of embodiment 1, and is different in that when the GOA circuit performs an electrical aging test, a voltage difference between a voltage of the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG is set to be greater than 0, so that the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 perform electrical aging.

When the GOA circuit is subjected to an electrical aging test, if the first thin film transistor T11, the second thin film transistor T21, and the third thin film transistor T22 are all P-type thin film transistors, a voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG is greater than 0, so that the thin film transistors T11, T21, and T22 are turned on once from an original frame to be set that all the frames are turned on, thereby improving the aging efficiency.

The present embodiment further provides a method for testing electrical aging of a GOA circuit, where the GOA circuit is the above-mentioned GOA circuit; the electrical aging test method of the GOA circuit comprises S21) -S22).

S21) setting a voltage difference between the first constant voltage low level signal VSSQ and the second constant voltage low level signal VSSG to be greater than 0, so that the first, second, and third thin film transistors T11, T21, and T22 are electrically aged.

S22) setting the voltage of the first constant voltage low level signal VSSQ and the voltage of the second constant voltage low level signal VSSG as lighting points, respectively.

In the embodiment, the potential setting of VSSG < VSSQ is adopted, the potential difference Vgs between the gate and source electrodes of the thin film transistors T11, T21 and T22 is less than 0, and the GOA circuit still undergoes electrical aging, so that the aging speed can be greatly accelerated, and the problem of left bias failure of the thin film transistors in the GOA circuit can be prevented.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The GOA circuit and the electrical aging test method thereof provided by the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and implementations of the present application, and the description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A GOA circuit comprising a plurality of cascaded GOA fabric units, an nth level GOA unit comprising: the device comprises a pull-up control unit (1), a pull-up unit (2), a signal downloading unit (3) and a first pull-down maintaining unit (4); wherein N is a positive integer;

the pull-up control unit (1) includes a first thin film transistor (T11), the pull-up unit (2) includes a second thin film transistor (T21), and the signal download unit (3) includes a third thin film transistor (T22);

the gate and the drain of the first thin film transistor (T11) are respectively connected to an N-6 th level pull-up control signal (ST (N-6)) and an N-6 th level gate signal (G (N-6)), and the source of the first thin film transistor (T11) and the source of the fifth thin film transistor (T42), the gate of the second thin film transistor (T21) and the gate of the third thin film transistor (T22) are connected to a first node (q (N));

the drain electrode of the second thin film transistor (T21) and the drain electrode of the third thin film transistor (T22) are both connected with a clock signal, the source electrode of the third thin film transistor (T22) outputs an Nth-stage pull-up control signal (ST (N)), and the source electrode of the second thin film transistor (T21) is used as the output end of an Nth-stage gate signal (G (N));

a drain of the fourth thin film transistor (T32) is connected to a second constant voltage low level signal (VSSG), a drain of the fifth thin film transistor (T42) is connected to a first constant voltage low level signal (VSSQ), and a source of the fourth thin film transistor (T32) is connected to a source of the second thin film transistor (T21);

when the GOA circuit is subjected to an electrical aging test, setting the voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) to be greater than 0 or less than 0 so as to electrically age the first thin film transistor (T11), the second thin film transistor (T21) and the third thin film transistor (T22); when the GOA circuit is subjected to electrical burn-in testing,

a voltage of a gate and a source of the first thin film transistor (T11) are both the same as a voltage of the first constant voltage low level signal (VSSQ), and a voltage of a drain of the first thin film transistor (T11) is the same as a voltage of the second constant voltage low level signal (VSSG);

a voltage of a gate of the second thin film transistor (T21) is the same as a voltage of the first constant voltage low level signal (VSSQ), and a voltage of a source of the second thin film transistor (T21) is the same as a voltage of the second constant voltage low level signal (VSSG);

a gate voltage of the third thin film transistor (T22) is the same as a voltage of the first constant voltage low level signal (VSSQ), and a source voltage of the third thin film transistor (T22) is the same as a voltage of the second constant voltage low level signal (VSSG).

2. The GOA circuit of claim 1,

when the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are all N-type thin film transistors, a voltage difference between a voltage of the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) is less than 0.

3. The GOA circuit of claim 2,

a voltage of the first constant voltage low level signal (VSSQ) is less than a voltage of the second constant voltage low level signal (VSSG); a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) ranges from-10 to-2.

4. The GOA circuit of claim 1,

when the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are all P-type thin film transistors, a voltage difference between the voltage of the first constant voltage low level signal (VSSQ) and the voltage of the second constant voltage low level signal (VSSG) is greater than 0.

5. The GOA circuit of claim 1, wherein the Nth stage GOA unit further comprises: a second pull-down maintaining unit (5), wherein the second pull-down maintaining unit (5) comprises a sixth thin film transistor (T33) and a seventh thin film transistor (T43), the drains of the sixth thin film transistor (T33) and the seventh thin film transistor (T43) are both connected with a constant voltage low level signal, the source of the seventh thin film transistor (T43) is connected with the gate of the third thin film transistor (T22), and the source of the sixth thin film transistor (T33) is connected with the source of the second thin film transistor (T21).

6. The GOA circuit of claim 5, wherein the Nth stage GOA unit further comprises: a first inverter (6) and a second inverter (7);

an input terminal of the first inverter (6) is connected to the source of the first thin film transistor (T11), and an output terminal of the first inverter (6) is connected to the gate of the fourth thin film transistor (T32) and the gate of the fifth thin film transistor (T42);

an input terminal of the second inverter (7) is connected to the source of the first thin film transistor (T11), and an output terminal of the second inverter (7) is connected to the gates of the sixth thin film transistor (T33) and the seventh thin film transistor (T43).

7. The GOA circuit of claim 1, wherein the Nth stage GOA unit further comprises: a pull-down unit (8), the pull-down unit (8) including eighteenth and nineteenth thin film transistors (T31, T41); a drain of the eighteenth thin film transistor (T31) and a drain of the nineteenth thin film transistor (T41) are both connected to a constant voltage low level signal, a gate of the eighteenth thin film transistor (T31) and a gate of the nineteenth thin film transistor (T41) are both connected to an N +8 th-order gate signal (G (N +8)), a source of the eighteenth thin film transistor (T31) is connected to a source of the second thin film transistor (T21), and a source of the nineteenth thin film transistor (T41) is connected to a gate of the second thin film transistor (T21) and a gate of the third thin film transistor (T22).

8. A method for electrical burn-in testing of a GOA circuit, wherein the GOA circuit is the GOA circuit of any one of claims 1 to 7; the electrical aging test method of the GOA circuit comprises the following steps:

setting a voltage difference between the first constant voltage low level signal (VSSQ) and the second constant voltage low level signal (VSSG) to be greater than 0 or less than 0, so that the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are electrically aged.

9. The electrical burn-in method of claim 8, wherein,

after the first thin film transistor (T11), the second thin film transistor (T21), and the third thin film transistor (T22) are electrically aged, further comprising:

and respectively setting the voltage of the first constant voltage low level signal (VSSQ) and the voltage of the second constant voltage low level signal (VSSG) as lighting point positions.