CN113660764A

CN113660764A - Circuit board

Info

Publication number: CN113660764A
Application number: CN202010396961.4A
Authority: CN
Inventors: 沈芾云; 何明展; 徐筱婷; 郭宏艳
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2020-05-12
Filing date: 2020-05-12
Publication date: 2021-11-16
Anticipated expiration: 2040-05-12
Also published as: CN113660764B

Abstract

The utility model provides a circuit board, includes inlayer circuit layer, locates respectively the first outer circuit layer and the second outer circuit layer of inlayer circuit layer both sides, inlayer circuit layer includes the signal line, first outer circuit layer includes power cord and control line, second outer circuit layer includes mains voltage line, the power cord the control line reaches mains voltage line is in the orthographic projection on inlayer circuit layer with the signal line staggers.

Description

Circuit board

Technical Field

The present application relates to a circuit board.

Background

The 5G technology has the technical characteristics of large bandwidth, low time delay and super-large scale connection, and especially the millimeter wave frequency band puts higher requirements on antenna receiving, transmitting and transmitting, so that the use amount of radio frequency cables is increased. In the 5G middle and high-end models, LCP/MPI flexible boards are gradually adopted to directly undertake the radio frequency connection function. Compared with a radio frequency cable, the LCP/MPI flexible printed circuit board has a compact structure and a small occupied volume.

In the conventional design, the power voltage line, the power line, the control line and the signal transmission line are disposed in the same inner layer to reduce interference. This results in too many cables in the same layer and a large occupied space. The supply voltage lines need to pass large currents and therefore require conductors of large dimensions.

Disclosure of Invention

Accordingly, there is a need for a circuit board to solve the above problems.

An embodiment of the application provides a circuit board, include inlayer circuit layer, locate respectively the first outer circuit layer and the second outer circuit layer of inlayer circuit layer both sides, inlayer circuit layer includes the signal line, first outer circuit layer includes power cord and control line, second outer circuit layer includes power voltage line, the power cord the control line reaches power voltage line is in the orthographic projection on inlayer circuit layer with the signal line staggers.

Further, in some embodiments of the present application, the inner line layer further includes a first shield wire surrounding the signal wire; the first outer layer circuit layer further comprises a second shielding wire, and the second shielding wire surrounds the power line and the control line; the second outer layer circuit layer further includes a third shield line surrounding the supply voltage line.

Further, in some embodiments of the present application, the circuit board further includes a plurality of conductive vias, each of the conductive vias is electrically connected to the first shielding line, the second shielding line and the third shielding line, and the conductive vias are used for grounding.

Further, in some embodiments of the present application, the circuit board further includes a first cover layer covering the first outer layer circuit layer and a second cover layer covering the second outer layer circuit layer.

Further, in some embodiments of the present application, the circuit board further includes a first shielding layer and a second shielding layer, the first shielding layer is disposed on the first covering layer, the second shielding layer is disposed on the second covering layer, the first shielding layer and the second shielding layer are in an orthographic projection of the inner circuit layer and staggered with the signal line, and the first shielding layer and the second shielding layer are respectively electrically connected with the conductive hole.

Further, in some embodiments of the present application, the signal line is a strip line; the power line, the control line and the power voltage line adopt microstrip lines.

The embodiment of the application still provides a circuit board, including the circuit layer, the circuit layer includes signal line, power cord, control line and mains voltage line, the circuit board is still including locating respectively the first shielded wire and the second shielded wire of circuit layer both sides, first shielded wire covers whole circuit layer, the second shielded wire covers the signal line exposes power cord, control line and mains voltage line.

Further, in some embodiments of the present application, the circuit layer further includes a third shielding line, the third shielding line is located between the signal line and the power line, the control line, and the power voltage line, and the third shielding line further surrounds an outer side of the signal line, the power line, the control line, and the power voltage line.

Further, in some embodiments of the present application, the circuit board further includes a first cover layer and a second cover layer, the first cover layer is disposed on the first shielding line, and the second cover layer is disposed on the second shielding line and the circuit layer exposed from the second shielding line.

Further, in some embodiments of the present application, the circuit board further includes a shielding layer, the shielding layer is disposed on the first covering layer and directly faces the power line, the control line and the power voltage line, and the shielding layer is electrically connected to the third shielding line.

The circuit board is applied to place the signal lines in the inner layer of the circuit board so as to reduce interference. The power line, control line, and power voltage line are disposed on the outer layer of the circuit board. According to the calculation formula of the allowable current, the current carrying capacity of the circuit at the outer layer is twice that of the circuit at the inner layer. Therefore, the power line, the control line and the power voltage line are arranged on the outer layer, so that the advantages of line width and current bearing are achieved. Therefore, the entire volume of the circuit board can be reduced.

Drawings

Fig. 1 is a sectional view of a first copper-clad unit according to a second embodiment of the present invention.

Fig. 2 is a cross-sectional view of the copper-clad unit shown in fig. 1 after an inner wiring layer is formed thereon.

Fig. 3 is a cross-sectional view of the second copper clad unit laminated on the inner wiring layer shown in fig. 2.

Fig. 4 is a cross-sectional view of the structure of fig. 3 with a first via and a second via.

Fig. 5 is a cross-sectional view of the first via and the second via shown in fig. 4 after forming the first conductive via and the second conductive via, respectively.

Fig. 6 is a cross-sectional view of the structure of fig. 5 after forming a first outer wiring layer and a second outer wiring layer, respectively.

Fig. 7 is a cross-sectional view of the first outer circuit layer shown in fig. 6 with a first cover layer attached and a second outer circuit layer attached.

Fig. 8 is a cross-sectional view of the circuit board shown in fig. 7 after forming a first shielding layer on the first cover layer and a second shielding layer on the second cover layer.

Fig. 9 is a cross-sectional view of a first copper-clad unit according to a fourth embodiment of the present application.

Fig. 10 is a cross-sectional view of the copper-clad unit shown in fig. 9 after a wiring layer is formed thereon.

Fig. 11 is a cross-sectional view of the second copper clad unit laminated on the inner layer wiring layer shown in fig. 10.

Fig. 12 is a cross-sectional view of the structure of fig. 11 with a first via and a second via.

Fig. 13 is a cross-sectional view of the first and second vias shown in fig. 12 after forming the first and second conductive vias, respectively.

Fig. 14 is a cross-sectional view of the structure shown in fig. 13 with a portion of the second copper clad unit removed.

Fig. 15 is a cross-sectional view of the structure of fig. 14 with first and second cover layers attached.

Fig. 16 is a sectional view of the circuit board shown in fig. 15 after a first shielding layer is formed on the first cover layer.

Description of the main elements

Circuit boards

100, 200

Inner layer wiring layer 10

Signal lines

11, 211

First shielded

wire

12, 220

First outer circuit layer 20

Power supply line

21, 212

Control lines

22, 213

Second shielded

wire

23, 230

Second outer wiring layer 30

Supply voltage line

31, 214

Third shielded

wire

32, 215

First cover layer

40, 240

First

adhesive layer

41, 241

First

protective layer

42, 242

Second cover layer

50, 250

Second

adhesive layer

51, 251

Second

protective layer

52, 252

Conductive vias

60, 260

First shield layer 71

Second shield layer 72

First copper-clad

unit

101, 201

First carrier plates

1011, 3011

First copper layer

1012, 3012

Second copper layer

1013, 3013

Second copper-clad

unit

102, 202

Second carrier

2011, 2021

Third copper layer

2012, 2022

Adhesive layers

2013, 2023

First through-

hole

61, 261

Second through

hole

62, 262

First

conductive holes

611, 2611

Second

conductive vias

621, 2621

First opening 401, 2401

Second opening 501

Line layer 210

Shield layer 270

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The circuit board places the signal lines in the inner layer of the circuit board to reduce interference. The power line, control line, and power voltage line are disposed on the outer layer of the circuit board. According to the calculation formula of the allowable current, the current carrying capacity of the circuit at the outer layer is twice that of the circuit at the inner layer. Therefore, the power line, the control line and the power voltage line are arranged on the outer layer, so that the advantages of line width and current bearing are achieved. Therefore, the entire volume of the circuit board can be reduced.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Referring to fig. 8, a circuit board 100 according to a first embodiment of the present invention includes an inner circuit layer 10, and a first outer circuit layer 20 and a second outer circuit layer 30 respectively disposed on two sides of the inner circuit layer 10.

The circuit board 100 further includes a first cover layer 40 covering the first outer layer circuit layer 20 and a second cover layer 50 covering the second outer layer circuit layer 30.

The first covering layer 40 includes a first glue layer 41 and a first protection layer 42. The first glue layer 41 is adjacent to the first outer layer circuit layer 20. The second cover layer 50 includes a second adhesive layer 51 and a second protective layer 52. The second adhesive layer 51 is adjacent to the second outer layer wiring layer 30.

The inner circuit layer 10 includes a signal line 11 (for transmitting Intermediate Frequency (IF) signals in this embodiment) and a first shielding line 12. The first shield line 12 is disposed around the signal line 11.

In the illustrated embodiment, the number of the signal lines 11 is two. The first shield line 12 also extends between the two signal lines 11.

The first outer circuit layer 20 includes a power line 21, a control line (Pon)22, and a second shield line 23. The second shield line 23 is provided around the power supply line 21 and the control line 22.

The second outer layer circuit layer 30 includes a supply voltage line (VBATT)31 and a third shielding line 32. The third shielding line 32 is disposed around the power supply voltage line 31. In the illustrated embodiment, the number of the power supply voltage lines 31 is two.

The orthographic projection of the power line 21, the control line 22 and the power voltage line 31 on the inner layer line layer 10 is staggered with the signal line 11 to reduce the interference of the signal line 11. The orthographic projection of the power line 21, the control line 22 and the power voltage line 31 on the inner layer line layer 10 is located on the first shielding line 12. The orthographic projection of the signal line 11 on the first outer layer circuit layer 20 is positioned on the second shielding line 23. The orthographic projection of the signal line 11 on the second outer layer circuit layer 30 is located on the third shielding line 32.

The signal line 11 is a strip line; the power line 21, the control line 22 and the power voltage line 31 are microstrip lines.

The circuit board 100 also includes a plurality of conductive vias 60. Each conductive via 60 is electrically connected to the first shielded line 12, the second shielded line 23, and the third shielded line 32. A plurality of the conductive holes 60 are used for grounding to shield interference.

The circuit board 100 further includes a first shielding layer 71 and a second shielding layer 72. The first shielding layer 71 is disposed on the first cover layer 40. The second shielding layer 72 is disposed on the second cover layer 50. The first shielding layer 71 and the second shielding layer 72 are respectively located outside the power line 21, the control line 22 and the power voltage line 31. The first shielding layer 71 and the second shielding layer 72 are electrically connected to the conductive holes 60 at two sides of the power line 21, the control line 22 and the power voltage line 31.

The orthographic projections of the first shielding layer 71 and the second shielding layer 72 on the inner wiring layer 10 are staggered from the signal line 11.

The second embodiment of the present application provides a method for manufacturing the circuit board 100 of the first embodiment. The manufacturing method of the circuit board comprises the following steps:

first, referring to fig. 1, a first copper clad unit 101 is provided, where the first copper clad unit 101 includes a first carrier 1011 and a first copper layer 1012 and a second copper layer 1013 respectively disposed on two sides of the first carrier 1011.

In a second step, referring to fig. 2, an inner circuit layer 10 is formed on the first copper layer 1012.

The inner circuit layer 10 includes a signal line 11 and a first shield line 12, and the first shield line 12 is disposed around the signal line 11.

In at least one embodiment, the first copper layer 1012 is processed to form the inner circuit layer 10 by applying a dry film, exposing, developing, etching, and stripping process.

Third, referring to fig. 3, a second copper-clad unit 102 is provided, where the second copper-clad unit 102 includes a second carrier 2011 and a third copper layer 2012 disposed on one side of the second carrier 2011, and the second carrier 2011 is attached to the inner circuit layer 10.

In at least one embodiment, an adhesive layer 2013 is coated on the inner circuit layer 10, and the second carrier 2011 is attached to the adhesive layer 2013.

In other embodiments, the second carrier 2011 may be directly attached to the inner circuit layer 10.

In a fourth step, referring to fig. 4, a first via 61 penetrating the third copper layer 2012 to the inner circuit layer 10 is formed, and a second via 62 penetrating the second copper layer 1013 to the inner circuit layer 10 is formed.

The first through hole 61 and the second through hole 62 extend to the first shielding line 12 of the inner circuit layer 10.

In this embodiment, the first through hole 61 and the second through hole 62 are formed by laser cutting. In other embodiments, the first through hole 61 and the second through hole 62 may also be formed by mechanical cutting, etching, or other methods.

In a fifth step, referring to fig. 5, the first via hole 61 and the second via hole 62 are filled to form a first conductive hole 611 and a second conductive hole 621, respectively.

The first conductive via 611 and the second conductive via 621, which are coaxially disposed, form a conductive via 60.

In at least one embodiment, the first conductive via 611 and the second conductive via 621 are formed by electroplating copper on the first via 61 and the second via 62, respectively. It is understood that in other embodiments, the conductive material may also be filled.

In a sixth step, referring to fig. 6, a first outer circuit layer 20 is formed on the third copper layer 2012 and a second outer circuit layer 30 is formed on the second copper layer 1013.

The first outer circuit layer 20 includes a power line 21, a control line 22 and a second shielding line 23. The second shield line 23 is provided around the power supply line 21 and the control line 22.

The second outer circuit layer 30 includes a power voltage line 31 and a third shielding line 32. The third shielding line 32 is disposed around the power supply voltage line 31.

Seventh, referring to fig. 7, a first cover layer 40 is attached on the first outer circuit layer 20, and a second cover layer 50 is attached on the second outer circuit layer 30.

The first cover layer 40 is provided with a first opening 401 to expose the conductive via 60. The second cover layer 50 is provided with a second opening 501 to expose the conductive via 60.

In an eighth step, referring to fig. 8, a first shielding layer 71 is formed on the first cover layer 40 and a second shielding layer 72 is formed on the second cover layer 50.

The first shielding layer 71 and the second shielding layer 72 may be formed by electroplating or chemical plating. The first shielding layer 71 partially extends into the first opening 401 to connect to the conductive via 60. The second shielding layer 72 partially extends into the second opening 501 to connect with the conductive via 60.

Referring to fig. 16, a circuit board 200 according to a third embodiment of the present invention includes a circuit layer 210, and a first shielding line 220 and a second shielding line 230 respectively disposed on two sides of the circuit layer 210.

The circuit layer 210 includes a signal line 211, a power line 212, a control line 213, a power voltage line 214, and a third shielding line 215. The third shielding line 215 is located between the signal line 211 and the power line 212, the control line 213, and the power voltage line 214. The third shielding line 215 also surrounds the signal line 211, the power line 212, the control line 213, and the power voltage line 214.

The signal line 211 is a strip line; the power line 212, the control line 213 and the power voltage line 214 are microstrip lines.

The first shielding line 220 covers the entire circuit layer 210. The second shielding line 230 covers the signal line 211 and exposes the power line 212, the control line 213, and the power voltage line 214.

In the illustrated embodiment, the circuit board 200 further includes a first cover layer 240 and a second cover layer 250. The first cover layer 240 is disposed on the first shield line 220. The second cover layer 250 is disposed on the second shielding line 230 and the circuit layer 210 exposed from the second shielding line 230.

The first cover layer 240 includes a first glue layer 241 and a first protection layer 242. The first glue layer 241 is adjacent to the first shielding line 220. The second cover layer 250 includes a second glue layer 251 and a second protection layer 252. The second glue layer 251 is adjacent to the circuit layer 210.

The circuit board 200 also includes a plurality of conductive vias 260. Each conductive via 260 is electrically connected to the first shield line 220, the second shield line 230, and the third shield line 215. The plurality of conductive holes 260 are used for grounding to shield interference.

The circuit board 200 also includes a shield layer 270. The shielding layer 270 is disposed on the first cover layer 240 and faces the power line 212, the control line 213, and the power voltage line 214. The shielding layer 270 is electrically connected to the third shielding line 215.

In the fourth embodiment of the present application, a method for manufacturing the circuit board 200 of the third embodiment is provided. The manufacturing method of the circuit board comprises the following steps:

first, referring to fig. 9, a first copper-clad unit 201 is provided, where the first copper-clad unit 201 includes a first carrier 3011, and a first copper layer 3012 and a second copper layer 3013 respectively disposed on two sides of the first carrier 3011.

The second copper layer 3013 is the first shielding line 220.

In a second step, referring to fig. 10, a circuit layer 210 is formed on the first copper layer 3012.

Third, referring to fig. 11, a second copper-clad unit 202 is provided, where the second copper-clad unit 202 includes a second carrier 2021 and a third copper layer 2022 disposed on one side of the second carrier 2021, and the second carrier 2021 is attached to the circuit layer 210.

In at least one embodiment, an adhesive layer 2023 is coated on the circuit layer 210, and the second carrier 2021 is attached to the adhesive layer 2023.

The adhesive layer 2023 is coated on the signal line 211 and a portion of the third shielding line 215. The adhesive layer 2023 does not cover the power supply line 212, the control line 213, and the power supply voltage line 214.

In a fourth step, referring to fig. 12, a first via 261 is formed in the third copper layer 2022 and penetrates through the circuit layer 210, and a second via 262 is formed in the second copper layer 3013 and penetrates through the circuit layer 210.

The first via 261 and the second via 262 both extend to the third shielding line 215 of the circuit layer 210.

The second copper-clad unit 202 not connected with the adhesive layer 2023 does not have the first through hole 261.

In a fifth step, referring to fig. 13, the first via 261 and the second via 262 are filled to form a first conductive hole 2611 and a second conductive hole 2621, respectively.

The first through hole 261 and the second through hole 262, which are coaxially arranged, form a conductive hole 260.

In a sixth step, referring to fig. 14, the second copper-clad unit 202 located above the power line 212, the control line 213, and the power voltage line 214 is removed.

That is, the second copper-clad unit 202 to which the adhesive layer 2023 is not attached is removed. A portion of the second copper clad unit 202 may be removed by etching, laser cutting, or the like.

The third copper layer 2022 remaining after the removal is the second shielding line 230 (see fig. 15).

In the seventh step, referring to fig. 15, the first cover layer 240 and the second cover layer 250 are respectively attached to two sides of the structure obtained in the sixth step.

The first capping layer 240 covers the third copper layer 2022 and the circuit layer 210. The second capping layer 250 covers the second copper layer 3013.

The first cover layer 240 is provided with a first opening 2401 to expose a portion of the third shielding line 215.

The first cover layer 240 includes a first glue layer 241 and a first protection layer 242. The second cover layer 250 includes a second glue layer 251 and a second protection layer 252.

In an eighth step, referring to fig. 16, a shielding layer 270 is formed on the first cover layer 240.

The shielding layer 270 partially extends into the first opening 2401 to connect the third shielding line 215.

The circuit board 100, 300 of the present application places the

signal line

11, 211 in an inner layer to reduce interference. The

power supply line

21, 212, the control line 22, 2213, and the power

supply voltage line

31, 214 are disposed at the outer layer. According to the calculation formula of the allowable current, the current carrying capacity of the circuit at the outer layer is two parts of the inner layer. Therefore, the

power lines

21, 212, the control lines 22, 2213 and the

power voltage lines

31, 214 are disposed in the outer layer, which has the advantages of line width and current carrying. Therefore, the overall volume of the circuit board 100, 300 can be reduced.

Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a circuit board, includes inlayer circuit layer, locates respectively the first outer circuit layer and the second outer circuit layer of inlayer circuit layer both sides, its characterized in that: the inlayer circuit layer includes the signal line, first outer circuit layer includes power cord and control line, second outer circuit layer includes power supply voltage line, the power cord the control line reaches power supply voltage line is in the orthographic projection on inlayer circuit layer with the signal line staggers.

2. The circuit board of claim 1, wherein: the inner layer circuit layer further comprises a first shielding wire which surrounds the signal wire; the first outer layer circuit layer further comprises a second shielding wire, and the second shielding wire surrounds the power line and the control line; the second outer layer circuit layer further includes a third shield line surrounding the supply voltage line.

3. The circuit board of claim 2, wherein: the circuit board further comprises a plurality of conductive holes, each conductive hole is electrically connected with the first shielding wire, the second shielding wire and the third shielding wire, and the conductive holes are used for grounding.

4. The circuit board of claim 3, wherein: the circuit board further comprises a first covering layer covering the first outer layer circuit layer and a second covering layer covering the second outer layer circuit layer.

5. The circuit board of claim 4, wherein: the circuit board further comprises a first shielding layer and a second shielding layer, the first shielding layer is arranged on the first covering layer, the second shielding layer is arranged on the second covering layer, the orthographic projection of the inner layer circuit layer and the signal line are staggered, and the first shielding layer and the second shielding layer are respectively electrically connected with the conductive hole.

6. The circuit board of claim 1, wherein: the signal line adopts a strip line; the power line, the control line and the power voltage line adopt microstrip lines.

7. A circuit board comprising a wiring layer, characterized in that: the circuit layer includes signal line, power cord, control line and mains voltage line, the circuit board is still including locating respectively the first shielded wire and the second shielded wire of circuit layer both sides, first shielded wire covers whole circuit layer, the second shielded wire covers the signal line exposes power cord, control line and mains voltage line.

8. The circuit board of claim 7, wherein: the circuit layer further comprises a third shielding line, the third shielding line is located between the signal line and the power line, the control line and the power voltage line, and the third shielding line further surrounds the outer side of the signal line, the power line, the control line and the power voltage line.

9. The circuit board of claim 8, wherein: the circuit board further comprises a plurality of conductive holes, each conductive hole is electrically connected with the first shielding wire, the second shielding wire and the third shielding wire, and the conductive holes are used for grounding.

10. The circuit board of claim 9, wherein: the circuit board further comprises a first covering layer and a second covering layer, the first covering layer is arranged on the first shielding wire, and the second covering layer is arranged on the second shielding wire and the circuit layer exposed from the second shielding wire.

11. The circuit board of claim 10, wherein: the circuit board further comprises a shielding layer, the shielding layer is arranged on the first covering layer and is right opposite to the power line, the control line and the power voltage line, and the shielding layer is electrically connected with the third shielding line.