CN113659030A - CMOS SPAD photoelectric device with deep N trap with inverse doping distribution - Google Patents
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Abstract
The invention provides a CMOS SPAD photoelectric device with a deep N well with inverse doping distribution, which comprises a P substrate, wherein the P substrate is provided with the deep N well, a central N well and a P + layer, the two sides of the deep N well are provided with the N wells, the deep N well adopts an inverse doping distribution structure, namely, the concentration of the deep N well close to the surface of the device is lower, the concentration of the deep N well is higher along with the increase of the longitudinal depth far away from the surface of the device, transverse diffusion exists between the N wells at the two sides in the deep N well and the central N well, and N is formed at the edge of a PN junction‑The virtual guard ring is characterized in that when incident photons are emitted into the device and are mainly absorbed by the deep N well, most photons can be utilized by the P + layer/central N well junction to form photon-generated carriers, and only few photons penetrate through the deep N well to form the photon-generated carriers on the P substrate.
Description
Technical Field
The invention belongs to the field of semiconductor photoelectric detection and sensing, relates to the structural design of an APD photoelectric device, and particularly relates to the design of a CMOS SPAD photoelectric device with high photon detection efficiency.
Background
The Single photon Avalanche Diode (Single photon Avalanche Diode) is widely applied to the fields of automotive electronics, three-dimensional imaging, instruments and meters, biophotonics, fluorescence lifetime imaging and the like due to the characteristic of Single photon sensitivity, and is a semiconductor photoelectric detector adopting a PN junction structure and working in a Geiger mode (reverse bias voltage is greater than breakdown voltage). When photons irradiate the PN junction, photon-generated carriers are accelerated to move to an avalanche region and generate a multiplication effect, so that the single photons can trigger a large-current pulse signal. With the expansion of the application field, the performance requirements of SPAD are higher and higher, and especially the demand of SPAD devices with high detection efficiency is gradually increased.
Silicon-based SPAD devices have been extensively studied by many researchers. However, the performance of silicon-based SPAD devices is greatly limited due to the small optical absorption coefficient of silicon in the visible wavelength range. For example, the penetration depth of light in silicon at 700nm wavelength is about 5 μm, much larger than the depletion region thickness of a conventional SPAD, which results in the generation of a large fraction of carriers in the substrate. In order to improve the detection efficiency and the responsivity, a double-junction SPAD structure has been proposed to widen the thicknesses of a depletion region and an absorption region thereof, so that the device performance is further improved, and the field range of the engineering application thereof is continuously widened.
(however, when the technology is used, the band-to-band tunneling effect of a photogenerated carrier is easy to occur when the device is subjected to avalanche breakdown, the value of the dark current of the device is increased, and the noise performance of the device is not favorably improved.)
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A CMOS SPAD photonics device having a deep N-well with an inverse doping profile is presented that improves detection efficiency. The technical scheme of the invention is as follows:
a CMOS SPAD photoelectric device with a deep N well with inverse doping distribution comprises a P substrate, wherein the P substrate is provided with the deep N well, a central N well and a P + layer, the two sides of the deep N well are provided with the N wells, the deep N well adopts an inverse doping distribution structure, namely the concentration of the deep N well close to the surface of the device is lower, the concentration of the deep N well is higher along with the increase of the longitudinal depth far away from the surface of the device, transverse diffusion exists between the N wells on the two sides in the deep N well and the central N well, and N is formed at the edge of a PN junction-The virtual guard ring, when incident photons are injected into the device and are mainly absorbed by the deep N well, most photons can be utilized by the P + layer/central N well junction to form photon-generated carriers, and only few photons are emittedPenetrating the deep N well to form photon-generated carriers on the P substrate,
further, the thickness of the P + layer is 1.5-2.5 μm, and the P + layer is used for increasing the junction depth of the PN junction.
Furthermore, the concentration and the thickness of the P + layer, the concentration of the central N well layer and the thickness parameter of the reverse doping distribution deep N well are 3.5-4.5 μm and are adjustable.
Furthermore, the adjustable basis of the concentration and thickness of the P + layer, the concentration of the central N well layer and the thickness parameter of the counter doping distribution deep N well is as follows: firstly, analyzing main performance indexes of the device through a theoretical model, and roughly determining main parameters of the device; and performing simulation verification on the above main parameters through process and device simulation analysis to obtain different quantum efficiency characteristic curves, thereby obtaining a photon detection efficiency characteristic curve.
Further, the concentration range of the counter doping distribution deep N well is 1 x 1016/cm-3-6×1016/cm-3。
Furthermore, the surface of the CMOS SPAD photoelectric device is also provided with a layer of antireflection film for improving the quantum efficiency of the device.
Further, the anti-reflection film adopts SiO2。
The invention has the following advantages and beneficial effects:
the photon absorption region of the common SPAD device adopts a thinner N trap, so that a part of photons generate carriers on a substrate, the utilization rate of a PN junction to incident photons is greatly reduced, the device is not favorable for fully absorbing the photons, and the detection efficiency is lower. The design method is that a P +/central N well junction is manufactured in a deep N well with inverse doping distribution, and N wells are added on the left side and the right side inside the deep N well, so that a virtual protection ring is formed at the edge of a PN junction. Compared with the conventional CMOS SPAD device, the device designed by the invention obviously improves the detection efficiency of the device. The novel CMOS SAPD device structure with high detection efficiency can effectively overcome the design defects of the traditional CMOSSPAD device, and the device structure is designed as follows:
the SPAD device designed by the invention is a planar structure of P +/central N well/inverse doped deep N well/P substrate. The P +/central N well forms an avalanche region of the device, and the photogenerated carriers collide and ionize in the region to enable the device to generate avalanche breakdown, so that a large-current pulse signal is formed at an output port of the device; the inversely doped deep N well is a photon absorption region of the device, and the doping mode of the region is inversely doped distribution, namely the concentration of the deep N well close to the surface of the device is lower, and the concentration of the deep N well close to the P substrate is higher, so that the electric field distribution of the device is mainly optimized; and transverse diffusion exists between the two side N wells and the central N well in the reverse doping distribution deep N well, so that a virtual protection ring is formed at the edge of the PN junction. The device is characterized in that: and manufacturing a P +/central N well junction in the inversely-doped deep N well, and adding N wells at the left side and the right side inside the inversely-doped deep N well. When a light source irradiates the surface of the device, photons are absorbed by an absorption region of the device, the absorption region (deep N well) of the device is different from an absorption region (N well) of a common device, the thickness of the absorption region is much thicker, the probability that the photons penetrate through the deep N well and flow to a P substrate is reduced, the photon utilization rate of a PN junction in the deep N well is improved, and the photon detection efficiency of the device can be remarkably improved. Meanwhile, the N wells on two sides in the deep N well and the central N well core are laterally diffused, so that a virtual protection ring is formed at the edge of the PN junction, and the PN junction is restrained from being subjected to early edge breakdown, therefore, the quantum efficiency of the device is improved, and the photon detection efficiency of the device is further improved.
Drawings
FIG. 1 is a block diagram of a CMOS SPAD optoelectronic device with deep N-well with counter doping profile according to a preferred embodiment of the present invention;
FIG. 2 is a graph of electron and hole avalanche generation rates for a novel CMOS SAPD;
FIG. 3 is a graph of the spectral response of a novel CMOS SAPD;
fig. 4 is a graph of the photon detection efficiency characteristics of the novel CMOS SAPD.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
fig. 1 shows a structure diagram of a novel CMOS SPAD optoelectronic device. As can be seen, the device is a planar structure consisting of P +/central N well/counter-doped deep N well/P substrate. The P +/central N well forms an avalanche region (corresponding to the region 11 in the figure) of the device, and photogenerated carriers are subjected to impact ionization in the region and multiplied, so that a current which can be observed by naked eyes is formed, and photoelectric conversion is realized. The reversely doped deep N well forms a photon absorption region (corresponding to a region 12 in the figure) of the device, the reversely doped deep N well means that the concentration of the deep N well close to the surface of the device is lower, and the concentration of the deep N well is higher along with the increase of the depth of the device, and the doping mode is mainly adopted to optimize the electric field distribution of the device; and secondly, the thickness of the photon absorption region is deepened by adopting the deep N well, so that the device can fully absorb photons, and the detection efficiency of the device is improved. Meanwhile, transverse diffusion exists between the N wells on the two sides in the deep N well and the central N well, so that a virtual protection ring is formed at the edge of the PN junction, the early edge breakdown of the device is avoided, and the detection efficiency of the device is further optimized.
Fig. 2 shows a graph of the electron and hole avalanche generation rates of the novel CMOS SPAD, which is mainly related to the size of the electric field device of the device and the initial position of the photogenerated carriers. It can be seen that the avalanche generation rate of electrons is about 70% and the avalanche generation rate of holes is 0 in the range of 0-2 μm in the longitudinal depth of the device. Under the condition of reverse bias voltage, the direction of electric field intensity points to a P + region from a central N well, the mobility of electrons is much higher than that of holes, and the electrons move to the P + region under the action of the electric field to generate impact ionization, so that an avalanche effect is caused. In the range of 2-2.2 μm in the depth of the device in the longitudinal direction, the avalanche generation rate of electrons is 0 and the avalanche generation rate of holes is about 50%. This is because holes move toward the central N-well region under the influence of an electric field in the region, causing an avalanche effect.
Fig. 4 shows a spectral response characteristic diagram of the novel CMOS SPAD device. The responsivity is an index for measuring the photoelectric conversion capability of the device, and is mainly related to the optical window area and the quantum efficiency of the device. In addition, the wavelength of incident light has a certain influence on the responsivity, because the absorption effect of the materials used in the device on different wavelengths of incident light is different. For example, the silicon material has a good light absorption effect in the range of 400nm-1100nm, and the indium gallium arsenic material has a good light wavelength responsivity in the range of 900nm-1700 nm. The general measure for improving the responsivity of the device is to appropriately reduce the optical window area of the device, and the optical window area of the device designed by the invention is 10 μm × 10 μm, and the spectral response of the device is shown in fig. 3. As can be seen from the graph, the responsivity reaches the peak value of about 0.64A/W at the wavelength of 650nm, and the responsivity is more than 0.45A/W in the wavelength range of 800nm to 1000nm, so that the device can carry out good detection in the near infrared band. The fourth graph shows the photon detection efficiency characteristic of the novel CMOS SPAD device. Photon detection efficiency is the probability that an incident photon triggers an avalanche and is successfully detected, and is mainly related to the absorption coefficient, the depth of the multiplication region and the thickness of the device. It can be seen that the photon detection efficiency peaks at about 68% at a wavelength of 600nm, and drops sharply in the wavelength range of 600nm to 1000nm, which may be caused by too poor absorption coefficient of the device in this wavelength range.
In the design process of the CMOS SPAD photoelectric detector, a specific design method based on the device structure is provided. The design idea adopted is described as follows:
firstly, the structure starts from the aspects of increasing the thickness of the absorption region of the device and optimizing the quantum efficiency of the device to improve the photon detection efficiency of the device. The deep N trap with inverse doping distribution is added in the SPAD device to increase the thickness of the photon absorption region, so that most photons are utilized by the PN junction, and the photon detection efficiency of the device is improved. The N wells are added on two sides of the deep N well with the inverse doping distribution, so that a virtual protection ring is formed at the edge of the PN junction, the premature edge breakdown of the device is inhibited, and the purpose of optimizing the quantum efficiency of the device is achieved.
And secondly, the technological parameters and the structural parameters of the device are adjustable. That is, the concentration and thickness of the P + layer of the device, and the concentration of the central N well layerThe parameters such as the degree, the thickness of the inverse doping distribution deep N well and the like are adjustable. Firstly, analyzing main performance indexes of the device through a theoretical model, and roughly determining the main parameters of the device as follows: the concentration of the P + layer was 5X 1019/cm-3The thickness is 2 mu m; the concentration of the central N well is 5 x 1017/cm-3The thickness is 0.4 mu m; the concentration of N-well on both sides is 3 × 1017/cm-3The thickness is 0.5 mu m; the concentration of P substrate is 1.2 × 1015/cm-3(ii) a The deep N-well thickness is 4 μm. And performing simulation verification on the above main parameters through process and device simulation analysis to obtain different quantum efficiency characteristic curves, thereby obtaining a photon detection efficiency characteristic curve. Meanwhile, an antireflection film (SiO) can be added on the surface of the device2) To improve the quantum efficiency of the device.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.
Claims (7)
1. A CMOS SPAD photoelectric device with a deep N well with inverse doping distribution comprises a P substrate, wherein the P substrate is provided with the deep N well, a central N well and a P + layer, and N wells are arranged on two sides of the deep N well-And when incident photons are emitted into the device and are mainly absorbed by the deep N well, most photons can be utilized by the P + layer/central N well junction to form photon-generated carriers, and only few photons penetrate the deep N well to form the photon-generated carriers on the P substrate.
2. The CMOS SPAD optoelectronic device with deep N-well with retrograde doping profile of claim 1, wherein the thickness of the P + layer is 1.5 μm-2.5 μm for increasing PN junction depth.
3. The CMOS SPAD optoelectronic device with the deep N-well having the retrograde doping profile of claim 1, wherein the concentration and thickness of the P + layer, the concentration of the central N-well layer, and the thickness parameter of the deep N-well having the retrograde doping profile are adjustable from 3.5 μm to 4.5 μm.
4. The CMOS SPAD optoelectronic device with the deep N-well having the inverse doping profile as claimed in claim 3, wherein the concentration and thickness of the P + layer, the concentration of the central N-well layer and the thickness parameter of the deep N-well having the inverse doping profile can be adjusted according to the following: firstly, analyzing main performance indexes of the device through a theoretical model, and roughly determining main parameters of the device; and performing simulation verification on the above main parameters through process and device simulation analysis to obtain different quantum efficiency characteristic curves, thereby obtaining a photon detection efficiency characteristic curve.
5. The CMOS SPAD optoelectronic device with the deep N-well having the retrograde doping profile of claim 3, wherein the concentration range of the retrograde doping profile deep N-well is 1 x 1016/cm-3-6×1016/cm-3。
6. The CMOS SPAD photoelectric device with the deep N well with the inverse doping profile as claimed in one of claims 1 to 5, wherein an anti-reflection film is further arranged on the surface of the CMOS SPAD photoelectric device for improving the quantum efficiency of the device.
7. The CMOS SPAD optoelectronic device with deep N-well having inverse doping profile as claimed in claim 6, wherein said anti-reflective film is SiO2。
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| CN114914325A (en) * | 2022-07-18 | 2022-08-16 | 西安电子科技大学 | Multi-junction near-infrared single-photon avalanche diode and preparation method thereof |
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| CN114914325A (en) * | 2022-07-18 | 2022-08-16 | 西安电子科技大学 | Multi-junction near-infrared single-photon avalanche diode and preparation method thereof |
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Application publication date: 20211116 |