CN113659003A - MOSFET with adjustable grid resistance and preparation method thereof - Google Patents
MOSFET with adjustable grid resistance and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to the field of MOSFET (metal oxide semiconductor field effect transistor), and discloses a MOSFET with an adjustable grid resistance and a preparation method thereof.
Description
Technical Field
The invention relates to the field of Metal Oxide Semiconductor Field Effect Transistors (MOSFET), in particular to a MOSFET with an adjustable grid resistance and a preparation method thereof.
Background
In practical applications, power devices often suffer from EMI problems, and EMI level can be effectively improved by adjusting gate resistance (Rg) of the devices, as shown in fig. 3; the conventional method comprises the following steps: 1. a resistor is externally connected to the grid; 2. increasing the gate resistance (Rg) by adjusting the device design structure;
in the method 1, a resistor is externally connected to a gate, and due to the parasitic inductance problem of the resistor, oscillation can be generated on the gate, and the circuit volume can be increased;
as for the method 2, the method of increasing Rg by adjusting the device design structure is similar to that mentioned in patent CN104022093A, and the common adjustment method is to adjust the gate resistance (Rg) by modifying 1-2 Mask versions and adjusting the position of Poly or CT wire bonding; the disadvantages of this approach are: the plate needs to be made again, so that the processing cost is increased; the plate needs to be reflowed after plate making, and the production period is long.
Both methods have great defects in actual use and have poor actual application effect.
Disclosure of Invention
The invention is realized by the following technical scheme: a gate resistance adjustable MOSFET is characterized in that an adjustable resistance structure is arranged in a gate region of the MOSFET, the adjustable resistance structure comprises a plurality of Poly bar groups respectively connected between a gate Poly leading-out end and a gate Pad, each Poly bar group comprises at least one Poly bar, a body of each Poly bar at least comprises a thick bar part and a thin bar part, the thick bar parts of all the Poly bars in one Poly bar group are electrically connected, and the thick bar parts are connected with surface metal.
In a preferred embodiment of the present invention, the poly bar includes two thin bar sections and three thick bar sections, which are arranged and connected in a thick/thin/thick manner, the thick bar section located in the middle is connected to the surface metal through a metal hole, one thick bar section located in the end is connected to the gate poly terminal, and the other thick bar section located in the end is connected to the gate Pad.
As a preferred technical scheme of the invention, the number of the poly bars contained in each poly bar group is different.
In a preferred embodiment of the present invention, the surface metals of adjacent poly bar sets are isolated from each other.
As a preferred technical solution of the present invention, a method for increasing the resistance value of the adjustable resistance structure comprises: and applying a forward pulse current on the surface metal corresponding to the poly bar group and between the grid electrode pads to blow the thin bar sections.
As a preferred technical scheme of the invention, the method for quantitatively increasing the resistance value of the adjustable resistance structure comprises the following steps: and selecting a poly bar group to be burnt and disconnected according to the number of the poly bars in the poly bar group, and applying a forward pulse current between the surface metal corresponding to the selected poly bar group and the gate Pad to ensure that the thin bar section of the selected poly bar group is burnt and disconnected.
In a preferred embodiment of the present invention, the cross-sectional area of the thin strip is 1/8-1/10 of the cross-sectional area of the thick strip.
A preparation method of a MOSFET with adjustable grid resistance comprises the following steps:
forming an epitaxial layer on the n-type substrate sheet to obtain an epitaxial wafer;
growing a barrier layer formed by injecting Ring on an epitaxial layer of the epitaxial wafer, and forming a structural wafer with a high-voltage terminal structure through Ring photoetching, injection and furnace tube annealing;
carrying out photoetching, dry etching and furnace tube wet-process oxide layer growth on the structural sheet with the high-voltage terminal structure to obtain the structural sheet with the oxide layer;
performing JFET injection and well pushing on the surface of the structural sheet with the oxide layer, which corresponds to the N-epitaxial drift region, so as to form a JFET region and obtain the structural sheet with the JFET region;
growing a gate oxide layer on the structural sheet with the JFET area, and depositing polycrystal to form the structural sheet with a polycrystal layer;
carrying out poly photoetching and dry etching on a polycrystalline layer of the structural wafer with the polycrystalline layer to form a polycrystalline grid and a polycrystalline field oxygen region in a terminal region to obtain the structural wafer with the polycrystalline field oxygen;
carrying out P type body region injection and annealing in a region without polycrystal and field oxygen barrier on the structural sheet with polycrystal field oxygen to obtain the structural sheet with P type body region injection;
performing NSD photoetching and NSD injection on the structural sheet with the P type body region injection to form an NSD injection region, and performing NSD drive-in on the NSD injection region to obtain the structural sheet with the NSD injection region;
growing an SIN layer on the surface of the polycrystalline layer of the structural sheet in the NSD injection region to obtain a structural sheet with an SIN layer;
carrying out PSD photoetching and injection on the structure sheet with the SIN layer to form a PSD injection region, and carrying out RTA activation on the PSD injection region to obtain the structure sheet with the PSD injection region;
carrying out dielectric layer deposition on the structural sheet with the PSD injection region, and opening holes to obtain the structural sheet with the openings;
carrying out Metal sputtering, photoetching and corrosion on the structural sheet with the opening to form a gate region and a source region of the MOSFET and obtain the structural sheet with a complete front structure;
and thinning the back surface of the structural sheet with the complete front surface structure, evaporating metal on the back surface, and manufacturing a drain electrode on the back surface of the wafer to obtain a product sheet with the complete front surface structure and the complete back surface structure.
As a preferred technical scheme of the invention, the product wafer with complete front and back structures is subjected to passivation layer deposition, photoetching and corrosion to form opening areas of Gate and Source.
In conclusion, the invention has the following beneficial effects: an adjustable resistance structure is arranged between a grid Poly leading-out terminal of the MOSFET and a grid Pad, the adjustable resistor structure comprises a plurality of parallel poly bar groups, each poly bar group comprises different numbers of poly bars, namely, the resistance values of the various poly bar groups are different, when the resistance value of the adjustable resistance structure needs to be adjusted, the purpose of adjusting the adjustable resistance mechanism can be realized only by adjusting the number of the electrified poly bars in the adjustable resistance structure, because the structure of the poly strip comprises the thick strip part and the thin strip part, and the surface metal is connected outwards, it is possible to apply a forward pulse current between the surface metal corresponding to the poly bar group and the gate Pad, under the action of the forward pulse current, the thin strip part can be burnt, so that the corresponding poly strip group is disconnected, the effect of correspondingly adjusting the resistance value of the adjustable resistor structure is achieved, the actual adjusting process is simple and easy to operate, the adjusting flexibility is high, and the method is suitable for practical application; meanwhile, according to the manufacturing method of the MOSFET, the existing manufacturing layout is not required to be modified when the MOSFET is produced, the existing equipment can be directly used for preparation, and equipment resources are not additionally consumed.
Drawings
FIG. 1 is a schematic diagram of a poly strip structure for a MOSFET of the present invention;
FIG. 2 is a schematic diagram of a MOSFET of the present invention;
fig. 3 is a schematic diagram of a conventional MOSFET.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1 and 2, the present invention provides a MOSFET with adjustable gate resistance, wherein an adjustable resistance structure is disposed in a gate region of the MOSFET, the adjustable resistance structure includes a plurality of Poly bar groups respectively connected between a gate Poly terminal and a gate Pad, each Poly bar group includes at least one Poly bar, and the number of the Poly bars included in each Poly bar group is different, a body of each Poly bar includes at least one thick bar portion and one thin bar portion, specifically, each Poly bar includes two thin bar portions and three thick bar portions, the cross section of each thin bar portion has an area 1/8-1/10 which is the area of the cross section of each thick bar portion, and the thin bar portions are arranged and connected in a thick/thin/thick manner, one thick bar portion at an end is connected to the gate Poly terminal, the other thick bar portion at an end is connected to the gate Pad, and the thick bar portions of all the Poly bars in one Poly bar group are electrically connected, the thick strip part in the middle is connected with the surface metal through the metal hole, and the surface metals corresponding to the adjacent poly strip groups are isolated from each other.
Specifically, the method for increasing the resistance value of the adjustable resistance structure comprises the following steps: and applying a forward pulse current on the surface metal corresponding to the poly bar group and between the grid electrode pads to blow the thin bar sections.
Further, the method for quantitatively increasing the resistance value of the adjustable resistance structure comprises the following steps: and selecting a poly bar group to be burnt and disconnected according to the number of the poly bars in the poly bar group, and applying a forward pulse current between the surface metal corresponding to the selected poly bar group and the gate Pad to ensure that the thin bar section of the selected poly bar group is burnt and disconnected.
As an embodiment of the present invention, as shown in fig. 1, an adjustable resistance structure is disposed in the gate region of the MOSFET, and the adjustable resistance structure includes three Poly bar groups, denoted as s1, s2, and s3, between the gate Poly terminal and the gate Pad; the S1 comprises 1 Poly bar, the S2 comprises two Poly bars, the S3 comprises 3 Poly bars, all the Poly bars comprise two sections of thin bar parts and three sections of thick bar parts, the thin bar parts and the thick bar parts are arranged and connected in a thick/thin/thick mode, the thick bar parts at two ends are respectively connected with a grid electrode Poly leading-out end and a grid electrode Pad, the thick bar part in the middle is connected with a surface metal, the thick bar parts in the middle of the two Poly bars in the S2 are electrically connected, and the thick bar parts in the middle of the three Poly bars in the S3 are electrically connected.
When the MOSFET leaves a factory, s1, s2 and s3 are connected well, and when the MOSFET is used, the resistance value of the adjustable resistor structure is determined according to actual requirements, and as s1, s2 and s3 are connected in parallel between the leading-out end of the grid Poly and the grid Pad, the resistance value of the adjustable resistor structure can be increased by disconnecting s1, s2 or s 3; and due to the fact that the numbers of the poly bars in s1, s2 and s3 are different, namely the resistance values of s1, s2 and s3 are different, 6 schemes for adjusting the resistance values of the adjustable resistor structure are generated, namely the disconnection s1, the disconnection s2, the disconnection s3, the disconnection s1 and s2, the disconnection s3 and s2 and the disconnection s1 and s 3.
Taking the scheme of disconnecting s1 as an example, the specific disconnection method is as follows: applying a forward pulse current between the grid Pad and the surface metal corresponding to S1, wherein when the thin strip section is in over-current due to the large resistance of the thin strip part of the poly strip, the thin strip section is burnt due to the high local heat, so that S1 is disconnected; the same applies to other schemes of disconnecting s2, s3, s1 and s2, s3 and s2, and s1 and s3, so details are not repeated, and it can be seen that the actual step of adjusting the resistance value is simple and easy to operate, and the actual adjusting schemes are many, so that the flexibility of adjusting the resistance value is high, and the method is more suitable for practical application.
Corresponding to the MOSFET with the adjustable grid resistance, the invention also provides a corresponding preparation method, which comprises the following steps:
s1, forming an epitaxial layer on the n-type substrate sheet to obtain an epitaxial wafer; specifically, preparing a substrate material: the substrate of the epitaxial wafer is doped with an N-type (100) crystal orientation and arsenic or antimony, and the resistivity is usually less than 0.1 omega cm. Different device withstand voltages can be obtained by selecting different resistivities and thicknesses of the epitaxial wafers. Thickness of the epitaxial layer in general: 40-80um, resistivity: 9-24 omega cm, so that the withstand voltage of the MOSFET device can reach 500V-900V.
S2, growing a barrier layer formed by injecting Ring on the epitaxial layer of the epitaxial wafer, and forming a structural wafer with a high-pressure terminal structure through Ring photoetching, injection and furnace tube annealing; specifically, Ring (pressure Ring region) formation: and pre-growing an 800-1000A oxide layer on the epitaxial layer to serve as a barrier layer for Ring Ring injection, and forming a high-pressure terminal structure through Ring photoetching, injection and furnace tube annealing processes. Ion implantation energy: 100-140KeV, dose: 3E13-8E13, implant element: boron (B), annealing conditions: 1180 deg.c/300 deg.c for 500 min.
S3, carrying out photoetching, dry etching and furnace tube wet-process oxide layer growth on the structural sheet with the high-pressure terminal structure to obtain the structural sheet with the oxide layer; in particular field oxygen (Fox) growth: an oxide layer with the thickness of 20000 angstroms is grown by a furnace tube wet method through photoetching and dry etching.
S4, performing JFET injection and trap pushing on the surface, corresponding to the N-epitaxial drift region, of the structural sheet with the oxide layer to form a JFET region, and obtaining the structural sheet with the JFET region; specifically JFET injection, drive-well: phosphorus element with certain concentration is injected into the surface of the drift region (N-epitaxy), and a JFET region is formed in a region which is 3-6um close to the surface of the epitaxial layer through a high-temperature well-pushing process, so that the surface channel resistance is effectively reduced while the withstand voltage of the bottom epitaxial layer is not influenced. Implantation dose: 2E12-5E12, implant energy: 100KeV-150KeV, push trap conditions: 1150 deg.C/120 min-190 min.
S5, growing a gate oxide layer on the structural sheet with the JFET area, and depositing polycrystal to form a structural sheet with a polycrystal layer; specifically, gate oxide growth and polycrystalline (Poly) deposition: the gate oxide layer is grown with the thickness of generally 700-1200 angstroms and the growth temperature of generally 900-1000 ℃, the thickness of the deposited polycrystal is 6000-8000 angstroms, and the polycrystal is undoped polysilicon.
S6, carrying out poly photoetching and dry etching on the polycrystalline layer of the structural wafer with the polycrystalline layer to form a polycrystalline grid and a polycrystalline field oxygen region in the terminal region to obtain the structural wafer with the polycrystalline field oxygen; specifically, polycrystal photoetching and etching: poly photoetching and dry etching are carried out to form a polycrystalline grid, and a polycrystalline field oxide structure is formed in the terminal area, so that the voltage-resisting efficiency is effectively improved.
S7, carrying out P type body region injection and annealing in a region without polycrystal and field oxygen barrier on the structural sheet with polycrystal field oxygen to obtain the structural sheet with the P type body region injection; specifically, Pbody injection and annealing: in the area without polycrystal and field oxygen barrier, B element is implanted, the energy is 60KEV to 120Kev, and the dosage is adjusted according to the requirement of VTH parameters, generally about 1E13-8E 13.
S8, performing NSD photoetching and NSD injection on the structural sheet with the P type body region injection to form an NSD injection region, and performing NSD drive-in on the NSD injection region to obtain the structural sheet with the NSD injection region; in particular, NSD lithography, NSD implantation, NSD drive-in: and forming an NSD implantation area by photoetching, wherein the NSD implantation dose is formed by: 5E 15-1E 16, injection energy: 120Kev-160Kev, implant element: phosphorus. NSD drive well temperature: 950 ℃, time: for 25 minutes.
S9, growing an SIN layer on the surface of the polycrystalline layer of the structural sheet in the NSD injection region to obtain a structural sheet with the SIN layer; specifically, deposition of an SIN dielectric layer: a SIN layer with the thickness of about 1000 angstroms grows on the surface of the polycrystalline strip, and the reliability of the device can be effectively improved.
S10, carrying out PSD photoetching and injection on the structure sheet with the SIN layer to form a PSD injection area, and carrying out RTA activation on the PSD injection area to obtain the structure sheet with the PSD injection area; PSD photoetching and injection, RTA activation are concretely: forming a PSD implantation area through photoetching to form a PSD implantation dose: 5E 15-1E 16, injection energy: 120Kev-160Kev, implant element: b, it is necessary to activate the implanted atoms by an RTA (rapid annealing at 950 ℃ C. for 30 s) process.
S11, carrying out dielectric layer deposition on the structural sheet with the PSD injection area, and opening holes to obtain the structural sheet with the openings; specifically, dielectric layer deposition, hole photoetching and hole corrosion: dielectric BPSG (borophosphosilicate glass) is deposited at 11000 angstroms and then opened to form the hole contacts.
S12, carrying out Metal sputtering, photoetching and corrosion on the structural sheet with the opening to form a gate region and a source region of the MOSFET and obtain the structural sheet with a complete front surface structure, specifically sputtering Metal, Metal photoetching and corrosion: and depositing 4um of aluminum, and then photoetching and corroding the aluminum to form a gate region and a source region of the MOSFET.
S13, back thinning and back metal evaporation are carried out on the structure piece with the complete front-face structure, a drain electrode is manufactured on the back of the wafer, and the product piece with the complete front-face and back-face structures is obtained, and the method specifically comprises the following steps: back side Ti-Ni-Ag: the back of the wafer is thinned to 200-300 um, and Ti-Ni-Ag (titanium-nickel-silver) is evaporated on the back.
Specifically, passivation layer deposition, photoetching and corrosion are carried out on a product wafer with complete front and back surface structures to form opening areas of Gate and Source, specifically, the passivation layer deposition, the passivation layer photoetching and the corrosion are carried out: depositing silicon nitride 7000-12000 angstroms of passivation layer, and then etching by photolithography to form the opening region of Gate and Source.
The working principle and the using process of the invention are as follows: an adjustable resistance structure is arranged between a grid Poly leading-out terminal of the MOSFET and a grid Pad, the adjustable resistor structure comprises a plurality of parallel poly bar groups, each poly bar group comprises different numbers of poly bars, namely, the resistance values of the various poly bar groups are different, when the resistance value of the adjustable resistance structure needs to be adjusted, the purpose of adjusting the adjustable resistance mechanism can be realized only by adjusting the number of the electrified poly bars in the adjustable resistance structure, because the structure of the poly strip comprises the thick strip part and the thin strip part, and the surface metal is connected outwards, it is possible to apply a forward pulse current between the surface metal corresponding to the poly bar group and the gate Pad, under the action of the forward pulse current, the thin strip part can be burnt, so that the corresponding poly strip group is disconnected, the effect of correspondingly adjusting the resistance value of the adjustable resistor structure is achieved, the actual adjusting process is simple and easy to operate, the adjusting flexibility is high, and the method is suitable for practical application; meanwhile, according to the manufacturing method of the MOSFET, the existing manufacturing layout is not required to be modified when the MOSFET is produced, the existing equipment can be directly used for preparation, and equipment resources are not additionally consumed.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (9)
1. A MOSFET with adjustable grid resistance is characterized in that: an adjustable resistor structure is arranged in a grid region of the MOSFET, the adjustable resistor structure comprises a plurality of Poly bar groups respectively connected between a grid Poly leading-out end and a grid Pad, each Poly bar group comprises at least one Poly bar, a body of each Poly bar at least comprises a thick bar part and a thin bar part, the thick bar parts of all the Poly bars in one Poly bar group are electrically connected, and the thick bar parts are connected with surface metal.
2. A MOSFET of claim 1, wherein: the poly strip comprises two sections of thin strip parts and three sections of thick strip parts, the thin strip parts and the thick strip parts are arranged and connected in a thick/thin/thick mode, the thick strip part positioned in the middle is connected with surface metal through a metal hole, one thick strip part positioned at the end part is connected with a grid poly leading-out end, and the other thick strip part positioned at the end part is connected with a grid Pad.
3. A MOSFET of claim 1, wherein: the number of poly strands contained in each poly strand set varies.
4. A MOSFET of claim 1, wherein: the corresponding surface metals of adjacent poly bar groups are isolated from each other.
5. A MOSFET of claim 1, wherein: the method for increasing the resistance value of the adjustable resistance structure comprises the following steps: and applying a forward pulse current on the surface metal corresponding to the poly bar group and between the grid electrode pads to blow the thin bar sections.
6. A MOSFET of claim 1, wherein: the method for quantitatively increasing the resistance value of the adjustable resistance structure comprises the following steps: and selecting a poly bar group to be burnt and disconnected according to the number of the poly bars in the poly bar group, and applying a forward pulse current between the surface metal corresponding to the selected poly bar group and the gate Pad to ensure that the thin bar section of the selected poly bar group is burnt and disconnected.
7. A MOSFET of claim 1, wherein: the cross-sectional area of the thin strip is 1/8-1/10 of the cross-sectional area of the thick strip.
8. A preparation method of a MOSFET with adjustable grid resistance is characterized by comprising the following steps: the method comprises the following steps:
forming an epitaxial layer on the n-type substrate sheet to obtain an epitaxial wafer;
growing a barrier layer formed by injecting Ring on an epitaxial layer of the epitaxial wafer, and forming a structural wafer with a high-voltage terminal structure through Ring photoetching, injection and furnace tube annealing;
carrying out photoetching, dry etching and furnace tube wet-process oxide layer growth on the structural sheet with the high-voltage terminal structure to obtain the structural sheet with the oxide layer;
performing JFET injection and well pushing on the surface of the structural sheet with the oxide layer, which corresponds to the N-epitaxial drift region, so as to form a JFET region and obtain the structural sheet with the JFET region;
growing a gate oxide layer on the structural sheet with the JFET area, and depositing polycrystal to form the structural sheet with a polycrystal layer;
carrying out poly photoetching and dry etching on a polycrystalline layer of the structural wafer with the polycrystalline layer to form a polycrystalline grid and a polycrystalline field oxygen region in a terminal region to obtain the structural wafer with the polycrystalline field oxygen;
carrying out P type body region injection and annealing in a region without polycrystal and field oxygen barrier on the structural sheet with polycrystal field oxygen to obtain the structural sheet with P type body region injection;
performing NSD photoetching and NSD injection on the structural sheet with the P type body region injection to form an NSD injection region, and performing NSD drive-in on the NSD injection region to obtain the structural sheet with the NSD injection region;
growing an SIN layer on the surface of the polycrystalline layer of the structural sheet in the NSD injection region to obtain a structural sheet with an SIN layer;
carrying out PSD photoetching and injection on the structure sheet with the SIN layer to form a PSD injection region, and carrying out RTA activation on the PSD injection region to obtain the structure sheet with the PSD injection region;
carrying out dielectric layer deposition on the structural sheet with the PSD injection region, and opening holes to obtain the structural sheet with the openings;
carrying out Metal sputtering, photoetching and corrosion on the structural sheet with the opening to form a gate region and a source region of the MOSFET and obtain the structural sheet with a complete front structure;
and thinning the back surface of the structural sheet with the complete front surface structure, evaporating metal on the back surface, and manufacturing a drain electrode on the back surface of the wafer to obtain a product sheet with the complete front surface structure and the complete back surface structure.
9. The method of claim 8, wherein the method comprises the steps of: and carrying out passivation layer deposition, photoetching and corrosion on the product wafer with the complete front and back surface structures to form opening areas of the Gate and the Source.
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| CN202110854761.3A CN113659003A (en) | 2021-07-28 | 2021-07-28 | MOSFET with adjustable grid resistance and preparation method thereof |
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| CN202110854761.3A CN113659003A (en) | 2021-07-28 | 2021-07-28 | MOSFET with adjustable grid resistance and preparation method thereof |
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