CN113658923A - Packaging structure - Google Patents
Packaging structure Download PDFInfo
- Publication number
- CN113658923A CN113658923A CN202010396318.1A CN202010396318A CN113658923A CN 113658923 A CN113658923 A CN 113658923A CN 202010396318 A CN202010396318 A CN 202010396318A CN 113658923 A CN113658923 A CN 113658923A
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- CN
- China
- Prior art keywords
- circuit board
- printed circuit
- package
- chip
- injection hole
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A package structure includes a package module, a printed circuit board, and an epoxy layer between the package module and the printed circuit board. The printed circuit board is provided with at least one injection hole penetrating through the printed circuit board, and the injection hole leads to the space between part of the adjacent conductive welding balls, so that the underfill of the epoxy resin can be injected into and fill the central area of the packaging module and the space between the central area of the packaging module and the printed circuit board through the injection hole.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to an epoxy layer disposed in a space between a chip and a printed circuit board of a package structure.
Background
Due to the trend of increasing density of semiconductor chip packages, fine pitch ball grid array (FBGA) packages have been developed to allow for a reduction in semiconductor package profile and to provide increased package density. Generally, an FBGA package includes a semiconductor die having a lead frame mounted to the top surface of a Printed Circuit Board (PCB). The semiconductor die has a plurality of bonding pads electrically connected to the lead frame. In addition, bonding wires are used to connect the bonding pads on the semiconductor die and the conductive pads on the leadframe. Conductive elements, such as solder balls, are bonded to conductive traces on the PCB. The semiconductor die, the lead frame and the bonding wires are encapsulated by an encapsulant.
PCB manufacturers use Ball Grid Array (BGA) and other high density Array packages to reduce the board space required for a particular product. To reduce circuit board space, PCB manufacturers have used smaller pitch solder ball pitches, i.e., the pitch between a row of solder balls and a column of solder balls. To use these smaller pitches, PCB manufacturers are more demanding to use expensive techniques to manufacture PCBs.
When PCB manufacturers have used smaller pitch solder ball pitches, the high heat generated must be removed. At present, the common heat dissipation method in the industry is to conduct heat to external metal and heat-conducting medium through metal heat radiators, heat pipe heat radiators, fans, graphite patches, metal sheets, heat-conducting pads and the like, or to dissipate heat through air convection. However, the heat dissipation effect of these heat dissipation methods is still not good.
Disclosure of Invention
The main objective of the present invention is to provide a package structure, which can add one or more than one injection hole on the PCB located on the back of BGA, so that the injection head of the automatic dispensing machine can inject the epoxy resin into the space between the PCB and the center of BGA through the injection hole, and after the epoxy resin is diffused outwards, the epoxy resin can fill the space between the BGA and the PCB more easily.
In addition, when the PCB is punched, if the front and back surfaces of the PCB are connected with the BGA, the two BGA can be arranged in a staggered mode, and a required injection hole is reserved in the PCB so as to facilitate filling of epoxy resin glue. The method can facilitate the processing operation, and can isolate the heat energy generated by the BGA on the front side and the back side due to the operation without mutual influence.
In view of the above, a package structure is provided that includes a first package module, a printed circuit board, and a first thermal insulating layer. The first package module includes a first chip and a plurality of first conductive solder balls located under the first chip. The printed circuit board comprises a plurality of first pins positioned on the first surface of the printed circuit board and used for being respectively and electrically connected with the first conductive solder balls. The first thermal insulation layer is filled in a space between the first chip and the printed circuit board, wherein the first thermal insulation layer comprises epoxy resin.
According to an embodiment, the first package module may be a Ball-grid array (BGA) package.
According to another embodiment, the printed circuit board further comprises at least one first injection hole, wherein the at least one first injection hole penetrates through the printed circuit board and leads to a part of the space between adjacent first conductive solder balls.
According to another embodiment, the space width of each of the first conductive solder balls is fixed.
According to another embodiment, the package further comprises a second packaging module and a second thermal insulation layer. The second package module includes a second chip and a plurality of second conductive solder balls located under the second chip. Moreover, the printed circuit board further comprises a plurality of second pins located on the second surface of the printed circuit board for electrically connecting the second conductive solder balls, respectively. The second thermal insulation layer is filled in a space between the second chip and the printed circuit board, wherein the second thermal insulation layer contains the epoxy resin.
According to another embodiment, the second package module may be a ball grid array package.
According to yet another embodiment, the printed circuit board further comprises at least one second injection hole, wherein the at least one second injection hole penetrates through the printed circuit board and leads to a part of the second conductive solder balls between adjacent second conductive solder balls
According to another embodiment, the spacing width of each of the second conductive solder balls is constant.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a schematic diagram illustrating an operation structure of a package structure according to an embodiment of the invention.
FIG. 2 is a schematic diagram illustrating an operation structure of a package structure according to another embodiment of the invention.
Description of the reference numerals
100. 200: packaging structure
110: printed circuit board
110 a: first side
110 b: second surface
112 a: first pin
112 b: second connecting pin
114 a: a first injection hole
114 b: second injection hole
120 a: first packaging module
120 b: second package module
122 a: first chip
122 b: second chip
124 a: first conductive solder ball
124 b: second conductive solder ball
130 a: a first epoxy resin layer
130 b: second epoxy resin layer
150 a: first syringe
150 b: second syringe
Detailed Description
The embodiments of the invention will be described in detail with reference to the accompanying drawings, which are simplified schematic drawings and illustrate only the components and combinations thereof, which are relevant to the invention, by way of example structures or methods. Thus, the components shown in the figures are not necessarily to scale relative to actual implementation quantities, shapes, and sizes, and some of the dimensional ratios may be exaggerated or simplified to provide a clearer illustration. The actual implementation numbers, shapes or size ratios may be of selective design and arrangement, and the detailed component layout may be more complex.
FIG. 2 is a schematic diagram illustrating an operation structure of a package structure according to an embodiment of the invention. In fig. 2, the package structure 100 includes a first package module 120a, a printed circuit board 110, and a first epoxy layer 130 a. The first package module 120a includes a first chip 122a and a plurality of first conductive solder balls 124a under the first chip 122 a. The printed circuit board 110 includes a plurality of first pins 112a located on a first surface 110a of the printed circuit board and at least one first injection hole 124a penetrating the printed circuit board 110. The first pins 112a are electrically connected to the first conductive solder balls 124a, respectively, and the at least one first injection hole 114a leads to a portion of the first conductive solder balls 124a adjacent to each other. The first epoxy layer 130a is disposed between the first chip 120a and the printed circuit board 110 and partially within the at least one first injection hole 114 a. The first epoxy layer 130a is filled up by injecting an epoxy resin as an underfill into the gap between the first chip 120a and the printed circuit board 110 through the at least one first injection hole 114a using a first syringe 150 a.
FIG. 2 is a schematic diagram illustrating an operation structure of a package structure according to another embodiment of the invention. In fig. 2, in addition to the components of the package structure 100 shown in fig. 1, the package structure 200 further includes a second package module 120b including a second chip 122b and a plurality of second conductive solder balls 124b under the second chip 122 b. Moreover, the printed circuit board 110 further includes a plurality of second pins 112b located on the second surface 110b of the printed circuit board 110 and at least one second injection hole 114b penetrating through the printed circuit board 110. The second pins 112b are used to electrically connect the second conductive solder balls 124b, respectively, and the at least one second injection hole 114b leads to a portion of the space between the adjacent second conductive solder balls 124 b. The second epoxy layer 130b is located between the second chip 122b and the printed circuit board 110 and within the at least one second injection hole 114 b. The second epoxy layer 130b is filled with an epoxy resin as an underfill injected into the gap between the second chip 120b and the printed circuit board 110 through the at least one second injection hole 114b using a second injector 150 b.
The first package module 120a and the second package module 120b may be Ball-grid arrays (BGAs), such as a fine-pitch Ball grid array (FBGA) package, a very fine-pitch Ball grid array (VFBGA) package, a micro Ball grid array (μ BGA) package, or a Window Ball Grid Array (WBGA) package, but not limited thereto.
In summary, the present invention utilizes the characteristics of the epoxy resin used for underfill to add one or more injection holes on the PCB located on the back side of the BGA, so that the injection head of the automatic dispensing machine can inject the epoxy resin into the space between the PCB and the center of the BGA through the injection holes, and further diffuse outward, so that the epoxy resin can more easily fill the space between the BGA and the PCB. Thus, the problem of incomplete filling of epoxy resin, which is common in general, can be improved.
In addition, when the PCB is punched, if the front and back surfaces of the PCB are connected with the BGA, the two BGA can be arranged in a staggered mode, and a required injection hole is reserved in the PCB so as to facilitate filling of epoxy resin glue. The method can facilitate the processing operation, and can isolate the heat energy generated by the BGA on the front side and the back side due to the operation without mutual influence.
Therefore, the thermal energy generated by the chip in the BGA can be prevented from being conducted to and accumulated on the PCB through the injection filling mode of the epoxy resin. Therefore, the direction of heat energy conduction can be controlled, and the heat energy can be conducted to the outside to be in contact with the outside air by the shortest route, so that a large amount of heat energy is prevented from being accumulated in the packaging structure. The relevant experiments were performed with NP Nano Module as described in tables 1-4 below.
Next, a temperature test experiment using NP Nano Module (NP Nano Module) was performed. In this module, there is a PCIe slot on the PCB, and a μ SSD with SATA interface is inserted in the PCIe slot. The Iometer for testing is a software suite that measures subsystem I/O data for individual systems and clustered systems (cluster systems).
Table 1: temperature test data of NP nano module without heat sink.
| Without radiating fins | PCIe | uSSD |
| Raising the temperature to 30 ℃ at normal temperature | 59℃ | 53℃ |
| Standing at 30 deg.C for 15 min | 56℃ | 49℃ |
| Run Iometer 15 min at 30 ℃ | 86℃ | 68℃ |
| Raising the temperature of 30 ℃ to 70 DEG C | 92℃ | 83℃ |
| Standing at 70 deg.C for 15 min | 118℃ | 103℃ |
| Run Iometer 15 min at 70 ℃ | 126℃ | 108℃ |
Table 2: temperature test data of NP nano module without heat sink but filled with epoxy resin, wherein the epoxy resin is commercially available epoxy resin.
| Encapsulating (without radiating fin) | PCIe | uSSD |
| Raising the temperature to 30 ℃ at normal temperature | 42℃ | 43℃ |
| Standing at 30 deg.C for 15 min | 40℃ | 41℃ |
| Run Iometer 15 min at 30 ℃ | 57℃ | 57℃ |
| Raising the temperature of 30 ℃ to 70 DEG C | 82℃ | 82℃ |
| Standing at 70 deg.C for 15 min | 86℃ | 86℃ |
| Run Iometer 15 min at 70 ℃ | 94℃ | 96℃ |
Table 3: the temperature test data of NP nano module installed with stainless steel heat sink.
| Heat radiating fin (stainless steel) | PCIe | uSSD |
| Raising the temperature to 30 ℃ at normal temperature | 50℃ | 49℃ |
| Standing at 30 deg.C for 15 min | 48℃ | 48℃ |
| Run Iometer 15 min at 30 ℃ | 75℃ | 76℃ |
| Raising the temperature of 30 ℃ to 70 DEG C | 90℃ | 89℃ |
| Standing at 70 deg.C for 15 min | 104℃ | 106℃ |
| Run Iometer 15 min at 70 ℃ | 105℃ | 106℃ |
Table 4: the temperature test data of the NP nano module with the aluminum heat sink is provided.
| Heat radiating fin (aluminium) | PCIe | uSSD |
| Raising the temperature to 30 ℃ at normal temperature | 46℃ | 45℃ |
| Standing at 30 deg.C for 15 min | 45℃ | 44℃ |
| Run Iomter 15 min at 30 ℃ | 68℃ | 67℃ |
| Raising the temperature of 30 ℃ to 70 DEG C | 86℃ | 86℃ |
| Standing at 70 deg.C for 15 min | 85℃ | 84℃ |
| Run Ioemter 15 min at 70 ℃ | 94℃ | 94℃ |
Comparing tables 2-4, it can be seen that the module using only epoxy potting at 30 ℃ exhibited better heat dissipation than the module using stainless steel fins, but slightly worse than the module using aluminum fins, regardless of the Iometer program. However, when the ambient temperature rises to 70 ℃, the heat dissipation performance of the module using only epoxy resin potting is equivalent to that of the module using aluminum heat dissipation plates, no matter whether the Iometer program is available or not. The result shows that the epoxy resin potting adhesive can effectively achieve the effect of heat dissipation.
Claims (8)
1. A package structure, comprising:
a first package module comprising:
a first chip; and
a plurality of first conductive solder balls located under the first chip;
a printed circuit board, the printed circuit board comprising:
the first pins are positioned on the first surface of the printed circuit board and are respectively and electrically connected with each first conductive welding ball; and
and the first heat insulation layer is filled in the space between the first chip and the printed circuit board, wherein the first heat insulation layer contains epoxy resin.
2. The package structure of claim 1, wherein the first package module comprises a ball grid array package.
3. The package structure of claim 1, wherein the printed circuit board further comprises at least one first injection hole, wherein the at least one first injection hole penetrates through the printed circuit board and leads to a portion of the space between adjacent first conductive solder balls.
4. The package structure of claim 1, wherein a spacing width of each of the first conductive solder balls is constant.
5. The package structure of claim 1, further comprising:
a second package module comprising:
a second chip; and
a plurality of second conductive solder balls located under the second chip;
the printed circuit board further includes:
the second pins are positioned on the second surface of the printed circuit board and are respectively and electrically connected with each second conductive welding ball; and
and the second heat insulation layer is filled in the space between the second chip and the printed circuit board, wherein the second heat insulation layer comprises the epoxy resin.
6. The package structure of claim 5, wherein the second package module comprises a ball grid array package.
7. The package structure of claim 5, wherein the printed circuit board further comprises at least one second injection hole, wherein the at least one second injection hole penetrates through the printed circuit board and leads to a portion of the second conductive solder balls adjacent to each other.
8. The package structure of claim 5, wherein the spacing width of each of the second conductive solder balls is constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010396318.1A CN113658923A (en) | 2020-05-12 | 2020-05-12 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010396318.1A CN113658923A (en) | 2020-05-12 | 2020-05-12 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113658923A true CN113658923A (en) | 2021-11-16 |
Family
ID=78488665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010396318.1A Pending CN113658923A (en) | 2020-05-12 | 2020-05-12 | Packaging structure |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767446A (en) * | 1995-10-27 | 1998-06-16 | Anam Industrial Co., Ltd. | Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package |
| TW480688B (en) * | 2001-05-28 | 2002-03-21 | Chipmos Technologies Inc | Window BGA package structure |
| US20070246814A1 (en) * | 2006-04-21 | 2007-10-25 | Powertech Technology Inc. | Ball Grid array package structure |
| CN101360394A (en) * | 2007-07-31 | 2009-02-04 | 株式会社东芝 | Printed wiring board structure and electronic apparatus |
| CN103379736A (en) * | 2012-04-13 | 2013-10-30 | 广达电脑股份有限公司 | System-in-package assembly, printed circuit board assembly and manufacturing method thereof |
| CN108834304A (en) * | 2018-07-17 | 2018-11-16 | 盛世瑶兰（深圳）科技有限公司 | A kind of printed circuit board and its method for maintaining |
-
2020
- 2020-05-12 CN CN202010396318.1A patent/CN113658923A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767446A (en) * | 1995-10-27 | 1998-06-16 | Anam Industrial Co., Ltd. | Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package |
| TW480688B (en) * | 2001-05-28 | 2002-03-21 | Chipmos Technologies Inc | Window BGA package structure |
| US20070246814A1 (en) * | 2006-04-21 | 2007-10-25 | Powertech Technology Inc. | Ball Grid array package structure |
| CN101360394A (en) * | 2007-07-31 | 2009-02-04 | 株式会社东芝 | Printed wiring board structure and electronic apparatus |
| CN103379736A (en) * | 2012-04-13 | 2013-10-30 | 广达电脑股份有限公司 | System-in-package assembly, printed circuit board assembly and manufacturing method thereof |
| CN108834304A (en) * | 2018-07-17 | 2018-11-16 | 盛世瑶兰（深圳）科技有限公司 | A kind of printed circuit board and its method for maintaining |
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