CN113658905A - 一种深硅槽中选择性外延锗方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
本发明提供了一种深硅槽中选择性外延锗方法，包括：步骤1、在硅衬底表面沉积硬掩膜，并制作深硅槽；步骤2、在深硅槽的侧壁和底部同时选择性外延生长锗；步骤3、高温退火使侧壁锗材料再分布；步骤4、重复步骤2‑3使深硅槽处外延生长锗表面高于硬掩膜；步骤5、进行化学机械抛光使锗表面与硬掩膜表面齐平；步骤6、去除硬掩膜，完成深硅槽的选择性外延锗。本发明提出的方案在硅槽侧壁和底部同时外延锗/锗硅，结合高温锗再分布技术，可以在不影响形貌的情况下，实现深硅槽中锗/锗硅外延生长；并且无需在硅与锗中间插入氧化硅层，有利于提升硅波导到锗器件的耦合效率。
Description
技术领域
本发明涉及半导体制造领域，特别涉及一种深硅槽中选择性外延锗方法。
背景技术
在硅衬底的特定区域选择性生长锗的能力有利于基于锗的光电器件与基于硅的高速光电集成电路集成。潜在的应用包括集成高性能锗光电探测器、硅光调制器和各类硅光无源器件，进而形成具有高速收发功能的光收发芯片。除了锗探测器，Ge和Ge/SiGe量子阱(QW)都表现出电吸收效应(Franz效应)，即Ge中的Keldysh效应和Ge/SiGe中的量子限制斯塔克效应(QCSE)。外加电场的增加会使吸收光谱红移，这种行为允许开发紧凑、高性能、基于Ge的用于光互连应用的硅兼容光调制器。为了最小化锗结构中，在生长中直接在SOI波导中生长Ge或Ge/SiGe量子阱，将调制区域对接耦合到输入和输出波导，可以使调制器具有小占地面积和低电容，从而实现更高的速率。
锗的选择性生长通常通过使用介电掩模，如位于硅衬底上方二氧化硅(SiO2)或氮化硅(Si3N4)掩膜。锗的生长始于暴露的硅表面。在深硅槽中外延生长锗时，生长窗口可以有非常厚的暴露硅侧壁(取决于硅槽厚度)。因为任何暴露的晶体硅表面可以作为锗的生长区域，锗会在侧壁生长，影响外延形貌与外延质量。现有技术通过在侧壁形成一层SiO2阻挡层，来避免侧壁的锗外延。然而该方法会在硅波导与锗材料间插入SiO2阻挡层，会降低光的耦合效率。
发明内容
针对现有技术中存在的问题，提供了一种深硅槽中集成锗材料的制造工艺，可以在不使用侧壁SiO2阻挡层的情况下，在厚的硅槽中，实现高质量的锗材料选择性外延。
本发明采用的技术方案如下：一种深硅槽中选择性外延锗方法，包括以下步骤：
步骤1、在硅衬底表面沉积硬掩膜，并制作深硅槽；
步骤2、在深硅槽的侧壁和底部同时选择性外延生长锗；
步骤3、高温退火使侧壁锗材料再分布；
步骤4、重复步骤2-3使深硅槽处外延生长锗表面高于硬掩膜；
步骤5、进行化学机械抛光使锗表面与硬掩膜表面齐平；
步骤6、去除硬掩膜，完成深硅槽的选择性外延锗。
进一步的，所述步骤1中，制作深硅槽具体步骤为：在沉积硬掩膜的衬底表面通过光刻定义锗窗口，并刻蚀掉锗窗口部分的硬掩膜以及硅，完成深硅槽制作。
进一步的，所述深硅槽的深度为0.50-10um。
进一步的，所述步骤1中沉积的硬掩膜厚度为500nm。
进一步的，所述步骤2中，深硅槽底部外延生长的锗厚度～1um。
进一步的，所述步骤3中，高温退火环境为氢气、氮气或氩气环境，退火温度为700-900oC。
进一步的，所述步骤5中，抛光后硬掩膜厚度<100nm。
进一步的，所述硬掩膜为氧化硅、氮化硅或氧化硅与氮化硅多层膜组合中的一种。
进一步的，所述锗为纯锗或锗硅。
与现有技术相比，采用上述技术方案的有益效果为：
1.本发明在硅槽侧壁和底部同时外延锗/锗硅，结合高温锗再分布技术，可以在不影响形貌的情况下，实现深硅槽中锗/锗硅外延生长；
2.无需在硅与锗中间插入氧化硅层，有利于提升硅波导到锗器件的耦合效率。
附图说明
图1是为本发明提出的深硅槽中选择性外延锗的流程图。
图2是为一实施例的深硅槽中选择性外延锗具体示意图。
具体实施方式
下面结合附图对本发明做进一步描述。
在深硅槽中外延生长锗时，生长窗口有非常厚的暴露硅侧壁(取决于硅槽厚度)。因为任何暴露的晶体硅表面可以作为锗的生长区域，锗会在侧壁生长，影响外延形貌与外延质量。现有技术通过在侧壁形成一层SiO2阻挡层，来避免侧壁的锗外延。然而该方法会在硅波导与锗材料间插入SiO2阻挡层，会降低光的耦合效率。为了解决上述问题，提出了本方案，具体如下：
如图1、图2(a)-图2(h)所示，本实施例提出了一种深硅槽中选择性外延锗方法，包括：
步骤1、在硅衬底表面沉积硬掩膜，并制作深硅槽；
步骤2、在深硅槽的侧壁和底部同时选择性外延生长锗；
步骤3、高温退火使侧壁锗材料再分布；
步骤4、重复步骤2-3使深硅槽处外延生长锗表面高于硬掩膜；
步骤5、进行化学机械抛光使锗表面与硬掩膜表面齐平；
步骤6、去除硬掩膜，完成深硅槽的选择性外延锗。
具体的，所述步骤1中，制作深硅槽具体步骤为：在沉积硬掩膜的衬底表面通过光刻定义锗窗口，并刻蚀掉锗窗口部分的硬掩膜以及硅，完成深硅槽制作。在本实施例中，深硅槽的深度为0.50-10um。
在一个优选实施例中，步骤1中沉积的硬掩膜厚度为500nm。
在一个优选实施例中，所述步骤2中，深硅槽底部外延生长的锗厚度～1um。
在一个优选实施例中，所述步骤3中，高温退火环境为氢气、氮气或氩气环境，退火温度为700-900oC。
在一个优选实施例中，所述步骤5中，抛光后硬掩膜厚度<100nm。
在一个优选实施例中，所述硬掩膜为氧化硅、氮化硅或氧化硅与氮化硅多层膜组合中的一种。优选为氧化硅。
在一个优选实施例中，所述锗为纯锗或锗硅。
本发明相较于现有方法的有益效果为：
1.在硅槽侧壁和底部同时外延锗/锗硅，结合高温锗再分布技术，可以在不影响形貌的情况下，实现深硅槽中锗/锗硅外延生长；
2.无需在Si与Ge中间插入SiO2层，有利于提升Si波导到Ge器件的耦合效率。
本发明并不局限于前述的具体实施方式。本发明扩展到任何在本说明书中披露的新特征或任何新的组合，以及披露的任一新的方法或过程的步骤或任何新的组合。如果本领域技术人员，在不脱离本发明的精神所做的非实质性改变或改进，都应该属于本发明权利要求保护的范围。
本说明书中公开的所有特征，或公开的所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以以任何方式组合。
本说明书中公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换。即，除非特别叙述，每个特征只是一系列等效或类似特征中的一个例子而已。
Claims (9)
1.一种深硅槽中选择性外延锗方法，其特征在于，包括以下步骤：
步骤1、在硅衬底表面沉积硬掩膜，并制作深硅槽；
步骤2、在深硅槽的侧壁和底部同时选择性外延生长锗；
步骤3、高温退火使侧壁锗材料再分布；
步骤4、重复步骤2-3使深硅槽处外延生长锗表面高于硬掩膜；
步骤5、进行化学机械抛光使锗表面与硬掩膜表面齐平；
步骤6、去除硬掩膜，完成深硅槽的选择性外延锗。
2.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述步骤1中制作深硅槽具体步骤为：在沉积硬掩膜的衬底表面通过光刻定义锗窗口，并刻蚀掉锗窗口部分的硬掩膜以及硅，完成深硅槽制作。
3.根据权利要求2所述的深硅槽中选择性外延锗方法，其特征在于，所述深硅槽的深度为0.50-10um。
4.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述步骤1中沉积的硬掩膜厚度为500nm。
5.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述步骤2中底部锗厚度～1um。
6.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述步骤3中高温退火环境为氢气、氮气或氩气环境，退火温度为700-900oC。
7.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述步骤5中，抛光后硬掩膜厚度<100nm。
8.根据权利要求1或2所述的深硅槽中选择性外延锗方法，其特征在于，所述硬掩膜为氧化硅、氮化硅或氧化硅与氮化硅多层膜组合中的一种。
9.根据权利要求1所述的深硅槽中选择性外延锗方法，其特征在于，所述锗为纯锗或锗硅。
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| CN105261550A (zh) * | 2014-07-18 | 2016-01-20 | 中国科学院微电子研究所 | 一种锗的化学机械抛光方法 |
| CN111816733A (zh) * | 2020-07-28 | 2020-10-23 | 中国电子科技集团公司第四十四研究所 | 波导锗探测器制作工艺中选择性锗外延的前处理方法 |
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2021
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7354826B1 (en) * | 2005-04-22 | 2008-04-08 | Spansion Llc | Method for forming memory array bitlines comprising epitaxially grown silicon and related structure |
| US20100006961A1 (en) * | 2008-07-09 | 2010-01-14 | Analog Devices, Inc. | Recessed Germanium (Ge) Diode |
| CN105261550A (zh) * | 2014-07-18 | 2016-01-20 | 中国科学院微电子研究所 | 一种锗的化学机械抛光方法 |
| CN111816733A (zh) * | 2020-07-28 | 2020-10-23 | 中国电子科技集团公司第四十四研究所 | 波导锗探测器制作工艺中选择性锗外延的前处理方法 |
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