CN113658537A - Display and driving method thereof - Google Patents
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- CN113658537A CN113658537A CN202110947326.5A CN202110947326A CN113658537A CN 113658537 A CN113658537 A CN 113658537A CN 202110947326 A CN202110947326 A CN 202110947326A CN 113658537 A CN113658537 A CN 113658537A
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- 230000003068 static effect Effects 0.000 claims abstract description 77
- 239000003990 capacitor Substances 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 10
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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Abstract
The application discloses a display and a driving method thereof. In the read-write stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage; and in the non-read-write stage of the static storage array, the power supply controller is switched to a second power supply mode, and the power supply generator outputs a second working voltage, wherein the second working voltage is less than the first working voltage and greater than the minimum voltage required by the static storage array for storing data. Based on this, this application can reduce SRAM's power consumption.
Description
Technical Field
The application relates to the field of static storage, in particular to a display and a driving method thereof.
Background
An SRAM (Static Random-Access Memory) is one of the indispensable important components in an electronic system. The SRAM is used for temporarily storing data or instructions, and has the advantages of high speed, low power consumption, easy embedded integration, and the like, and thus is a preferred device for caching in a Central Processing Unit (CPU). In modern high-performance processors, the area of a chip occupied by the SRAM is becoming larger and larger, and in the coming years, with the explosive growth of mobile internet, internet of things and wearable electronic devices, the power consumption of the chip will be subject to strict requirements and severe challenges, and the SRAM is the first to rush. Therefore, how to reduce the power consumption of the SRAM is an urgent problem to be solved in the field of static storage.
Disclosure of Invention
In view of the above, the present application provides a display and a driving method thereof to solve the problem of large power consumption of the SRAM.
The application provides a display, which comprises a power supply generator, a static storage array and a power supply controller connected between the power supply generator and the static storage array,
in the read-write stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage;
and in the non-read-write stage of the static storage array, the power supply controller is switched to a second power supply mode, the power supply generator outputs a second working voltage, and the second working voltage is smaller than the first working voltage and larger than the minimum voltage required by the static storage array for storing data.
Optionally, the non-read-write stage includes a stage in which the display is in one of a rest mode, a standby mode, and a sleep mode.
Optionally, the static memory array comprises a first sub-memory area and at least one second sub-memory area, and the word line of the first sub-memory area is connected with the power controller;
the display also comprises at least one switching device, each switching device is arranged between the power supply controller and each second sub storage area, a word line of each second sub storage area is connected with one switching device, and the switching devices are used for controllably turning on the power supply generator and the second sub storage areas;
the switching device is a transistor, a control end of the transistor receives the control signal and is conducted, an input end of the transistor is connected with the power supply controller, and an output end of the transistor is connected with the second sub storage area.
Optionally, the control terminal of the switching device is connected to the power generator and receives the control signal.
Optionally, each static memory cell of the static memory array is connected to two bit lines, the display further includes a voltage boost circuit, a first switch and a second switch, each switch is connected between the voltage boost circuit and each bit line, and the voltage boost circuit is connected to the control end of the switching device.
Optionally, the boost circuit includes a third switch and a capacitor, the first electrode of the capacitor is connected to the two bit lines through the first switch and the second switch, the third switch is connected between the first electrode of the capacitor and the control terminal of the switching device, and the second electrode of the capacitor is grounded.
Optionally, each static memory cell of the static memory array is connected to two bit lines, the display further includes a voltage boost circuit, a first switch and a second switch, the first switch and the second switch are respectively connected between the voltage boost circuit and each bit line, and the voltage boost circuit is connected to the input terminal of the switching device.
Optionally, the boost circuit includes a third switch and a capacitor, the first electrode of the capacitor is connected to the two bit lines through the first switch and the second switch, the third switch is connected between the first electrode of the capacitor and the input terminal of the switching device, and the second electrode of the capacitor is grounded.
Optionally, the sum of the third voltage output by the voltage boost circuit and the second working voltage generated by the power generator is equal to the first working voltage;
or, in the breath screen mode, the ratio of the sum of the third voltage and the second working voltage to the first working voltage is between 90% and 100%; in the standby mode or the sleep mode, the ratio of the sum of the third voltage and the second working voltage to the first working voltage is 70-100%.
The application provides a driving method of a display, based on the display of any one of the preceding claims, the method includes:
in the read-write stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage;
when the static storage array enters a non-read-write stage, the power supply controller is switched to a second power supply mode, the power supply generator outputs a second working voltage, and the second working voltage is smaller than the first working voltage and larger than the minimum voltage required by the static storage array for storing data.
Based on the display and the driving method thereof, in the reading and writing stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage; in the non-read-write stage of the static storage array, the power supply controller is switched to a second power supply mode, the power supply generator outputs a second working voltage, the second working voltage is smaller than the first working voltage and larger than the minimum voltage required by the static storage array for storing data, according to the stage where the display is located, the working voltages of the static storage array in different stages are adaptively adjusted, normal read-write of image data is guaranteed, power consumption can be reduced, and the duration is prolonged in the situation that the display is suitable for wearable equipment such as a mobile phone or a smart watch.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a memory circuit of a display according to an embodiment of the present application;
FIG. 2 is a schematic view of an interface of a display of the present application in a breath screen mode;
FIG. 3 is an equivalent schematic diagram of a memory circuit of the display shown in FIG. 1;
FIG. 4 is an equivalent schematic diagram of another memory circuit of the display shown in FIG. 1;
FIG. 5 is an equivalent schematic diagram of the boost circuit of the present application coupled to a static memory cell;
FIG. 6 is a schematic diagram of a memory circuit of a display according to another embodiment of the present application;
FIG. 7 is an equivalent schematic diagram of a memory circuit of the display shown in FIG. 6;
FIG. 8 is a timing diagram of the display of the present application receiving an operating voltage;
fig. 9 is a flowchart illustrating a driving method of a display according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the following description of the present application will clearly and completely describe the technical solutions of the present application with reference to the specific embodiments and the accompanying drawings. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the application. Based on the following description, the various embodiments and their technical features may be combined with each other without conflict.
The conventional SRAM includes a plurality of static memory cells, the start of the static memory cells is controlled by word lines, stored information (e.g., image data) is communicated with the outside through bit lines, in a screen mode, a part of a panel area of a display needs to display various information such as time, date, battery status, notification, etc., at this time, the word lines receive operating voltage and become high level, all the static memory cells connected to the word lines enter a read-write phase, the static memory cells selected by the bit lines perform normal read or write operations (hereinafter, collectively referred to as read-write operations), the static memory cells not selected perform false read or write operations, and the false read or write operations, although the false read or write operations do not read or write data, still receive the operating voltage as the normal read or write operations, and generate power consumption.
In view of the above, the present application provides a static memory array and a display having the same, which can reduce the power consumption of an SRAM in a touchscreen mode.
Referring to fig. 1, the memory circuit of the display includes a power generator 11, a static memory array 12, and at least one switching device 13.
The power generator 11, also called a Memory power generator (Memory power generator), is used for generating a voltage required by the static Memory array 12 to implement image data or other instruction storage, i.e. an operating voltage VDDM. The power generator 11 may be connected to the power supply of the display and convert the power drawn from the power supply to a voltage suitable for the static memory array 12.
The first sub-storage area 121 can store information that the display needs to display in the breath screen mode, including but not limited to various information such as time, date, battery status, notification, etc. as shown in fig. 2, and the first sub-storage area 121 is always connected to the power generator 11 without being powered off, so that the stored information is not lost, and the display can be called and displayed quickly.
Optionally, a display interface of the display may be divided into a first panel area and a second panel area, the first panel area is used for displaying an image in a non-read-write stage, and the first sub-storage area is used for storing image data of the first panel area in the non-read-write stage and the read-write stage; the second sub-storage area is used for storing the image data of the second panel area in a non-read-write stage and a read-write stage.
That is, there is a corresponding relationship between each sub-storage area of the static storage array 12 and the panel area of the display, the first sub-storage area 121 has a corresponding relationship with the panel area (e.g., the panel area shown by the dotted line in fig. 2) of the information that needs to be displayed in the non-read-write phase (e.g., the screen-rest mode), and all the second sub-storage areas 122 have a corresponding relationship with the remaining panel areas. When the display is switched from, for example, the breath screen mode to the normal unlock display mode, the first sub-storage area 121 is only used for reading and writing the image data of the corresponding panel area, and the image data of the remaining panel areas are read and written by the corresponding second sub-storage area 122.
A switching device 13 is disposed between each second sub-storage area 122 and the power generator 11, controllably turns on the power generator 11 and the second sub-storage area 122, and transmits the operating voltage generated by the power generator 11 to the second sub-storage area 122 when turned on.
The second sub-memory area 122 is used to store image data of other panel areas (i.e., areas of the display other than the panel area where information needs to be displayed in the breath-screen mode). In the breath screen mode, the switching device 13 is turned off, the second sub-storage areas 122 are powered off, as shown in fig. 3, all word lines 12b in any one of the second sub-storage areas 122 do not receive the working voltage, all static storage units 12a in the second sub-storage area 122 do not perform the false read-write operation, power consumption is not generated, and power consumption of the static storage array 12 is reduced as a whole.
In view of the small amount of image data that needs to be read and written in the message screen mode, the display may set the capacity of the first sub storage area 121 to be smaller than the sum of the capacities of all the second sub storage areas 122, for example, the ratio of the capacity of the first sub storage area 121 to the capacity of all the second sub storage areas 122 is 1/3, that is, the capacity of the first sub storage area 121 occupies 25% of the SRAM capacity.
It should be understood that the present embodiment may divide the capacity ratio of the first sub-storage area 121 to all the second sub-storage areas 122 according to actual needs, and is not limited herein.
In one implementation, referring to fig. 1 and 3, the static memory array 12 includes a plurality of static memory cells 12a arranged in an array. These static memory units 12a can be divided into the aforementioned first sub memory area 121 and several second sub memory areas 122. It should be understood that the number of static memory cells 12a included in each sub-memory area is not a limitation of the present application. For example, an equal number of static memory cells 12a may be provided in the first sub memory area 121 and any one of the second sub memory areas 122; for another example, the same or different number of static memory cells 12a are disposed in each second sub-storage area 122, and the illustration in fig. 3 is only an exemplary illustration.
In the first sub-memory area 121, the word lines 12b of all the static memory cells 12a are connected to the power supply generator 11. In each second sub-memory area 122, the word lines 12b of all the static memory cells 12a are connected to a corresponding one of the switching devices 13.
Alternatively, the switching device 13 is a transistor, and has a control terminal g receiving the control signal EN and conducting, an input terminal s connected to the power generator 11 and receiving the operating voltage VDDM, and an output terminal d connected to the word line 12b of the second sub-storage area 122.
In an application scenario, the switching device 13 may be a P-type MOS transistor, and the control terminal g, the input terminal s, and the output terminal d are a gate, a source, and a drain, respectively.
In one implementation, as shown in fig. 4, the control terminal g of the switching device 13 may be connected to the power generator 11 and receive the control signal EN. At this time, the control signal EN is the working voltage VDDM applied to the second sub-storage area 122 by the power generator 11, and the power generator 11 outputs the working voltage VDDM to each second sub-storage area 122 through two different lines, preferably, the two lines can output the working voltage VDDM at the same time, so as to reduce the requirement on the output timing, and the display may not need to be provided with a timing controller for implementing the transmission.
In another implementation, the control terminal g of the switching device 13 can receive the control signal EN from the bit line of the static memory array 12 based on the fact that the control signal EN is substantially a high signal, as shown in fig. 5, and the display further includes the voltage boost circuit 20.
The booster circuit 20 is connected to the bit line of the static memory cell 12 a. As shown in FIG. 5, each static memory cell 12a includes a bit line 12c1 and a bit line 12c2 connected to two inverters H1 and H2 in parallel through transistors M1 and M2, respectively.
The voltage boost circuit 20 is connected to the bit line 12c1 and the bit line 12c2 through a first switch SW1 and a second switch SW2, respectively, for recovering charges drained by the bit line and applying the recovered charges to the control terminal g of the switching device 13. The connection point of the booster circuit 20, the first switch SW1, and the second switch SW2 is a node Q. Optionally, the boost circuit 20 includes a capacitor C1 and a third switch SW 3. The capacitor C1 has a first electrode connected to the node Q and a second electrode connected to ground. One end of the third switch SW3 is connected to the node Q and the first electrode of the capacitor C1, and the other end is connected to the control terminal g of the switching device 13.
In the read/write phase of the static memory cell 12a, one of the first switch SW1 and the second switch SW2 is turned on, the third switch SW3 is turned off, the capacitor C1 is connected in parallel with one of the bit lines, and the charge of the bit line is stored in the capacitor C1; then, the first switch SW1 and the second switch SW2 are both turned off, the third switch SW3 is turned on, and the capacitor C1 outputs a high level signal, which can be used as the control signal EN, and is applied to the control terminal g of the switching device 13.
Based on the boosting principle of the boosting circuit 20, in an implementation, the boosting circuit 20 may be connected to the power generator 11, or applied to each sub-storage region (for example, the boosting circuit 20 of each sub-storage region is connected to the input terminal s of the switching device 13), so as to assist the power generator 11, which is beneficial to reducing the working voltage generated by the power generator 11 and reducing the power consumption.
When the display is in the non-read-write stage, all word lines 12b in the first sub-storage area 121 continuously receive the working voltage VDDM generated by the power generator 11, all static storage units 12a will enter the read-write stage, the static storage unit 12a with the selected bit line performs normal read or write operations including information to be displayed in the display mode, but at this time, the display does not input the control signal EN to the control terminal g of any switching device 13, all switching devices 13 are turned off, all second sub-storage areas 122 are powered off, false read or normal read or write operations cannot be performed, and power consumption cannot be generated. Optionally, the non-read-write stage includes a stage in which the display is in any one of a screen rest mode, a standby mode, and a sleep mode.
It should be understood that all the static storage units 12a in the first sub-storage area 121 are not all used for storing information in the non-read-write phase, for example, not all used for storing image data in the information screen mode, but only a part of the static storage units 12a may perform this storage, and the rest of the static storage units 12a may serve as redundant storage space for assisting the second sub-storage area 122 to store other information when the display is switched to the read-write phase.
When the display is in a read-write stage, according to the size of data to be stored, the display selects the second sub-storage area 122 with the adaptive capacity, transmits a control signal EN to the control end g of the switching device 13 connected with the selected second sub-storage area 122, only the switching devices 13 are conducted, the selected second sub-storage area 122 receives the working voltage VDDM, normal read-write operation is executed, and the rest second sub-storage areas 122 do not generate power consumption.
In contrast to conventional SRAM structures, in the embodiment depicted in fig. 3 and 4, static memory array 12 changes the word line connection design of static memory cells 12a in each sub-memory block, while static memory array 12 is identical to the bit line connection design of conventional SRAMs.
Fig. 6 is a schematic diagram of a memory circuit of a display according to another embodiment of the present application, and fig. 7 is an equivalent schematic diagram of the memory circuit of the display shown in fig. 6. For ease of description, like reference numerals are used herein to identify like-named elements. On the basis of the description of the foregoing embodiments, except that the display of the present embodiment further includes a Power controller (Power controller) 14.
The power controller 14 is connected to the power generator 11, the first sub-bank 121 is connected to the power generator 11 through the power controller 14, and each switching device 13 is disposed between the power controller 14 and each second sub-bank 122 for controllably turning on or off a conductive path between the power controller 14 and the second sub-bank 122.
The power controller 14 is equivalent to a controller in a power supply mode, and is used for controlling each sub-storage region to perform read and write operations in different voltage modes.
In one implementation, shown in connection with fig. 8 and 9, the following:
s1: during the read/write phase of the static memory array 12, the power controller 14 switches to a first power supply mode in which the power generator 11 outputs a first operating voltage.
S2: in the non-read/write phase of the static memory array 12, the power controller 14 switches to a second power supply mode, in which the power generator 11 outputs a second working voltage. The second operating voltage is smaller than the first operating voltage and larger than the minimum voltage required by any sub-storage area to perform data storage, that is, in the non-read/write stage, the operating voltage VDDM of the static storage array 12 is lowered to keep each sub-storage area capable of performing normal read/write operations.
For example, in the breath-screen mode, the second operating voltage is greater than or equal to the minimum voltage required by any static memory cell 12a in the first sub-storage area 121 to perform normal read/write operations. At this time, since the switching devices 13 are all turned off, the second sub-storage area 122 does not perform the read/write operation, and thus the minimum voltage required for the static memory cells 12a in the second sub-storage area 122 to perform the normal read/write operation may not be considered when setting the value of the second operating voltage.
In the breath-screen mode, the ratio of the second operating voltage to the first operating voltage may be between 90% and 100%. In the standby mode or sleep mode scenario, the ratio of the second operating voltage to the first operating voltage may be between 70% and 100%.
In a scenario where the display is provided with the booster circuit 20 shown in fig. 5, the booster circuit 20 of each sub-storage region may be connected to the input terminal s of the switching device 13, where the second operating voltage generated by the power supply generator 11 may be further reduced in the non-read-write phase. The sum of the third voltage output by the boost circuit 20 and the second operating voltage generated by the power generator 11 may be equal to the first operating voltage, or the ratio of the sum of the third voltage and the second operating voltage to the first operating voltage may be between 90% and 100% (or 70% and 100%).
As shown in the lower diagram of fig. 8, the operating voltage VDDM received by the conventional SRAM in the non-read/write phase and the read/write phase is the same, i.e., the operating voltage VDDM of the conventional SRAM is always unchanged and is not changed by whether data is written or not. According to the embodiment of the application, the working voltage VDDM of the static storage array 12 at different stages is adaptively adjusted according to the stage of the display, so that normal display of information is ensured, and power consumption can be reduced. For example, in a scenario where the display is suitable for a wearable device such as a mobile phone or a smart watch, the duration can be prolonged.
The above description is only a part of the embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings are included in the scope of the present application.
Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element, and that elements, features, or elements having the same designation in different embodiments may or may not have the same meaning as that of the other elements, and that the particular meaning will be determined by its interpretation in the particular embodiment or by its context in further embodiments.
In addition, although the terms "first, second, third, etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive or meaning any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
Claims (10)
1. A display device comprising a power generator, a static memory array, and a power controller connected between the power generator and the static memory array,
in the read-write stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage;
and in the non-read-write stage of the static storage array, the power supply controller is switched to a second power supply mode, the power supply generator outputs a second working voltage, and the second working voltage is smaller than the first working voltage and larger than the minimum voltage required by the static storage array for storing data.
2. The display of claim 1, wherein the non-read-write phase comprises a phase in which the display is in one of a rest mode, a standby mode, and a sleep mode.
3. The display of claim 1,
the static storage array comprises a first sub storage area and at least one second sub storage area, and a word line of the first sub storage area is connected with the power supply controller;
the display also comprises at least one switching device, each switching device is arranged between the power supply controller and each second sub storage area, a word line of each second sub storage area is connected with one switching device, and the switching devices are used for controllably conducting the power supply generator and the second sub storage areas;
the switching device is a transistor, a control end of the transistor receives a control signal and is conducted, an input end of the transistor is connected with the power supply controller, and an output end of the transistor is connected with the second sub storage area.
4. The display of claim 3, wherein the control terminal of the switching device is connected to the power generator to receive the control signal.
5. The display of claim 3, wherein each static memory cell of the static memory array is connected to two bit lines,
the display further comprises a booster circuit, a first switch and a second switch, wherein the first switch and the second switch are respectively connected between the booster circuit and each bit line, and the booster circuit is connected with the control end of the switching device.
6. The display of claim 5, wherein the boost circuit comprises a third switch and a capacitor, the first electrode of the capacitor is connected to the two bit lines through the first switch and the second switch, respectively, the third switch is connected between the first electrode of the capacitor and the control terminal of the switching device, and the second electrode of the capacitor is connected to ground.
7. The display of claim 3, wherein each static memory cell of the static memory array is connected to two bit lines,
the display also comprises a booster circuit, a first switch and a second switch, wherein the first switch and the second switch are respectively connected between the booster circuit and each bit line, and the booster circuit is connected with the input end of the switching device.
8. The display of claim 7, wherein the boost circuit comprises a third switch and a capacitor, the first electrode of the capacitor is connected to the two bit lines through the first switch and the second switch, respectively, the third switch is connected between the first electrode of the capacitor and the input terminal of the switching device, and the second electrode of the capacitor is connected to ground.
9. The display of claim 7,
the sum of a third voltage output by the booster circuit and a second working voltage generated by the power supply generator is equal to the first working voltage;
or, in the breath screen mode, the ratio of the sum of the third voltage and the second working voltage to the first working voltage is between 90% and 100%; in the standby mode or the sleep mode, the ratio of the sum of the third voltage and the second working voltage to the first working voltage is 70-100%.
10. A method for driving a display, the method being based on the display of any one of claims 1 to 9, the method comprising:
in the read-write stage of the static storage array, the power supply controller is switched to a first power supply mode, and the power supply generator outputs a first working voltage;
when the static storage array enters a non-read-write stage, the power supply controller is switched to a second power supply mode, the power supply generator outputs a second working voltage, and the second working voltage is smaller than the first working voltage and larger than the minimum voltage required by the static storage array for storing data.
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