CN113655306A - Analog-digital converter testing method - Google Patents
Analog-digital converter testing method Download PDFInfo
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- CN113655306A CN113655306A CN202110831313.1A CN202110831313A CN113655306A CN 113655306 A CN113655306 A CN 113655306A CN 202110831313 A CN202110831313 A CN 202110831313A CN 113655306 A CN113655306 A CN 113655306A
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- 238000012545 processing Methods 0.000 abstract description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/28—Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response
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Abstract
The invention discloses a method for testing an analog-digital converter, which is characterized by comprising the following steps of: step S1: selecting an analog-digital converter and a test system to be tested; step S2: inputting a signal, generating amplitude by an analog signal source, and equally dividing each least significant bit of the analog-digital converter. The invention utilizes the universality test platform, fully utilizes the prior art to realize the test operation of the analog-digital converter, is convenient for collecting and analyzing the test data of the analog-digital converter and leads the test to be convenient; the test data of the analog-digital converter is analyzed, so that the quantization processing operation of the test result of the analog-digital converter can be realized, and the quality of the analog-digital converter can be conveniently and accurately tested. The invention has the advantages of convenient test and realization of test result quantification.
Description
Technical Field
The invention relates to the technical field of analog-digital converters, in particular to a test method of an analog-digital converter.
Background
An analog-to-digital converter is a converter for converting an analog quantity after comparison with a standard quantity (or a reference quantity) into a discrete signal represented by a binary number, which is referred to as an ADC or an a/D converter for short. The analog-to-digital conversion process includes quantization to divide the range of the analog signal into a number of discrete magnitudes and determine the magnitude to which the input signal belongs, and encoding to assign a unique digital code to each magnitude and determine the code corresponding to the input signal. The analog-digital converter in the prior art is widely used, so that the test of the analog-digital converter is necessary.
In the prior art, the test operation of the analog-digital converter is very inconvenient, errors are very easily caused, and the analog-digital converter cannot be well embodied and processed in a quantization mode, so that the test operation of the analog-digital converter cannot be well performed. For the above reasons, the present invention provides an analog-to-digital converter testing method to solve the deficiencies of the prior art.
Disclosure of Invention
The invention provides a method for testing an analog-digital converter, which aims to overcome the defects of inconvenience in testing and poor effect in the prior art. The testing method of the analog-digital converter has the characteristics of convenience in testing, realization of quantification of a testing result and the like.
In order to achieve the purpose, the invention provides the following technical scheme: an analog-to-digital converter testing method, comprising the steps of:
step S1: selecting an analog-digital converter and a test system to be tested;
step S2: inputting a signal, wherein an analog signal source generates amplitude, and each least significant bit of an analog-digital converter is equally divided;
step S3: collecting data of the analog-digital converter through a test system;
step S4: carrying out differential non-linearity analysis on the collected test data to obtain a numerical point of each least significant bit of the analog-digital converter;
step S5: analyzing the whole nonlinearity of the analog-digital converter according to the obtained numerical point of each least significant bit of the analog-digital converter to obtain a corresponding analog value on the numerical point of each least significant bit of the analog-digital converter;
step S6: carrying out offset error analysis on the obtained analog value;
step S7: and performing gain error analysis on the analog-digital converter through the obtained detuning error value, and finally obtaining the performance of the analog-digital converter through the analysis of the gain error value.
As a further aspect of the present invention, the analog-to-digital converter in step S1 is a 12-bit TLC2543 analog-to-digital converter, and the test system is a J750 large-scale digital-to-analog hybrid test system platform.
As a further aspect of the present invention, in step S2, the analog signal source is programmed to generate an analog ramp signal with an amplitude equal to the full capacity of the analog-to-digital converter, and each least significant bit of the analog-to-digital converter is divided by N, where N is a non-negative integer and N > 0.
As a further aspect of the present invention, in step S3, ideal code width data of each least significant bit of the analog-to-digital converter is collected.
As a further aspect of the present invention, in the middle difference nonlinearity analysis of step S4, the following formula is used:
middle Differential Nonlinearity (DNL) ═ actual code width-ideal code width/1 LSB
Calculating a numerical point of each least significant bit of the analog-digital converter; where LSB is the quantity represented by the least significant bit of the analog-to-digital converter.
As a further aspect of the present invention, in the overall non-linearity analysis in step S5, the following formula is used:
overall non-linearity (INL) ═ DNL [ i ] + DNL [ i-1 ] + … … + DNL [ 0 ] } ∑ DNL [ i ]
Calculating the corresponding analog value of each least significant bit of the analog-digital converter; wherein DNL is the middle differential nonlinearity, i is the least significant bit group number, i is a nonnegative integer, and i is greater than or equal to 1.
As a further aspect of the present invention, the method for calculating the misalignment error in step S6 includes: the ideal 0 code input analog value is subtracted from the actual input analog value at the first least significant bit output of the analog-to-digital converter minus the 1/2 Least Significant Bit (LSB) values.
As a further aspect of the present invention, the step of analyzing the gain error in step S7 is as follows:
a. correcting the offset error of the transmission function to 0;
and b.2002, subtracting the voltage value at the actual gain point from the voltage value at the ideal gain point on the transmission function of the analog-digital converter to obtain the gain error.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention utilizes the universality test platform, fully utilizes the prior art to realize the test operation of the analog-digital converter, is convenient for collecting and analyzing the test data of the analog-digital converter and leads the test to be convenient.
2. The test data of the analog-digital converter is analyzed, so that the quantization processing operation of the test result of the analog-digital converter can be realized, and the quality of the analog-digital converter can be conveniently and accurately tested.
Drawings
FIG. 1 is a flow chart of the test of the present invention;
FIG. 2 is a diagram of an analog acquisition point corresponding to a digital output code of the present invention;
FIG. 3 is a schematic diagram of the differential nonlinearity analysis test of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-3, the present invention provides a technical solution: an analog-to-digital converter testing method, comprising the steps of:
step S1: and selecting the tested analog-digital converter and the test system. The analog-digital converter in the step is a 12-bit TLC2543 analog-digital converter, and the test system is a J750 large-scale digital-analog hybrid test system platform.
Step S2: the input of the signal, the analog signal source generates the amplitude, and equally divides each least significant bit of the analog-to-digital converter. Specifically, in this step, the analog signal source is programmed to generate an analog ramp signal with an amplitude equal to the full amplitude of the analog-to-digital converter, and each least significant bit of the analog-to-digital converter is divided by N, where N is a non-negative integer and N > 0.
Step S3: data of the analog-to-digital converter is collected by the test system. As shown in fig. 3, the ideal code width data for each least significant bit of the analog-to-digital converter is collected in this step.
Step S4: and carrying out differential non-linearity analysis on the collected test data to obtain a numerical point of each least significant bit of the analog-digital converter. In the middle difference non-linearity analysis of the step, the following formula is used:
middle Differential Nonlinearity (DNL) ═ actual code width-ideal code width/1 LSB
Calculating a numerical point of each least significant bit of the analog-digital converter; where LSB is the quantity represented by the least significant bit of the analog-to-digital converter. As shown in fig. 3, in practical tests, if the DNL value is greater than 1, the ADC cannot be guaranteed to be even monotonic, the input voltage increases, and the point value at a certain least significant bit decreases.
Step S5: and analyzing the whole nonlinearity of the analog-digital converter according to the obtained numerical point of each least significant bit of the analog-digital converter to obtain a corresponding analog value on the numerical point of each least significant bit of the analog-digital converter. In the overall nonlinear degree analysis in the step, the following formula is used:
overall non-linearity (INL) ═ DNL [ i ] + DNL [ i-1 ] + … … + DNL [ 0 ] } ∑ DNL [ i ]
Calculating the corresponding analog value of each least significant bit of the analog-digital converter; wherein DNL is the middle differential nonlinearity, i is the least significant bit group number, i is a nonnegative integer, and i is greater than or equal to 1. In the test, INL represents the corresponding analog value of the adc at all the numerical points, and the error value of the point with the largest error between the real values. That is, the output value deviates from the linear maximum distance.
Step S6: and carrying out offset error analysis on the obtained analog value. The method for calculating the misadjustment error in the step comprises the following steps: the ideal 0 code input analog value is subtracted from the actual input analog value at the first least significant bit output of the analog-to-digital converter minus the 1/2 Least Significant Bit (LSB) values.
Step S7: and performing gain error analysis on the analog-digital converter through the obtained detuning error value, and finally obtaining the performance of the analog-digital converter through the analysis of the gain error value. Specifically, the analysis steps of the gain error in this step are as follows:
a. correcting the offset error of the transmission function to 0;
and b.2002, subtracting the voltage value at the actual gain point from the voltage value at the ideal gain point on the transmission function of the analog-digital converter to obtain the gain error.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
As described above, the present invention can be preferably realized.
Claims (8)
1. A method for testing an analog-to-digital converter is characterized by comprising the following steps:
step S1: selecting an analog-digital converter and a test system to be tested;
step S2: inputting a signal, wherein an analog signal source generates amplitude, and each least significant bit of an analog-digital converter is equally divided;
step S3: collecting data of the analog-digital converter through a test system;
step S4: carrying out differential non-linearity analysis on the collected test data to obtain a numerical point of each least significant bit of the analog-digital converter;
step S5: analyzing the whole nonlinearity of the analog-digital converter according to the obtained numerical point of each least significant bit of the analog-digital converter to obtain a corresponding analog value on the numerical point of each least significant bit of the analog-digital converter;
step S6: carrying out offset error analysis on the obtained analog value;
step S7: and performing gain error analysis on the analog-digital converter through the obtained detuning error value, and finally obtaining the performance of the analog-digital converter through the analysis of the gain error value.
2. The method of claim 1, wherein the method further comprises: the analog-to-digital converter in the step S1 is a 12-bit TLC2543 analog-to-digital converter, and the test system is a J750 large digital-to-analog hybrid test system platform.
3. The method of claim 2, wherein the step of testing the analog-to-digital converter comprises the steps of: in step S2, the programmed analog signal source generates an analog ramp signal with a full amplitude of the analog-to-digital converter, and divides each least significant bit of the analog-to-digital converter by N equal parts, where N is a non-negative integer and N > 0.
4. A method for testing an analog to digital converter as claimed in claim 3, characterized in that: the ideal code width data of each least significant bit of the analog-to-digital converter is collected in the step S3.
5. The method of claim 4, wherein the step of testing the analog-to-digital converter comprises the steps of: in the middle difference nonlinearity analysis of step S4, the following formula is used:
middle Differential Nonlinearity (DNL) ═ actual code width-ideal code width/1 LSB
Calculating a numerical point of each least significant bit of the analog-digital converter; where LSB is the quantity represented by the least significant bit of the analog-to-digital converter.
6. The method of claim 5, wherein the step of testing the analog-to-digital converter comprises the steps of: in the overall non-linearity analysis in step S5, the following formula is used:
overall non-linearity (INL) ═ DNL [ i ] + DNL [ i-1 ] + … … + DNL [ 0 ] } ∑ DNL [ i ]
Calculating the corresponding analog value of each least significant bit of the analog-digital converter; wherein DNL is the middle differential nonlinearity, i is the least significant bit group number, i is a nonnegative integer, and i is greater than or equal to 1.
7. The method of claim 6, wherein the step of testing the analog-to-digital converter comprises the steps of: the method for calculating the misalignment error in step S6 includes: the ideal 0 code input analog value is subtracted from the actual input analog value at the first least significant bit output of the analog-to-digital converter minus the 1/2 Least Significant Bit (LSB) values.
8. The method of claim 7, wherein the step of testing the analog-to-digital converter comprises the steps of: the analysis steps of the gain error in step S7 are as follows:
a. correcting the offset error of the transmission function to 0;
b. the gain error is obtained by subtracting the voltage value at the actual gain point from the voltage value at the ideal gain point on the transfer function of the analog-to-digital converter.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638263A (en) * | 2012-04-24 | 2012-08-15 | 上海宏力半导体制造有限公司 | Testing device and corresponding testing method |
| CN102723950A (en) * | 2012-07-03 | 2012-10-10 | 航天科工防御技术研究试验中心 | Test adapter and test method for analog-to-digital converter nonlinear parameters |
| CN104168025A (en) * | 2014-08-25 | 2014-11-26 | 西安交通大学 | Charge type assembly line successive approximation register analog to digital converter |
| CN112311399A (en) * | 2020-01-04 | 2021-02-02 | 成都华微电子科技有限公司 | Analog-digital converter testing device and method |
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- 2021-07-22 CN CN202110831313.1A patent/CN113655306A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638263A (en) * | 2012-04-24 | 2012-08-15 | 上海宏力半导体制造有限公司 | Testing device and corresponding testing method |
| CN102723950A (en) * | 2012-07-03 | 2012-10-10 | 航天科工防御技术研究试验中心 | Test adapter and test method for analog-to-digital converter nonlinear parameters |
| CN104168025A (en) * | 2014-08-25 | 2014-11-26 | 西安交通大学 | Charge type assembly line successive approximation register analog to digital converter |
| CN112311399A (en) * | 2020-01-04 | 2021-02-02 | 成都华微电子科技有限公司 | Analog-digital converter testing device and method |
Non-Patent Citations (4)
| Title |
|---|
| 周凯: "基于参数谱估计的高速高精度ADC测试算法研究与实现", 《中国优秀硕士学位论文全文数据库·信息科技辑》, no. 3, 15 March 2017 (2017-03-15), pages 10 * |
| 周银: "无线通信系统中流水线模数转换器的低成本低功耗研究与设计", 《中国优秀硕士学位论文全文数据库·信息科技辑》, no. 1, 15 January 2016 (2016-01-15), pages 8 * |
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