WO2023005825A1

WO2023005825A1 - Analog-to-digital converter, electric quantity measurement circuit, and battery management system

Info

Publication number: WO2023005825A1
Application number: PCT/CN2022/107292
Authority: WO
Inventors: 陈敏; 丁召明
Original assignee: 合肥市芯海电子科技有限公司
Priority date: 2021-07-30
Filing date: 2022-07-22
Publication date: 2023-02-02
Also published as: CN115694509A

Abstract

Embodiments of the present application provide an analog-to-digital converter, an electric quantity measurement circuit, and an analog-to-digital conversion method. The analog-to-digital converter comprises a modulator, an auxiliary conversion module, and an output module. The modulator is used for converting an input signal in a preset plurality of conversion periods, and outputting a first conversion result after each conversion, the first conversion result comprising a residual signal. The auxiliary conversion module is connected to the modulator, and used for converting the residual signal in the last conversion period among the plurality of conversion periods, and outputting a second conversion result. The output module is connected to the modulator and the auxiliary conversion module, and used for compensating for the residual signal in the last conversion period according to the second conversion result, and outputting a final conversion result.

Description

Analog-to-digital converter, power detection circuit and battery management system

Cross References to Related Applications

This application claims priority to Chinese application No. 2021108717582 filed on July 30, 2021, which is hereby incorporated by reference in its entirety for all purposes.

technical field

The present application relates to the technical field of analog-to-digital conversion, in particular to an analog-to-digital converter, a power detection circuit and a battery management system.

Background technique

In recent years, with the improvement of VLSI manufacturing level, Σ-ΔADC (Sigma-Delta Analog-to-Digital Converter, Σ-ΔADC) is becoming more and more popular with its high resolution, good linearity and low cost. Features are more and more widely used. The low-order incremental Σ-Δ ADC has high measurement accuracy for AC signals, fast dynamic response and low power consumption; however, it has large quantization errors for DC signal measurement accuracy. Therefore, how to improve the measurement accuracy of low-order incremental Σ-Δ ADCs for signals, especially DC signals, is an urgent problem to be solved by those skilled in the art.

Contents of the invention

In view of the above problems, embodiments of the present application provide an analog-to-digital converter, a power detection circuit, and a battery management system to solve the above technical problems.

The embodiment of the present application is realized by adopting the following technical solutions:

An analog-to-digital converter, including a modulator, an auxiliary conversion module, and an output module, the modulator is used to respectively convert input signals within a plurality of preset conversion periods, and output a first conversion result after each conversion, wherein The first conversion result includes a residual signal; the auxiliary conversion module is connected to the modulator, and is used to convert the residual signal of the last conversion cycle in the plurality of conversion cycles, and output the second conversion result; the output module is connected to the modulator and an auxiliary conversion module, configured to compensate the residual signal of the last conversion period according to the second conversion result, and output the final conversion result.

The embodiment of the present application also provides a power detection circuit, including the above-mentioned analog-to-digital converter, and the power detection circuit further includes a sampling circuit; one end of the sampling circuit is used for sampling the input voltage, and the other end is connected to the analog-to-digital converter.

An embodiment of the present application further provides a battery management system, including the above electric power detection circuit.

The embodiment of the present application also provides an analog-to-digital conversion method, which is applied to any one of the above-mentioned analog-to-digital converters. The method includes converting the input signal respectively within a plurality of preset conversion cycles, and after each conversion Outputting a first conversion result, wherein the first conversion result includes a residual signal; converting the residual signal in a last conversion cycle among the plurality of conversion cycles, and outputting a second conversion result; and converting the last conversion result according to the second conversion result The residual signal in the first conversion result of one conversion period is compensated, and the final conversion result is output.

These or other aspects of the present application will be more concise and understandable in the description of the following embodiments.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 shows a block diagram of an analog-to-digital converter provided by an embodiment of the present application.

Fig. 2 shows an example diagram of an implementation manner of an analog-to-digital converter provided in an embodiment of the present application.

FIG. 3 shows an example diagram of a first-order incremental Σ-Δ ADC provided by an embodiment of the present application.

FIG. 4 shows a schematic circuit diagram of a power detection circuit provided by an embodiment of the present application.

FIG. 5 shows a schematic flowchart of an analog-to-digital conversion method provided by an embodiment of the present application.

Detailed ways

Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

With the popularization of fast charging and 5G (5th generation mobile networks, fifth-generation mobile communication technology), accurate mobile phone battery power monitoring function is required. Battery power monitoring is realized by fuel gauge, which is used to measure and display battery power. It usually includes remaining capacity, full capacity, percentage capacity, voltage, current, temperature, etc., and some fuel gauges also include emptying, full time, maximum chemical capacity, and impedance meters. The fuel gauge obtains the charge (current*time) information by sampling the battery current with high precision within a specified time window, and realizes the dynamic refresh of key parameters such as battery power and impedance meter by measuring the open circuit voltage and combining the two information.

The traditional Σ-ΔADC (Sigma-Delta Analog-to-Digital Converter, Σ-ΔADC) does not have accurate automatic gain control, does not eliminate Offset (offset) measures, and uses complex digital decimation filtering Therefore, it cannot meet the requirements of ADCs used in instrumentation and sensor measurement fields. Although the dual-slope ADC has better low offset and precise gain, it requires 2N+1 quantization cycles to achieve N Bit quantization accuracy, and requires the analog circuit to have good matching accuracy. Due to the limitations of the number of quantization cycles and the matching accuracy of analog devices, dual-slope ADCs cannot meet the requirements of high-precision ADCs. Incremental Σ-ΔADC can well meet the application conditions in the field of instrumentation and sensor measurement. Therefore, the incremental Σ-ΔADC is widely used in the battery power monitoring system because it can accurately collect the voltage/current signal of the battery.

The low-order incremental Σ-Δ ADC has high measurement accuracy for AC signals, fast dynamic response and low power consumption; however, it has large quantization errors for DC signal measurement accuracy. The mobile phone battery power monitoring system has high requirements on power consumption, and the battery current needs to respond quickly to fluctuations with the load. It usually uses a low-order incremental Σ-ΔADC with lower power consumption. Therefore, how to improve the signal measurement accuracy of the low-order incremental Σ-Δ ADC, especially the measurement accuracy of the DC signal, is an urgent problem to be solved by those skilled in the art.

After long-term research and verification by the inventor, the embodiment of the present application provides an analog-to-digital converter, a power detection circuit, a battery management system, and an analog-to-digital conversion method. The analog-to-digital converter includes a modulator, an auxiliary conversion module, and an output module. The modulator is used to respectively convert the input signal within a plurality of preset conversion periods, and output a first conversion result after each conversion, wherein the first conversion result includes a residual signal; the auxiliary conversion module is connected to the a modulator, configured to convert the residual signal of the last conversion period among the plurality of conversion periods, and output a second conversion result; the output module is connected to the modulator and the auxiliary conversion module, and Compensating the residual signal of the last conversion cycle according to the second conversion result, and outputting a final conversion result. In this embodiment, the auxiliary conversion module converts the input signal simultaneously with the modulator in the last conversion cycle of the modulator, and compensates the residual signal of the last conversion cycle according to the second conversion result, thereby improving the analog-to-digital converter accuracy.

As shown in FIG. 1 , an embodiment of the present application provides an analog-to-digital converter 100 . The ADC 100 includes a modulator 110 , an auxiliary conversion module 120 and an output module 130 . The modulator 110 is used to respectively convert the input signal within a plurality of preset conversion periods, and output a first conversion result after each conversion, wherein the first conversion result includes a residual signal; the auxiliary conversion module 120 is connected to the modulation The device 110 is used to convert the residual signal of the last conversion cycle among the multiple conversion cycles, and output the second conversion result; the output module 130 is connected to the modulator 110 and the auxiliary conversion module 120, and is used for according to the first The second conversion result compensates the residual signal of the last conversion cycle, and outputs the final conversion result.

Modulator 110 is an incremental sigma-delta modulator. The analog-to-digital converter 100 samples the input signal according to the sampling clock, and sends the input signal to the modulator 110, and the modulator 110 receives the input signal and converts the input signal. For every sample of the analog-to-digital converter 100, the modulator 110 may convert the input signal at least once. In this embodiment, the input signal may be, but not limited to, an AC signal or a DC signal. For the convenience of description, all the conversion cycles in the preset plurality of conversion cycles are referred to as "complete conversion cycles" hereinafter.

The first conversion result output by the modulator 110 each time includes a residual signal, which is related to the conversion error of the modulator 110 . Specifically, in each conversion period, the modulator converts the input signal sampled in the current conversion period and the accumulated conversion error of each previous conversion period to obtain the first conversion result, so the residual signal in the first conversion result corresponds to The superposition of the conversion errors of the conversion cycles preceding the current conversion cycle. Assuming that the preset number of conversion cycles is n, the residual signal in the first conversion result output by the modulator 110 in the i-th cycle corresponds to the accumulated conversion error of the modulator 110 in the previous i-1 cycles , where 1≤i is less than or equal to n.

As an implementation, the first conversion result output by the modulator 110 is a code value, and the code value may correspond to a voltage value, which is the voltage corresponding to the input signal deduced according to the first conversion result of the modulator 110 The value is called the theoretical value of the input signal, and the difference between the theoretical value and the actual value of the input signal is the conversion error of the modulator 110 . The residual signal of the last conversion period corresponds to the superposition of the conversion error of the modulator 110 in the complete conversion period, that is, the difference between the voltage value corresponding to the first conversion result of the last conversion period and the actual voltage value of the input signal. For example, assuming that the actual voltage value corresponding to the input signal is 1V, and the voltage value corresponding to the first conversion result is 1.1V, the conversion error is 0.1V. As another example, assume that the actual voltage value corresponding to the input signal is 1V, the conversion result of the first conversion cycle corresponds to a voltage value of 1.1V, and the conversion error is 0.1V; the conversion result of the second conversion cycle corresponds to a voltage value of 0.8 V, the conversion error is -0.2V; the conversion errors of the first two conversion cycles are superimposed to -0.1V, and the conversion error corresponding to the residual signal output in the third conversion cycle is -0.1V.

In this embodiment, the auxiliary conversion module 120 starts when the modulator 110 converts the input signal for the last time. At this time, in the last conversion cycle of the modulator 110, the auxiliary conversion module 120 converts the residual signal, and then outputs the second Convert the result.

Since the residual signal in the first conversion result output by the modulator 110 in the last conversion cycle (the nth cycle) corresponds to the superposition of the reset cycle and the conversion errors in the previous n-1 conversion cycles, the superposition of the conversion errors The value divided by n is the final conversion error of the modulator, so the residual signal of the last conversion cycle can be used to characterize the final conversion error of the modulator. The auxiliary conversion module 120 converts the residual signal at the last conversion of the modulator 110, so the output module 130 compensates the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, which is equivalent to modulating Therefore, the conversion error of the final conversion result output by the output module 130 is smaller than the conversion error of the first conversion result output by the modulator 110 , thereby improving the conversion accuracy of the analog-to-digital converter 100 . Meanwhile, since the auxiliary conversion module 120 is started only in the last conversion cycle of the modulator 110 , the auxiliary conversion module 120 basically does not increase the power consumption of the ADC 100 , so that the power consumption of the ADC 100 can be kept low.

Therefore, the analog-to-digital converter 100 provided in this embodiment converts the residual signal through the auxiliary conversion module 120 when the modulator 110 converts the input signal for the last time, and outputs the second conversion result; and is connected to the modulator through the output module 130 The converter 110 and the auxiliary conversion module 120 are used to compensate the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, so that the final conversion result output by the output module 130 is compared to the modulator The conversion error of the first conversion result output by 110 is smaller, so as to improve conversion precision while maintaining low power consumption of the analog-to-digital converter 100 .

In some implementations, as shown in FIG. 2 , the modulator 110 includes an integrator 111, a main quantizer 112, and a digital-to-analog converter 113; wherein, the integrator 111 is an incremental Σ-Δ modulation integrator, and the integrator 111 It is used to integrate the difference between the input signal and the output signal of the digital-to-analog converter 113 in each conversion cycle to output the integral signal; the main quantizer 112 is connected to the integrator 111 and is used to quantize the integral signal to output The first conversion result; the digital-to-analog converter 113 is connected to the main quantizer 112 output terminal and the input terminal of the integrator 111 to form a feedback path, and the digital-to-analog converter 113 is used to generate an output signal according to the first conversion result, and output The signal is fed back to the integrator 111 . Optionally, the modulator 110 further includes a first gain module 114 , a second gain module 115 and a third gain module 116 . Wherein the input end of the first gain module 114 is used to receive the input signal, and the output end is connected to the input end of the integrator 111; The second gain module 115 is arranged between the integrator 111 and the main quantizer 112, and the second gain module 115 The input end of is connected to the output end of the integrator 111, and the output end is connected to the input end of the main quantizer 112; The third gain module 116 is arranged in the feedback path, and the input end of the third gain module 116 is connected to the digital-to-analog converter 113 The output terminal of is connected to the input terminal of the integrator 111. Since the first conversion result output by the modulator 110 is the quantization result of the main quantizer 112, the conversion error of the modulator 110 is referred to as "quantization error" hereinafter.

As an example, the main quantizer 112 is a first-order single-bit quantizer, that is, the number of bits of the main quantizer 112 is 1, and the output code value of the main quantizer 112 is 0 or 1. At this time, the main quantizer 112 can be implemented using a comparator. Correspondingly, the digital-to-analog converter 113 outputs a corresponding feedback voltage according to the output code value of the main quantizer 112 . For example, when the output code value of the main quantizer 112 is 1, the DAC 113 outputs the first feedback voltage, and when the output code value of the main quantizer 112 is 0, the DAC 113 outputs the second feedback voltage.

In this embodiment, the modulator 110 is a Σ-Δ modulator, its sampling and conversion frequency is much higher than the frequency of the input signal, and the tracking performance of the above feedback loop will make the voltage value corresponding to the first conversion result and the voltage value of the input signal The long-term average value of the difference tends to zero, that is, the average quantization error or the superimposed quantization error will tend to zero after multiple transformations. In this way, the first conversion result gradually approaches the input value, thereby realizing analog-to-digital conversion. In the actual conversion process, although the average quantization error is getting smaller and smaller, it always exists. Therefore, in this embodiment, the auxiliary conversion module 120 is used to supplement the quantization error of the modulator 110 to improve the conversion accuracy of the analog-to-digital converter 100 .

The auxiliary conversion module 120 includes a clock generation circuit 121 and an auxiliary quantizer 122 . Wherein, the clock generation circuit 121 is used to output a clock signal, and the clock frequency of the clock signal is an integer multiple of the switching frequency of the modulator 110. The auxiliary quantizer 122 is connected to the clock generation circuit 121 and the modulator 110, and is used for performing quantization conversion on the residual signal of the last conversion period, and outputting a second conversion result.

Specifically, the input end of the auxiliary quantizer 122 is connected to the input end of the main quantizer 112, and starts to work when the main quantizer 112 quantizes the input signal for the last time, and the auxiliary quantizer 122 synchronizes with the main quantizer 112 to the second quantizer. The output signal of the gain block 115 is quantized. The first conversion result obtained by the main quantizer 112 after the last quantization is different from the input signal, and the difference between the first conversion result and the input signal is the residual signal; at this time, when the auxiliary quantizer 122 is in the main The quantizer 112 starts quantization synchronously at the last quantization, and the auxiliary quantizer 122 quantizes the residual signal. In this embodiment, the conversion rate of the auxiliary conversion module 120 is an integer multiple of the conversion rate of the modulator 110, that is, the auxiliary quantizer 122 uses the aforementioned clock signal as a high-frequency reference clock, and the quantization rate of the auxiliary quantizer 122 is the main quantizer. An integer multiple of the quantization rate of 112. During the last quantization of the main quantizer 112, the auxiliary quantizer 122 quantizes the residual signal at a quantization rate that is an integral multiple of the quantization rate of the main quantizer 112, and the number of quantization times of the auxiliary quantizer 122 is equal to that of the main quantizer 112. At this time, the auxiliary quantizer 122 and the main quantizer 112 output quantization information synchronously, and the number of code values output by the auxiliary quantizer 122 is an integer multiple of the number of code values output by the main quantizer 112 during the last quantization. For example, if the quantization rate of the auxiliary quantizer 122 is twice the quantization rate of the main quantizer 112, the main quantizer 112 outputs one code value and the auxiliary quantizer 122 outputs two code values during the last quantization. It can be understood that the quantization information output by the auxiliary quantizer 122 is also the second conversion result output by the auxiliary conversion module 120 .

As an implementation manner, the output module 130 includes a digital integration filter 131 , an error compensation module 132 and a weighting module 133 . Wherein, the digital integration filter 131 is connected to the modulator 110, and is used for filtering the first conversion result; the error compensation module 132 is connected to the auxiliary quantizer 122, and is used for converting the second conversion result into an error compensation signal; the weighting module 133 It is connected to the digital integration filter 131 and the error compensation module 132, and is used for performing equivalent processing on the error compensation signal and superimposing it with the first conversion result, and outputting the final conversion result.

Specifically, in this embodiment, the digital integration filter 131 is connected to the output end of the main quantizer 112 to digitally filter the quantized information output by the main quantizer 112 . The digital integration filter 131 may be a low-order digital integration filter 131 or a high-order digital integration filter 131 , and the order of the digital integration filter 131 is not limited in this embodiment. As an example, the digital integration filter 131 may be used to calculate an average value of multiple first conversion results output by the main quantizer within a complete conversion period, and the average value represents the final quantization result of the main quantizer 112 . Optionally, the digital integration filter 131 can be implemented by digital circuits or software.

The error compensation module 132 converts the second conversion result output by the auxiliary quantizer 122 into an error compensation signal. Specifically, the error compensation module 132 converts the code value output by the auxiliary quantizer 122 into an analog signal, so as to facilitate subsequent processing of the second conversion result. For example, assuming that the auxiliary quantizer 122 outputs a code value D[0:1]=11, the error compensation module 132 converts the code value into an analog signal, and outputs V _D[0:1] =3. It can be understood that the converted analog signal is also the error compensation signal.

The weighting module 133 performs further equivalent processing on the error compensation signal output by the error compensation module 132 , and weights the processed error compensation signal to the digital integration filter 131 . Specifically, since the quantization rate of the auxiliary quantizer 122 is an integral multiple of the quantization rate of the main quantizer 112, during the last quantization, the number of code values (ie, the number of bits) output by the auxiliary quantizer 122 is equal to that of the main quantizer. 112 is a multiple of the number of code values output by 112. At this time, the weighting module 133 performs equivalent processing on the code values output by the auxiliary quantizer 122 according to the number of bits of the main quantizer 112, so that the second conversion result output by the auxiliary quantizer 122 is Can be weighted with the first conversion result output by the main quantizer 112 . For example, assume that the auxiliary quantizer 122 outputs a code value D[0:1]=11, which includes two code values; the main quantizer 112 quantizes and outputs a code value for the last time, at this time, the code value D[ 0:1] is converted into an analog signal, the weighting module 133 equivalently processes D[0:1] after the digital-to-analog conversion into a code value and then outputs a digital signal, and then adds the equivalently processed digital signal to the digital integral filter 131, so as to compensate the first conversion result output by the main quantizer 112.

In this embodiment, when the number of bits of the modulator is 1 and the number of bits of the auxiliary quantizer is 2, the weighting module 133 can perform equivalent processing on the error compensation signal by the following formula.

Wherein, V _q-comp is the equivalent error compensation signal; V _D is the error compensation signal; V _ref is the reference voltage of the digital-to-analog converter 113; PGA is the gain of the modulator 110; n is the cycle number of multiple conversion cycles.

As an implementation manner, the weighting module 133 converts the equivalent error compensation signal into a digital signal and accumulates it in the digital integration filter 131, so as to weight the first conversion result output by the main quantizer 112 and output the final conversion result. The final conversion result is due to the compensation effect of the equivalent error compensation signal, and its quantization error is smaller than the first conversion result output by the main quantizer 112. At the same time, because the auxiliary quantizer 122 is only started when the main quantizer 112 is quantized for the last time, In this way, the sampling accuracy and linearity of the analog-to-digital converter 100 are effectively improved, the influence of quantization errors is reduced, and the accuracy is improved without increasing power consumption while maintaining fast dynamic response capability.

As shown in FIG. 3 , the principle of the analog-to-digital converter 100 provided by the embodiment of the present application will be described in detail below by taking the first-order incremental Σ-Δ ADC as an example.

The analog-to-digital converter 100 also includes a reset circuit (not shown in the figure). The reset circuit is used for resetting the analog-to-digital converter 100 in each conversion period of the modulator 110 before converting the input signal, so as to eliminate last quantization information of the analog-to-digital converter 100 . Specifically, the reset circuit can reset the main quantizer 112 , the auxiliary quantizer 122 and the digital integration filter 131 .

When the analog-to-digital converter 100 converts the input signal, in the reset phase: V ₁ [0]=0 (1);

Where V ₁ [0] is the output signal of the second gain module 115 in the reset phase, and the reset phase is referred to as the 0th conversion hereinafter.

The first conversion cycle: V ₁ [1]=(V ₁ [0]+a1*Vin[0]-b1*Vref*D[0])*a2 (2);

Arranged from formula (2): V ₁ [1]=(a1*Vin[0]-b1*Vref*D[0])*a2 (3);

Among them, V ₁ [1] is the output signal of the second gain module 115 in the first conversion period (ie, during the first conversion); a1 is the gain of the first gain module 114; Vin[0] is the input signal in the reset phase b1 is the gain of the third gain module 116; Vref is the reference signal of the digital-to-analog converter 113; D[0] is the code value output by the main quantizer 112 in the reset stage.

The second conversion cycle: V ₁ [2]=(V ₁ [1]+a1*Vin[1]-b1*Vref*D[1])*a2 (4);

Arranged from formula (4): V ₁ [2]=[a1*(Vin[1]+Vin[0])-b1*Vref*(D[1]+D[0])]*a2 (5) ;

Wherein, V ₁ [2] is the output signal of the second gain module 115 in the second conversion period (that is, during the second conversion); Vin[1] is the input sampled by the analog-to-digital converter 100 in the first conversion period signal; D[1] is the code value output by the main quantizer 112 during the first conversion.

From this it can be deduced that at the nth conversion:

Wherein, V ₁ [n] is the output signal of the second gain module 115 during the nth conversion; Vin[k] is the input signal; D[k] is the digital integral filter.

Since the analog-to-digital converter 100 is a first-order incremental Σ-ΔADC, the input signal Vin satisfies the following formula:

Wherein, PGA is the gain of the analog-to-digital converter 100, PGA=a1/b1; D[k] is the code value output by the main quantizer 112 in the kth conversion period, that is, the first conversion result of the kth conversion period.

In formula (7),

Vq=[V ₁ [n]/(b1*a2)]/(n*PGA).

Wherein, -Vref/(n*PGA)≤Vq≤Vref/(n*PGA); -Vref*b1*a2≤V ₁ [n]≤Vref*b1*a2. Vin' is the input voltage corresponding to the final conversion result of the main quantizer 112 and the theoretical value of the input voltage; Vq is the residual error of the first conversion result, that is, the difference between the theoretical value and the actual input voltage.

In the embodiment of the present application, when the main quantizer 112 switches for the last time, the auxiliary quantizer 122 starts to quantize the output signal of the second gain module 115 synchronously with the main quantizer 112, and the conversion rate of the auxiliary quantizer 122 is equal to that of the main quantizer. 112 M times the conversion rate Fs. In this embodiment, M=2. That is, the second conversion result output by the auxiliary quantizer 122 is D[0:1].

As an implementation manner, the output range of the main quantizer 112 is -Vref˜+Vref, and the quantization level is defined as 4 intervals.

When -Vref≤V ₁ [n]/(b1*a2)≤-Vref/2, D[0:1]=00, at this time the error compensation signal V _D[0:1] output by the error compensation module 132 = 0, the equivalent error compensation signal output by the weighting module 133

When -Vref/2<V ₁ [n]/(b1*a2)≤0, D[0:1]=01, at this time the error compensation signal V _D[0:1] output by the error compensation module 132=1 , the equivalent error compensation signal output by the weighting module 133

When 0<V ₁ [n]/(b1*a2)≤Vref/2, D[0:1]=10, at this time the error compensation signal V _D[0:1] =2 output by the error compensation module 132, The equivalent error compensation signal output by the weighting module 133

When Vref/2<V ₁ [n]/(b1*a2)≤Vref, D[0:1]=11, at this time the error compensation signal V _D[0:1] =3 output by the error compensation module 132, The equivalent error compensation signal output by the weighting module 133

Suppose a1=40/15, b1=4/15, a2=21/24, PGA=10, input signal Vin=5.4uV, Vref=1.2V, Fs=65536Hz, n=65536.

At this time, the quantization error Vq of the main quantizer 112=[V ₁ [n]/(b1*a2)]/(n*PGA)=1.74μV; the first conversion result Vin'=Vin-Vq=3.66μV, that is The measurement error of the second conversion result output by the main quantizer 112 is 1.74uV.

Assuming that the second conversion result D[0:1]=11 output by the auxiliary quantizer 122, then the equivalent error compensation signal output by the weighting module 133 at this time

After the weighting module 133 superimposes the equivalent error compensation signal and the first conversion result output by the main quantizer 112, the final conversion result Vin"=3.66 μV+1.83 μV=5.49 μV is output. At this time, the measurement error of the final conversion result Vin" is 0.09uV. Therefore, the measurement error of the analog-to-digital converter 100 is reduced from 1.74uV to 0.09uV, and the precision of the analog-to-digital converter 100 is improved. It can be seen that the quantization error of the analog-to-digital converter 100 is small, the measurement accuracy is high while maintaining low power consumption, and the dynamic response capability is good.

The analog-to-digital converter provided in the embodiment of the present application includes a modulator, an auxiliary conversion module, and an output module. The modulator is used to convert the input signal respectively within a plurality of preset conversion cycles, and output the first converted signal after each conversion. As a result, wherein the first conversion result includes a residual signal; the auxiliary conversion module is connected to the modulator, and is used to convert the residual signal of the last conversion period among the plurality of conversion periods, and output The second conversion result; the output module is connected to the modulator and the auxiliary conversion module, and is used to compensate the residual signal of the last conversion cycle according to the second conversion result, and output the final conversion result. In this embodiment, the auxiliary conversion module converts the input signal simultaneously with the modulator in the last conversion cycle of the modulator, and compensates the residual signal of the last conversion cycle according to the second conversion result, thereby improving the analog-to-digital converter accuracy.

As shown in FIG. 4 , the embodiment of the present application also provides a power detection circuit 200 . The power detection circuit 200 includes a sampling circuit 210 and the above-mentioned analog-to-digital converter 100 . Wherein, one end of the sampling circuit 210 is used for sampling the input signal, and the other end is connected to the analog-to-digital converter 100 .

The sampling circuit 210 includes a first resistor R1, a second resistor R2, a third resistor R3 and a capacitor C1. Wherein, the first end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end is connected to the first end of the third resistor R3; the two ends of the first resistor R1 are also respectively connected to the two ends of the battery BAT end; the first end of the capacitor C1 is connected to the second end of the second resistor R2, and the second end is connected to the second end of the third resistor R3; the second end of the second resistor R2 is connected to the second end of the third resistor R3 connected to the analog-to-digital converter.

The sampling circuit 210 can sample the voltage of the battery BAT, convert the sampled signal into a differential signal, and input it to the analog-to-digital converter for high-precision measurement.

The power detection circuit provided in this embodiment includes a modulator, an auxiliary conversion module, and an output module, and the modulator is used to respectively convert the input signal within a plurality of preset conversion cycles, and output the first conversion result after each conversion, Wherein the first conversion result includes a residual signal; the auxiliary conversion module is connected to the modulator, and is used to convert the residual signal of the last conversion period among the plurality of conversion periods, and output a second The conversion result: the output module is connected to the modulator and the auxiliary conversion module, and is used for compensating the residual signal of the last conversion cycle according to the second conversion result, and outputting a final conversion result. In this embodiment, the auxiliary conversion module converts the input signal simultaneously with the modulator in the last conversion cycle of the modulator, and compensates the residual signal of the last conversion cycle according to the second conversion result, thereby improving the analog-to-digital converter accuracy.

An embodiment of the present application further provides a battery management system, which includes the above electric power detection circuit.

As shown in FIG. 5 , the embodiment of the present application also provides an analog-to-digital conversion method 300 , which can be applied to incremental Σ-Δ ADCs. The analog-to-digital conversion method 300 includes the following steps S310 to S330 .

Step S310: Convert the input signal respectively within a plurality of preset conversion periods, and output a first conversion result after each conversion, wherein the first conversion result includes a residual signal.

In this embodiment, the analog-to-digital converter samples the input signal according to the sampling clock, and converts the input signal. The analog-to-digital converter converts the input signal at least once per sample.

Each first conversion result includes a residual signal that is related to the conversion error. Specifically, in each conversion cycle, the input signal sampled in the current conversion cycle is converted with the accumulated conversion error of each previous conversion cycle to obtain the first conversion result, so the residual signal in the first conversion result corresponds to the current conversion The superposition of the conversion errors of the individual conversion cycles preceding the cycle. Assuming that the preset number of conversion cycles is n, the residual signal in the first conversion result output by the modulator 110 in the i-th cycle corresponds to the accumulated conversion error of the modulator 110 in the previous i-1 cycles , where 1≤i is less than or equal to n.

Step S320: In the last conversion cycle among the plurality of conversion cycles, perform auxiliary conversion on the residual signal, and output a second conversion result.

In this embodiment, during the last conversion cycle of the analog-to-digital converter, auxiliary conversion may be performed on the residual signal at the same time. Specifically, an additional auxiliary conversion module may be started in the last cycle of the analog-to-digital converter, and the residual signal may be auxiliary quantized synchronously with the analog-to-digital converter, so as to obtain the second conversion result.

Step S330: Compensate the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, and output the final conversion result.

In this embodiment, since the residual signal in the first conversion result output in the last conversion cycle (the nth cycle) corresponds to the superposition of the reset cycle and the conversion errors in the previous n-1 conversion cycles, the conversion error The superposition value divided by n is the final conversion error, so the residual signal of the last conversion cycle can be used to characterize the final conversion error. Auxiliary conversion is performed on the residual signal at the last conversion, so the residual signal in the first conversion result of the last conversion cycle can be compensated according to the second conversion result, which is equivalent to compensation for the final conversion error, so the final conversion The conversion error of the result is smaller than the conversion error of the first conversion result, thereby improving the conversion accuracy of the analog-to-digital converter.

The analog-to-digital conversion method provided by the embodiment of the present application converts the input signal respectively within a plurality of preset conversion periods, and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal; and performing auxiliary conversion on the residual signal in the last conversion cycle of the plurality of conversion cycles, and outputting a second conversion result; then compensating the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, And output the final conversion result, thereby improving the precision of the analog-to-digital converter.

The above are only the preferred embodiments of the application, and do not limit the application in any form. Although the application has been disclosed as above with the preferred embodiments, it is not intended to limit the application. Anyone skilled in the art, Without departing from the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or be modified into equivalent embodiments with equivalent changes, but if it does not deviate from the technical solution of the application, the technical essence of the application will Any brief modifications, equivalent changes and modifications made in the above embodiments still fall within the scope of the technical solutions of the present application.

Claims

An analog-to-digital converter, characterized in that it comprises:

a modulator, configured to respectively convert the input signal within a plurality of preset conversion periods, and output a first conversion result after each conversion, wherein the first conversion result includes a residual signal;

an auxiliary conversion module, connected to the modulator, configured to convert the residual signal of the last conversion period among the plurality of conversion periods, and output a second conversion result; and

The output module is connected to the modulator and the auxiliary conversion module, and is used for compensating the residual signal of the last conversion period according to the second conversion result, and outputting a final conversion result.
The analog-to-digital converter according to claim 1, wherein the conversion rate of the auxiliary conversion module is an integer multiple of the conversion rate of the modulator.
The analog-to-digital converter according to claim 2, wherein the auxiliary conversion module comprises:

a clock generating circuit for outputting a clock signal whose clock frequency is an integer multiple of the switching frequency of the modulator; and

An auxiliary quantizer, connected to the clock generation circuit and the modulator, is used to quantize and convert the residual signal in the last conversion period, and output the second conversion result.
The analog-to-digital converter according to claim 3, wherein the output module comprises:

a digital integration filter connected to the modulator for filtering the first conversion result; and

an error compensation module, connected to the auxiliary quantizer, for converting the second conversion result into an error compensation signal; and

A weighting module, connected to the digital integration filter and the error compensation module, is used for performing equivalent processing on the error compensation signal and superimposing it with the first conversion result, and outputting the final conversion result.
The analog-to-digital converter according to claim 4, wherein, when the number of bits of the modulator is 1 and the number of bits of the auxiliary quantizer is 2, the weighting module applies the following formula to the The above error compensation signal is equivalently processed:

Wherein, V D is the error compensation signal; V ref is the reference voltage of the digital-to-analog converter; PGA is the gain of the modulator; n is the cycle number of the plurality of conversion cycles.
The analog-to-digital converter according to claim 1, wherein the analog-to-digital converter further comprises a reset circuit, and the reset circuit is used for the modulator to perform an operation on the input signal in each conversion cycle. Before conversion, reset the analog-to-digital converter.
The analog-to-digital converter of claim 1, wherein the modulator comprises an integrator, a main quantizer, and a digital-to-analog converter;

The integrator is used to integrate the difference between the input signal and the output signal of the digital-to-analog converter in each conversion cycle to output an integrated signal;

The main quantizer is connected to the integrator and used to quantize the integrated signal to output the first conversion result; and

The digital-to-analog converter is connected to the output terminal of the main quantizer and the input terminal of the integrator, and is used for generating an output signal according to the first conversion result, and feeding the output signal back to the integrator.
A power detection circuit, characterized in that it includes the analog-to-digital converter described in one of claims 1 to 7 above, and the power detection circuit also includes a sampling circuit; one end of the sampling circuit is used to sample the input voltage, and the other end is connected to in the analog-to-digital converter.
A battery management system, characterized by comprising the power detection circuit according to claim 8.
An analog-to-digital conversion method, applied to the analog-to-digital converter described in any one of claims 1 to 7, characterized in that the method comprises:

Converting the input signal respectively within a plurality of preset conversion periods, and outputting a first conversion result after each conversion, wherein the first conversion result includes a residual signal;

In a last conversion cycle of the plurality of conversion cycles, converting the residual signal and outputting a second conversion result; and

Compensating the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, and outputting a final conversion result.