CN113644054B - Radiation-resistant transistor - Google Patents
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- CN113644054B CN113644054B CN202110803430.7A CN202110803430A CN113644054B CN 113644054 B CN113644054 B CN 113644054B CN 202110803430 A CN202110803430 A CN 202110803430A CN 113644054 B CN113644054 B CN 113644054B
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- 230000005855 radiation Effects 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000000956 alloy Substances 0.000 claims abstract description 4
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 43
- 238000001259 photo etching Methods 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- 238000001465 metallisation Methods 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 23
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 23
- 229910052796 boron Inorganic materials 0.000 claims description 23
- 229910052698 phosphorus Inorganic materials 0.000 claims description 23
- 239000011574 phosphorus Substances 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 22
- 230000001590 oxidative effect Effects 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005275 alloying Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000004151 rapid thermal annealing Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 230000004913 activation Effects 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 6
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 description 20
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 238000001459 lithography Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003213 activating effect Effects 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 2
- 230000005865 ionizing radiation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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Abstract
The invention provides a radiation-resistant transistor, which comprises a collector region, wherein a base region is formed on the collector region; an emitter region A is generated on the base region, an alloy layer is processed at the bottom of the collector region, a plurality of guard rings are further processed on the base region, metal layers are arranged on the emitter region A and the guard rings, and the upper ends of the base region and the guard rings are sealed through a seal layer. The invention controls the impurity concentration of the base region, the emitter region A and the collector region, so that the transistor has small performance influence when receiving radiation, and when the transistor receives radiation, because the doping concentration of each region has a gradient mutually, the energy proportion given by the radiation is lower, so that the change rate of IC and IB is in a certain range, the amplification factor is not changed greatly, and the normal operation of the satellite is ensured.
Description
Technical Field
The invention relates to a radiation-resistant transistor.
Background
In the field of aerospace, satellites in particular, are subject to a great deal of cosmic radiation during their orbital motion. Cosmic radiation is divided into two types, namely neutron radiation and ionizing radiation, and gamma rays in the ionizing radiation can cause the carrier concentration of a semiconductor device in a satellite to change, so that the resistivity of a base region of a transistor is reduced, and parameters such as an amplification factor vibrate. Affecting the normal operation of the satellite.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a radiation-resistant transistor.
The invention is realized by the following technical scheme.
The invention provides a radiation-resistant transistor, which comprises a collector region, wherein a base region is formed on the collector region; an emitter region A and an emitter region B are inlaid on the base region, an alloy layer is processed at the bottom of the collector region, a plurality of guard rings are further processed on the base region, metal layers are arranged on the emitter region A and the guard rings, the upper ends of the base region and the guard rings are sealed through a seal layer, and the doping concentrations of the collector region, the base region and the emitter region A are changed in a gradient mode.
The emitter regions B are a plurality of and are uniformly embedded in the middle of the base region.
The emitter region a is embedded in the base region.
The lower end of the guard ring is a doped layer made of the same material as the emitter region A, and the upper end of the guard ring extends out of the base region and is connected with the metal layer.
The sealing layer is three layers, namely an oxygen silicon layer, a loose silicon nitride layer and a compact silicon nitride layer from bottom to top.
The thicknesses of the silicon oxide layer, the loose silicon nitride layer and the dense silicon nitride layer are respectively 800-1300A, 1800-2500A and 5000-7000A.
The manufacturing process comprises the following steps:
1) performing epitaxy to obtain N-type epitaxial wafer with resistivity of 4-6 Ω -cm;
2) oxidizing to form an oxide layer;
3) carrying out primary photoetching to etch the middle part of the oxide layer to form an injection hole;
4) ion implantation is carried out in the hole, and activation is carried out after a base region is formed, so that the doping concentration of the formed base region is 1E17/cm3-5E18/cm3；
5) Photoetching is carried out on the base region, and an injection hole of the emitter region A is etched;
6) ion implantation is performed at the hole to form a doping concentration of 1E19/cm3-5E19/cm3The emitting region A;
7) photoetching the bottom of the epitaxial wafer;
8) performing back ion implantation to form a doping concentration of 1E19/cm3-5E19/cm3The collector region of (1);
9) photoetching the base region to form an injection hole of the protection ring;
10) carrying out ion implantation at the collector junction to form a guard ring;
11) growing a passivation layer;
12) performing fifth photoetching to reserve the passivation layer of the region except the electrode;
13) carrying out front metallization;
14) carrying out sixth photoetching to reserve the metal layer on the electrode;
15) carrying out alloying;
16) carrying out a thinning process;
17) back side metallization is performed.
The transistors include NPN type and PNP type.
When the NPN transistor forms a P-region base region, the energy of boron implantation is 60keV, the implantation angle is 7 degrees, and the P-region of the base region is formed to ensure that the doping concentration is 1E17/cm3-1E19/cm3；
The PNP type transistor forms an N-region base region, the energy of phosphorus injection is 100keV, the angle is 7 degrees, and an N-region of the base region is formed, so that the doping concentration of the N-region is 1E17/cm3-5E18/cm3。
When the NPN transistor forms an N-region emitter region A, the energy of phosphorus implantation is 100keV, the implantation angle is 9 degrees, and the formed doping concentration is 1E17/cm3-5E19/cm3The emitting region A;
when the PNP transistor forms a P-region emitter A, the energy of boron implantation is 90keV, the angle is 7 degrees, and the formed doping concentration is 1E17/cm3-1E19/cm3The emission region a.
When the NPN type transistor forms a collector region, the energy of phosphorus implantation is 100keV, the implantation angle is 7 degrees, and the formed doping concentration is 1E17/cm3-5E19/cm3The collector region of (1);
the PNP type transistorWhen the collector region was formed, the boron implantation energy was 60keV at an angle of 7 DEG to form a doping concentration of 1E17/cm3-1E19/cm3The collector region of (1).
The oxide layer adopts a dry-wet-dry growth mode, the oxidation time is 120-160 minutes, and the temperature is 1000-1200 ℃.
And performing rapid thermal annealing activation during each ion implantation, wherein the temperature is 900-1100 ℃, and the time is 10-60S.
The invention has the beneficial effects that: the impurity concentration of the base region, the emission region and the collector region is controlled, so that the performance influence is small when the transistor receives radiation, and when the transistor receives radiation, the energy occupation ratio given by radiation is lower because the doping concentration of each region has a gradient mutually, so that the change rate of IC and IB is in a certain range, the amplification factor is not changed greatly, and the normal operation of the satellite is ensured.
Drawings
FIG. 1 is a schematic structural view of the present invention;
in the figure: 1-sealing layer, 2-base region, 3-emitter region A, 4-collector region, 5-guard ring, 6-emitter region B, 7-metal layer and 8-alloy layer.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
Example 1:
the manufacturing method of the NPN radiation-resistant transistor comprises the following steps:
1, manufacturing an N epitaxial wafer with the substrate resistivity of 3 omega cm; the epitaxial wafer is provided with 1E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A. It cannot be too thick, which can be used as a masking layer for ion implantation, to prevent too large height difference.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting boron at an angle of 7 DEG and 60keV to form base region 2Then activated to a doping concentration of 1E17/cm3。
5 performing 2 times of lithography, leaving the specified positions:
6 at a given position, 2 times of phosphorus implantation with energy of 100keV and angle of 9 deg. is carried out to form N + region 3 of the emitter region, which is then activated to a doping concentration of 2E19/cm3；
7 photolithography was performed 3 times, leaving the specified positions:
8, performing back phosphorus implantation with energy of 100keV and implantation angle of 7 ° for 2-3 times to form a doping concentration of 3E19/cm3The doping level difference between the N + region and the N-region of the collector 4 is 2-3 powers.
9 lithography pass 4, leaving the specified positions:
10 phosphorus implantation is performed in the N-region of the collector junction to form an N + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3A concentration gradient is manufactured outside a chip wafer to protect an internal high-concentration doping area.
And 11, growing a passivation layer which is respectively silicon oxide 900A, loose silicon nitride 1900A and dense silicon nitride 5500A from bottom to top, wherein the passivation layer is on a top plane and serves as the uppermost area of the structural space to protect the chip.
12 performing 5 th photolithography to retain the passivation layer in the region except the electrode
13 carrying out front metallization, wherein the material is aluminum;
14, carrying out 6 th photoetching to keep the metal layer on the electrode;
15, alloying at 450 ℃ for 15 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and the device performance is improved.
16, thinning process is carried out, the area with low doping concentration is removed, and saturation pressure drop is reduced.
17, back metallization is carried out, and the titanium-nickel-silver layer can enable subsequent packaging and attaching efficiency to be higher.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
Example 2: the manufacturing method of the NPN radiation-resistant transistor comprises the following steps:
1, manufacturing an N epitaxial wafer with the substrate resistivity of 4 omega cm; the epitaxial wafer is provided with 3E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 140 minutes, the temperature is 1150 ℃, and the thickness of the oxide layer is 1000A. It cannot be too thick, which can be used as a masking layer for ion implantation, to prevent too large height difference.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting boron at an angle of 7 deg. and 60keV to form a P-region of base region 2, and activating to obtain a doping concentration of 1E17/cm3。
5 performing 2 times of lithography, leaving the specified positions:
6 at a given position, 2 times of phosphorus implantation with energy of 100keV and angle of 9 deg. is carried out to form N + region 3 of the emitter region, which is then activated to a doping concentration of 3E19/cm3；
7 photolithography was performed 3 times, leaving the specified positions:
8, performing back phosphorus implantation with energy of 100keV and implantation angle of 7 ° for 2-3 times to form a doping concentration of 4E19/cm3The doping level difference between the N + region and the N-region of the collector 4 is 2-3 powers.
9 lithography pass 4, leaving the specified positions:
10 phosphorus implantation is performed in the N-region of the collector junction to form an N + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E12/cm3A concentration gradient is manufactured outside a chip wafer to protect an internal high-concentration doping area.
And 11, growing a passivation layer, namely silicon oxide 1000A, loose silicon nitride 2100A and dense silicon nitride 6000A from bottom to top, wherein the passivation layer is on a top plane and serves as the uppermost area of the structural space to protect the chip.
12 performing 5 th photolithography to retain the passivation layer in the region except the electrode
13 carrying out front metallization, wherein the material is aluminum;
14, carrying out 6 th photoetching to keep the metal layer on the electrode;
15, alloying at 450 ℃ for 15 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and the device performance is improved.
16, thinning process is carried out, the area with low doping concentration is removed, and saturation pressure drop is reduced.
17, back metallization is carried out, and the titanium-nickel-silver layer can enable subsequent packaging and attaching efficiency to be higher.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
Example 3: the manufacturing method of the NPN radiation-resistant transistor comprises the following steps:
1, manufacturing an N epitaxial wafer with the substrate resistivity of 5 omega cm; the epitaxial wafer is provided with 1E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A. It cannot be too thick, which can be used as a masking layer for ion implantation, to prevent too large height difference.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting boron at an angle of 7 deg. and 60keV to form a P-region of base region 2, and activating to obtain a doping concentration of 1E18/cm3。
5 performing 2 times of lithography, leaving the specified positions:
6 at a given position, 2 times of phosphorus implantation with energy of 100keV and angle of 9 deg. is carried out to form N + region 3 of the emitter region, which is then activated to a doping concentration of 2E19/cm3；
7 photolithography was performed 3 times, leaving the specified positions:
8, performing back phosphorus implantation with energy of 100keV and implantation angle of 7 ° for 2-3 times to form a doping concentration of 4E19/cm3The N + region 4 of the collector region of (a),the doping levels between the N + and N-regions of the collector 4 differ by 2-3 powers.
9 lithography pass 4, leaving the specified positions:
10 injecting phosphorus into the N-region of the collector junction to form an N + region 5; this region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3A concentration gradient is manufactured outside a chip wafer to protect an internal high-concentration doping area.
And 11, growing a passivation layer which is respectively silicon oxide 900A, loose silicon nitride 1900A and dense silicon nitride 5500A from bottom to top, wherein the passivation layer is on a top plane and serves as the uppermost area of the structural space to protect the chip.
12 performing 5 th photolithography to retain the passivation layer in the region except the electrode
13 carrying out front metallization, wherein the material is aluminum;
14, carrying out 6 th photoetching to keep the metal layer on the electrode;
15, alloying at 450 ℃ for 15 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and the device performance is improved.
16, thinning process is carried out, the area with low doping concentration is removed, and saturation pressure drop is reduced.
17, back metallization is carried out, and the titanium-nickel-silver layer can enable subsequent packaging and attaching efficiency to be higher.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
Example 4: the manufacturing method of the NPN radiation-resistant transistor comprises the following steps:
1, manufacturing an N epitaxial wafer with the substrate resistivity of 6 omega cm; the epitaxial wafer is provided with 1E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A. It cannot be too thick, which can be used as a masking layer for ion implantation, to prevent too large height difference.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting boron at an angle of 7 deg. and 60keV to form a P-region of base region 2, and activating to obtain a doping concentration of 1E18/cm3。
5 performing 2 times of lithography, leaving the specified positions:
6 at a given position, 2 times of phosphorus implantation with energy of 100keV and angle of 9 deg. is carried out to form N + region 3 of the emitter region, which is then activated to a doping concentration of 3E19/cm3；
7 photolithography was performed 3 times, leaving the specified positions:
8, performing back phosphorus implantation with energy of 100keV and implantation angle of 7 ° for 2-3 times to form a doping concentration of 4E19/cm3The doping level difference between the N + region and the N-region of the collector 4 is 2-3 powers.
9 lithography pass 4, leaving the specified positions:
10 phosphorus implantation is performed in the N-region of the collector junction to form an N + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3A concentration gradient is manufactured outside a chip wafer to protect an internal high-concentration doping area.
And 11, growing a passivation layer which is respectively silicon oxide 900A, loose silicon nitride 1900A and dense silicon nitride 5500A from bottom to top, wherein the passivation layer is on a top plane and serves as the uppermost area of the structural space to protect the chip.
12 performing 5 th photolithography to retain the passivation layer in the region except the electrode
13 carrying out front metallization, wherein the material is aluminum;
14, carrying out 6 th photoetching to keep the metal layer on the electrode;
15, alloying at 450 ℃ for 15 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and the device performance is improved.
16, thinning process is carried out, the area with low doping concentration is removed, and saturation pressure drop is reduced.
17, back metallization is carried out, and the titanium-nickel-silver layer can enable subsequent packaging and attaching efficiency to be higher.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
1, a P epitaxial wafer having a resistivity of 2. omega. cm was produced. The epitaxial wafer is provided with 3E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting phosphorus with an angle of 7 deg. and a doping concentration of 3E18/cm into the N-region of the base region at 100keV3。
5 photolithography was performed 2 times, leaving the specified positions.
Implanting boron at the given position at energy of 90keV and angle of 7 deg. for 1-2 times to form P + region 3 of the emitter region, and activating to obtain a dopant concentration of 4E19/cm3。
6 photolithography was performed 3 times, leaving the specified positions.
7 carrying out 2 times of back boron implantation with energy of 60keV and implantation angle of 7 degrees to form doping concentration of 5E19/cm3The doping level difference between the P + region and the P-region of the collector 4 is 2-3 powers.
The 4 th lithography is performed 8, leaving the specified locations.
9 boron implantation is performed in the P-region of the collector junction to form a P + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3And a concentration gradient is manufactured outside the chip wafer to protect the high-concentration doping area inside.
10 growing a passivation layer, which is silicon oxide 1000A, loose silicon nitride 2000A and dense silicon nitride 6000A from bottom to top respectively, on the top plane as the uppermost region of the structural space to protect the chip.
11, the 5 th photolithography is performed to leave the passivation layer in the region except the electrode.
12 front side metallization is carried out, and the material is aluminum.
13, 6 th photoetching is carried out, and the metal layer on the electrode is remained.
And 14, alloying at 480 ℃ for 20 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and improving the performance of the device.
15 thinning process is carried out, the area with low doping concentration is removed, the saturation voltage drop is reduced, and finally the thickness of the chip is 180-230 microns.
16, back metallization is carried out, the thicknesses of the back metallization are 85nm and 85nm respectively, and the subsequent packaging and attaching efficiency can be higher due to the titanium-nickel-silver layer with the silver thickness of 145 nm.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
1, a P epitaxial wafer having a resistivity of 2. omega. cm was produced. The epitaxial wafer is provided with 2E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting phosphorus with an angle of 7 deg. and a doping concentration of 3E18/cm into the N-region of the base region at 100keV3。
5 photolithography was performed 2 times, leaving the specified positions.
Implanting boron at the given position at energy of 90keV and angle of 7 deg. for 1-2 times to form P + region 3 of the emitter region, and activating to obtain a dopant concentration of 4E19/cm3。
6 photolithography was performed 3 times, leaving the specified positions.
7 carrying out 2 times of back boron implantation with energy of 60keV and implantation angle of 7 degrees to form doping concentration of 5E19/cm3P + region 4 of the collector region, doping between the P + region and the P-region of the collector 4The difference between the miscellaneous levels is 2-3 powers.
The 4 th lithography is performed 8, leaving the specified locations.
9 boron implantation is performed in the P-region of the collector junction to form a P + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3And a concentration gradient is manufactured outside the chip wafer to protect the high-concentration doping area inside.
10 growing a passivation layer, which is silicon oxide 1000A, loose silicon nitride 2000A and dense silicon nitride 6000A from bottom to top respectively, on the top plane as the uppermost region of the structural space to protect the chip.
11, the 5 th photolithography is performed to leave the passivation layer in the region except the electrode.
12 front side metallization is carried out, and the material is aluminum.
13, 6 th photoetching is carried out, and the metal layer on the electrode is remained.
And 14, alloying at 480 ℃ for 20 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and improving the performance of the device.
15 thinning process is carried out, the area with low doping concentration is removed, the saturation voltage drop is reduced, and finally the thickness of the chip is 180-230 microns.
16, back metallization is carried out, the thicknesses of the back metallization are 85nm and 85nm respectively, and the subsequent packaging and attaching efficiency can be higher due to the titanium-nickel-silver layer with the silver thickness of 145 nm.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
1, a P epitaxial wafer having a resistivity of 4. omega. cm was produced. The epitaxial wafer itself is doped with 3E 15.
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting phosphorus with an angle of 7 deg. and a doping concentration of 3E18/cm into the N-region of the base region at 100keV3。
5 photolithography was performed 2 times, leaving the specified positions.
Implanting boron at the given position at energy of 90keV and angle of 7 deg. for 1-2 times to form P + region 3 of the emitter region, and activating to obtain a dopant concentration of 4E19/cm3。
6 photolithography was performed 3 times, leaving the specified positions.
7 carrying out 2 times of back boron implantation with energy of 60keV and implantation angle of 7 degrees to form the doping concentration of 4E19/cm3The doping level difference between the P + region and the P-region of the collector 4 is 2-3 powers.
The 4 th lithography is performed 8, leaving the specified locations.
9 boron implantation is performed in the P-region of the collector junction to form a P + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3And a concentration gradient is manufactured outside the chip wafer to protect the high-concentration doping area inside.
10 growing a passivation layer, which is silicon oxide 1000A, loose silicon nitride 2000A and dense silicon nitride 6000A from bottom to top respectively, on the top plane as the uppermost region of the structural space to protect the chip.
11 performing 5 th photolithography to retain the passivation layer in the region except the electrode
12 front side metallization is carried out, and the material is aluminum.
13, 6 th photoetching is carried out, and the metal layer on the electrode is remained.
And 14, alloying at 480 ℃ for 20 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and improving the performance of the device.
15 thinning process is carried out, the area with low doping concentration is removed, the saturation voltage drop is reduced, and finally the thickness of the chip is 180-230 microns.
16, back metallization is carried out, the thicknesses of the back metallization are 85nm and 85nm respectively, and the subsequent packaging and attaching efficiency can be higher due to the titanium-nickel-silver layer with the silver thickness of 145 nm.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
1, a P epitaxial wafer having a resistivity of 5. omega. cm was produced. The epitaxial wafer is provided with 5E15/cm3Doping of (3).
2, oxidizing to form an oxide layer, and adopting a dry-wet-dry growth mode, wherein the oxidizing time is 130 minutes, the temperature is 1100 ℃, and the thickness of the oxide layer is 900A.
And 3, carrying out 1-time photoetching, etching the oxide layer, and forming holes in the designated area.
4 implanting phosphorus with an angle of 7 deg. and a doping concentration of 4E18/cm into the N-region of the base region at 100keV3。
5 photolithography was performed 2 times, leaving the specified positions.
Implanting boron at the given position at energy of 90keV and angle of 7 deg. for 1-2 times to form P + region 3 of the emitter region, and activating to obtain a dopant concentration of 3E19/cm3。
6 photolithography was performed 3 times, leaving the specified positions.
7 carrying out 2 times of back boron implantation with energy of 60keV and implantation angle of 7 degrees to form doping concentration of 2E19/cm3The doping level difference between the P + region and the P-region of the collector 4 is 2-3 powers.
The 4 th lithography is performed 8, leaving the specified locations.
9 boron implantation is performed in the P-region of the collector junction to form a P + region 5. This region serves as a guard ring for the final dicing of the chip and is implanted at a dose of 1E15/cm3And a concentration gradient is manufactured outside the chip wafer to protect the high-concentration doping area inside.
10 growing a passivation layer, which is silicon oxide 1000A, loose silicon nitride 2000A and dense silicon nitride 6000A from bottom to top respectively, on the top plane as the uppermost region of the structural space to protect the chip.
11, the 5 th photolithography is performed to leave the passivation layer in the region except the electrode.
12 front metallization is carried out, the material is aluminum, and the thickness is 2-5 microns.
13, 6 th photoetching is carried out, and the metal layer on the electrode is remained.
And 14, alloying at 480 ℃ for 20 minutes, wherein the temperature and the time can enable the aluminum and the silicon layer to form ohmic contact, and improving the performance of the device.
15 thinning process is carried out, the area with low doping concentration is removed, the saturation voltage drop is reduced, and finally the thickness of the chip is 180-230 microns.
16, back metallization is carried out, the thicknesses of the back metallization are 85nm and 85nm respectively, and the subsequent packaging and attaching efficiency can be higher due to the titanium-nickel-silver layer with the silver thickness of 145 nm.
Note: each ion implantation is activated by rapid thermal annealing at 900-1100 deg.C for 10-60S.
The NPN type VCB is 40-60V, the VCE is 15-30V, and the amplification factor is 200-450 times. And by controlling the impurity concentration of the base region, the emitter region and the collector region, the transistor has small performance influence when receiving radiation, the amplification factor of the transistor is IC/IB, when the transistor receives radiation, each region of the transistor obtains energy, as long as the doping concentration of each region is high enough and mutually has gradient, the energy ratio given by radiation is lower, the change rate of the IC and the IB is in a certain range, and therefore the amplification factor is not greatly changed. And finally, the region with low doping concentration is removed and thinned, so that the saturation voltage drop is reduced, and finally the whole thickness of the chip is 180-230 microns.
The data for examples 1 to 4 are shown in Table 1.
The data for examples 5 to 8 are shown in Table 2.
Claims (12)
1. A radiation-resistant transistor comprises a collector region (4), wherein a base region (2) is generated on the collector region (4), an emitter region A (3) and an emitter region B (6) are inlaid on the base region (2), an alloy layer (8) is processed at the bottom of the collector region (4), a plurality of guard rings (5) are further processed on the base region (2), metal layers (7) are arranged on the emitter region A (3) and the guard rings (5), the upper ends of the base region (2) and the guard rings (5) are sealed through a sealing layer (1), and the doping concentrations of the collector region (4), the base region (2) and the emitter region A (3) are changed in a gradient manner;
the manufacturing process is characterized by comprising the following steps:
1) performing epitaxy to obtain N-type epitaxial wafer with resistivity of 4-6 Ω -cm;
2) oxidizing to form an oxide layer;
3) carrying out primary photoetching to etch the middle part of the oxide layer to form an injection hole;
4) ion implantation is carried out in the hole, and after the base region (2) is formed, activation is carried out, so that the doping concentration of the formed base region is 1E17/cm3-5E18/cm3；
5) Photoetching is carried out on the base region (2) to etch an injection hole of the emitter region A (3);
6) ion implantation is performed at the hole to form a doping concentration of 1E19/cm3-5E19/cm3An emission area A (3);
7) photoetching the bottom of the epitaxial wafer;
8) performing back ion implantation to form a doping concentration of 1E19/cm3-5E19/cm3A collector region (4);
9) an injection hole of the guard ring (5) is formed on the base region (2) through photoetching;
10) performing ion implantation at the collector junction to form a guard ring (5);
11) growing a passivation layer;
12) performing fifth photoetching to reserve the passivation layer of the region except the electrode;
13) carrying out front metallization;
14) carrying out sixth photoetching to reserve the metal layer on the electrode;
15) carrying out alloying;
16) carrying out a thinning process;
17) back side metallization is performed.
2. The radiation-hard transistor of claim 1, wherein: the emitter regions B (6) are a plurality of and are uniformly embedded in the middle of the base region (2).
3. The radiation-hard transistor of claim 1, wherein: the lower end of the guard ring (5) is a doped layer made of the same material as the emitter region A (3), and the upper end of the guard ring (5) extends out of the base region (2) and is connected with the metal layer (7).
4. The radiation-hard transistor of claim 1, wherein: the sealing layer (1) is three layers, namely an oxygen silicon layer, a loose silicon nitride layer and a compact silicon nitride layer from bottom to top.
5. The radiation-hard transistor of claim 4, wherein: the thicknesses of the silicon oxide layer, the loose silicon nitride layer and the dense silicon nitride layer are respectively 800-1300A, 1800-2500A and 5000-7000A.
6. The radiation-hard transistor of any one of claims 1 through 5, wherein: the transistors include NPN type and PNP type.
7. The radiation-hard transistor of claim 6, wherein:
when the NPN transistor forms a P-region base region (2), the energy of boron implantation is 60keV, the implantation angle is 7 degrees, and the P-region of the base region is formed to ensure that the doping concentration is 1E17/cm3-1E19/cm3；
The PNP type transistor forms an N-region base region (2), the energy of phosphorus injection is 100keV, the angle is 7 degrees, and an N-region of the base region is formed, so that the doping concentration of the N-region is 1E17/cm3-5E18/cm3。
8. The radiation-hard transistor of claim 6, wherein:
when the NPN transistor forms an N-region emitter region A (3), the energy of phosphorus implantation is 100keV, the implantation angle is 9 degrees, and the formed doping concentration is 1E17/cm3-5E19/cm3An emission area A (3);
when the PNP transistor forms a P-region emitter A (3), the energy of boron implantation is 90keV, the angle is 7 degrees, and the formed doping concentration is 1E17/cm3-1E19/cm3The emission area a (3).
9. The radiation-hard transistor of claim 6, wherein:
when the NPN type transistor forms a collector region (4), the energy of phosphorus injection is 100keV, the injection angle is 7 degrees, and the formed doping concentration is 1E17/cm3-5E19/cm3A collector region (4);
when the PNP type transistor forms a collector region (4), the energy of boron injection is 60keV, the angle is 7 degrees, and the formed doping concentration is 1E17/cm3-1E19/cm3The collector region (4).
10. The radiation-hard transistor of claim 6, wherein:
when the NPN type transistor forms a guard ring (5), the energy of phosphorus implantation is 100keV, the implantation angle is 7 degrees, and the formed doping concentration is 1E17/cm3-5E19/cm3The guard ring (5);
when the PNP type transistor forms a guard ring (5), the energy of boron implantation is 60keV, the angle is 7 degrees, and the formed doping concentration is 1E17/cm3-1E19/cm3The guard ring (5).
11. The radiation-hard transistor of claim 1, wherein: the oxide layer adopts a dry-wet-dry growth mode, the oxidation time is 120-160 minutes, and the temperature is 1000-1200 ℃.
12. The radiation-hard transistor of claim 1, wherein: and performing rapid thermal annealing activation during each ion implantation, wherein the temperature is 900-1100 ℃, and the time is 10-60S.
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