CN113641609A - Interface circuit, electronic device, and insertion recognition method - Google Patents
Interface circuit, electronic device, and insertion recognition method Download PDFInfo
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- CN113641609A CN113641609A CN202110726885.3A CN202110726885A CN113641609A CN 113641609 A CN113641609 A CN 113641609A CN 202110726885 A CN202110726885 A CN 202110726885A CN 113641609 A CN113641609 A CN 113641609A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
The application discloses an interface circuit, an electronic device and an insertion identification method. The interface circuit includes an interface including a detection pin. And the negative pressure unit is electrically connected with the detection pin. When the interface is not connected with external equipment, the negative voltage unit is used for setting the voltage of the pin of the detection pin as a first voltage, and the first voltage is a negative voltage; when the interface is connected with the external device, the voltage of the pin is set to be the second voltage by the external device. The identification unit is electrically connected with the detection pin; when the pin voltage is set to be a first voltage, the identification unit is used for outputting a first indication signal; when the pin voltage is set to be the second voltage, the identification unit is used for outputting a second indication signal. In the interface circuit, the pin voltage of the detection pin is set to be in a negative voltage state. Therefore, the detection pin becomes an electron collecting region, and the detection pin is not easy to lose electrons and is not easy to oxidize, so that the risk of oxidation corrosion can be greatly reduced.
Description
Technical Field
The present disclosure relates to the field of interface technologies, and in particular, to an interface circuit, an electronic device, and an insertion identification method.
Background
After electronic equipment such as a mobile phone and a tablet is used for a period of time, The problem of interface function failure occurs, for example, an OTG (on The go) interface cannot be identified after being inserted into an OTG line, so that signal transmission cannot be realized, and The use experience of a user is influenced.
The applicant finds that a PIN PIN (detection PIN) for detecting insertion identification is arranged in the interface, and the detection PIN is easily oxidized and corroded due to long-time use, so that the function of the interface is invalid, and the insertion condition of external equipment cannot be identified.
Disclosure of Invention
In order to solve the problem that a PIN of a PIN for detecting insertion identification is oxidized and corroded to cause interface function failure in an interface of electronic equipment, the application provides an interface circuit, the electronic equipment and an insertion identification method, so that the risk of oxidation and corrosion can be greatly reduced, and the interface function failure is avoided.
In a first aspect, the present application provides an interface circuit. The interface circuit includes an interface including a detection pin. And the negative pressure unit is electrically connected with the detection pin. When the interface is not connected with external equipment, the negative voltage unit is used for setting the voltage of the pin of the detection pin as a first voltage, and the first voltage is a negative voltage; when the interface is connected with the external device, the voltage of the pin is set to be the second voltage by the external device. The identification unit is electrically connected with the detection pin; when the pin voltage is set to be a first voltage, the identification unit is used for outputting a first indication signal; when the pin voltage is set to be the second voltage, the identification unit is used for outputting a second indication signal.
In the interface circuit, when the external device is not inserted into the interface (i.e., the interface is not connected to the external device), the negative voltage unit sets the pin voltage of the detection pin to the first voltage in the negative voltage state (it can be understood that the first voltage is the negative voltage output by the negative voltage unit) by using the negative voltage output by itself, so that the first voltage becomes the region with a lower potential. Therefore, the detection pin becomes an electron collection region, so that the detection pin is not easy to lose electrons and is not easy to oxidize, and the risk of oxidation corrosion can be greatly reduced. When an external device is plugged into the interface (i.e., the interface connects the external device), the sense pin is coupled to the external device, in which case the pin voltage of the sense pin is pulled by the external device to a second voltage, e.g., 0V, thereby generating an interrupt.
In order to enable an interrupt generated by the interface circuit to be responded by the processor of the electronic device so that the processor establishes a handshake communication or the like with the external device, the interface circuit is further provided with an identification unit which outputs a first indication signal and a second indication signal having voltage values within a voltage domain of the processor based on the pin voltage of the detection pin. Since the first indication signal and the second indication signal are in the voltage domain of the processor, the processor can respond to the interrupt generated by the first indication signal and the second indication signal, so as to know the insertion action of the external device and establish the actions of handshaking communication and the like between the external device and the processor.
Optionally, the negative pressure unit includes: a first negative pressure source, and a first voltage divider circuit. The first end of the first voltage division circuit is electrically connected with the first negative pressure source, the second end of the first voltage division circuit is electrically connected with an equal potential level, and the voltage division output end of the first voltage division circuit is electrically connected with the detection pin. In this embodiment, the first negative pressure source may output a negative voltage, and the first voltage dividing circuit divides the first negative pressure source, and the obtained first voltage may also be a negative voltage. In other words, the negative voltage unit in this example may output a negative voltage in order to set the pin voltage of the detection pin to the first voltage of the negative voltage state. Further, by adjusting the first voltage dividing circuit, the magnitude of the first voltage can be adjusted so that the first voltage is within the voltage domain of the identification cell. In this case, the identification unit may be responsive to the first voltage and output a first indication signal that the voltage value is within the voltage domain of the processor.
In some embodiments, the identification unit comprises: a reference unit, and a comparator. A reference unit for outputting a reference voltage; the reference voltage is higher than the first voltage and lower than the second voltage. The first input end of the comparator is electrically connected with the reference unit and used for receiving a reference voltage; the second input end of the comparator is electrically connected with the detection pin and used for receiving the pin voltage. When the pin voltage is a first voltage, the output end of the comparator is used for outputting a first indicating signal; when the pin voltage is the second voltage, the output end of the comparator is used for outputting a second indicating signal. In this embodiment, the comparator has a function of comparing inputs of two input terminals. And the comparator may output a voltage of a positive voltage source connected to a power source terminal of the comparator, or 0V, according to the comparison result. It can be seen that since the comparator can output a positive voltage, and the comparator can adjust the voltage domain of the comparator output voltage by connecting a suitable positive voltage source. In other words, the comparator may output the first and second indication signals within a voltage domain of the processor, so that the processor may obtain the insertion action of the external device based on the first and second indication signals.
Optionally, the first input terminal is a non-inverting input terminal of the comparator; the second input terminal is the inverting input terminal of the comparator. In this example, the comparator may output an interrupt from high to low to inform the processor of the insertion of the external device.
Optionally, the first input terminal is an inverting input terminal of the comparator; the second input end is the non-inverting input end of the comparator. In this example, the comparator may output an interrupt from low to high to inform the processor of the insertion of the external device.
Illustratively, the reference unit includes: a second negative pressure source, and a second voltage divider circuit. The first end of the second voltage division circuit is electrically connected with the second negative pressure source, the second end of the second voltage division circuit is electrically connected with an equal potential level, and the voltage division output end of the second voltage division circuit is electrically connected with the detection pin. In this example, the second voltage dividing circuit may divide the negative voltage output by the second negative pressure source so that the reference cell outputs the reference voltage whose voltage value is within the voltage domain of the identification cell. In addition, by adjusting the second voltage dividing circuit, the magnitude of the reference voltage can be adjusted to be higher than the first voltage and lower than the second voltage.
In other embodiments, the identification cell includes an inverting amplification circuit. The input end of the inverting amplifying circuit is electrically connected with the detection pin and used for receiving the voltage of the pin. When the voltage of the pin is a first voltage, the output end of the inverting amplifying circuit is used for outputting a first indicating signal with the polarity opposite to that of the first voltage; when the pin voltage is the second voltage, the output end of the inverting amplifying circuit is used for outputting a second indicating signal with the polarity opposite to that of the second voltage. In this embodiment, the inverting amplifier circuit may perform inverting amplification on the pin voltage of the detection pin, so that the first indication signal and the second indication signal are positive voltages and are within a voltage domain of the processor, and the processor may obtain the insertion action of the external device based on the first indication signal and the second indication signal.
Optionally, the inverting amplifier circuit includes: the circuit comprises an inverting amplifier, a first resistance unit and a second resistance unit. The first end of the first resistance unit is electrically connected with the inverting input end of the inverting amplifier, and the second end of the first resistance unit forms the input end of the inverting amplifying circuit. The non-inverting input of the inverting amplifier is electrically connected to an equipotential potential. The second end of the second resistance unit is electrically connected with the inverting input end of the inverting amplifier. The first end of the second resistance unit is electrically connected with the output end of the inverting amplifier. The output terminal of the inverting amplifier forms the output terminal of the inverting amplification circuit. In this example, by adjusting the ratio of the first resistance unit and the second resistance power supply, the amplification factor of the inverting amplification circuit to the pin voltage of the detection pin may be adjusted, so that the first indication signal and the second indication signal may be in the voltage domain of the processor.
In a second aspect, the present application provides an electronic device. The electronic device comprises a processor and the interface circuit of any of the first aspect. The processor is electrically connected to the interface circuit.
It is to be understood that the electronic device of the second aspect provided above is associated with the interface circuit provided above, and therefore, the beneficial effects achieved by the electronic device can be referred to the beneficial effects of the interface circuit provided above, and are not described herein again.
In a third aspect, the present application provides an insertion recognition method. The interface circuit according to any one of the first aspect, wherein the insertion recognition method includes: the identification unit acquires a pin voltage of the detection pin. When the pin voltage is the first voltage, the identification unit outputs a first indication signal. When the pin voltage is the second voltage, the identification unit outputs a second indication signal.
It can be understood that the insertion identification method of the third aspect provided above is associated with the interface circuit provided above, and therefore, the beneficial effects achieved by the insertion identification method can refer to the beneficial effects in the interface circuit provided above, and are not described herein again.
Drawings
FIG. 1 is a schematic diagram of a detection of an insertion of an electronic device into an external device;
fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an interface circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another interface circuit provided in the embodiment of the present application;
FIG. 5 is a schematic diagram of the pin voltage of the detection pin of the interface circuit shown in FIG. 4;
fig. 6 is a schematic structural diagram of another interface circuit provided in the embodiment of the present application;
FIG. 7 is a schematic diagram of the pin voltage of the detection pin of the interface circuit shown in FIG. 6;
fig. 8 is a schematic structural diagram of another interface circuit provided in the embodiment of the present application;
fig. 9 is a flowchart of an insertion identification method according to an embodiment of the present application.
Detailed Description
Generally, an electronic device such as a mobile phone or a tablet includes an interface for connecting with an external device to implement signal transmission between the electronic device and the external device. However, after the electronic device is used for a period of time, the problem of interface function failure may occur, for example, the OTG (on the go) interface cannot be identified after being inserted into the OTG line, so that signal transmission cannot be realized, and the user experience is affected.
In some embodiments, a PIN (hereinafter referred to as a detection PIN) for detecting insertion identification is provided in the interface, the detection PIN is easily oxidized and corroded due to long-term use, so that the interface function is disabled, the insertion condition of the external device cannot be identified, and the reason for detecting the PIN oxidation and corrosion is related to the principle of insertion identification detection.
Specifically, referring to fig. 1, (a) in fig. 1 shows a state where no external device is inserted into the interface, (b) in fig. 1 shows a state where an external device is inserted into the interface, and (c) in fig. 1 shows levels of the detection pin in two states of (a) in fig. 1 and (b) in fig. 1, respectively. Referring to fig. 1 (c) in conjunction with fig. 1 (a) and (b), when no external device 200 is inserted into the interface 111, the detection pin 111-1 is at a high level, and when an external device 200 is inserted into the interface 111, the detection pin 111-1 is pulled to a low level to generate an interrupt. Based on the interrupt, the processor 120 may be aware of the insertion action of the external device 200, and then the processor 120 controls the action of establishing handshake communication with the external device 200, and the like.
According to the principle of electrode electrolysis, metal with high electrode potential is the anode of the primary battery, and is easy to lose electrons in a corrosive environment and preferentially oxidize and corrode; the metal with low electrode potential is the cathode of the primary battery, and is easy to absorb electrons to carry out reduction reaction, so that the electrons are gathered around the metal, and the electrons are not easy to lose. As can be seen from (c) of fig. 1, when no external device 200 is inserted into the interface 111, the detection pin 111-1 is at a high level, which corresponds to the anode with a high potential in the primary battery. In addition, since the sensing pin 111-1 is not normally connected to the external device 200, the sensing pin 111-1 is exposed to an external environment having corrosiveness for a long time. Therefore, the detection pin 111-1 is easy to lose electrons and is oxidized and corroded, so that an insulating oxide film is formed on the surface of the detection pin 111-1. The presence of the oxide film makes the detection pin 111-1 unable to be pulled to a low level by the external device 200, and thus unable to generate an interrupt to recognize the insertion action of the external device 200.
The interface 111 in the electronic device 100 of fig. 1, in which the above-described problems may occur, is briefly described below.
Illustratively, the interface 111 may be a micro-B interface. In this case, the detection pin 111-1 is generally referred to as an ID pin. The external device 200 may be an electronic product supporting micro-B interface connection, such as an OTG data line, a usb disk, a card reader, and the like.
For example, the interface 111 may be a type-C interface. In this case, the two test pins 111-1 are usually used to support the test identification of the front and back connection of the external device 200, and the two test pins 111-1 are usually referred to as CC1 pin and CC2 pin. The external device 200 may be an electronic product supporting a type-C interface connection, for example, a power adapter, a digital headset, etc.
For example, the interface 111 may also be an OTG interface. In this case, the external device 200 may be an electronic product supporting an OTG interface connection, such as a usb disk, a PAD (PAD), or a mobile phone, which is connected to the OTG interface through an OTG line.
Illustratively, the interface 111 may also be an analog headphone interface. In this case, the external device 200 may be an analog headset.
For example, the interface 111 may also be an SD card slot. In this case, the external device 200 may be an SD card.
Illustratively, the interface 111 may also be a SIM card slot, in which case the external device 200 may be a SIM card.
Illustratively, the interface 111 may also be a pogo pin (pogo pin) interface, in which case the external device 200 may be a keyboard, a mouse, or the like supporting the pogo pin interface connection.
It should be understood that the micro-B interface, the type-C interface, the OTG interface, the analog earphone interface, and the PogoPin interface are not normally connected to the external device 200 and are exposed to a corrosive external environment for a long time. Therefore, the detection pin 111-1 of the interface 111 is susceptible to oxidation corrosion due to loss of electrons when it is in a high-level and corrosive environment for a long time. The SD card slot and the SIM card slot are normally connected to the external device 200, but since the mobile phone is not a completely sealed environment, the environment of the interface 111 may be corrosive, and the above problem may also exist.
The above scenarios are merely some illustrations of the interface 111. It should be understood that, in an environment where the detection pin 111-1 of the interface 111 is in a high level state for a long time and is corrosive, the above-mentioned problem of function failure of the interface 111 may be the interface 111 mentioned in the embodiment of the present application, and the type of the interface 111 is not particularly limited in the embodiment of the present application.
In order to solve the above problem, embodiments of the present application provide an interface circuit. In this interface circuit, when no external device is inserted into the interface, the detection pin of the interface is set to a negative voltage, and the detection pin is set to a region having a low potential, thereby breaking the condition that the detection pin is oxidized and corroded. Particularly, when the detection pin is in a negative voltage state, the periphery of the detection pin is an area where electrons are gathered, and the detection pin is not easy to lose electrons and is not easy to oxidize, so that the risk of oxidation and corrosion can be greatly reduced.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present application, and not all embodiments.
In the embodiments of the present application, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. The term "electrically connected" as used herein to convey an interconnection between different components may include direct connection or indirect connection through other components.
Exemplarily, fig. 2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 may include a mobile phone (mobile phone), a PAD, a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) terminal device, an augmented reality (augmented reality) terminal device, and the like, and has an interface 111 for connecting the external device 200. The embodiment of the present application does not specifically limit the specific form of the electronic device.
As shown in fig. 2, the electronic device 100 may include an interface circuit 110, and a processor 120. The interface circuit 110 is connected to an external device, and acquires a voltage change when the external device is inserted, thereby acquiring an insertion operation of the external device. The processor 120 is electrically connected to the interface circuit 110, and is configured to obtain a voltage change when an external device is inserted from the interface circuit 110, and establish a handshake communication or the like with the external device through the interface circuit 110 after the external device is inserted, so as to implement signal transmission. The interface circuit 110 in the electronic device 100 is described in detail below with reference to fig. 3 to 8.
For example, fig. 3 is a schematic structural diagram of an interface circuit provided in an embodiment of the present application.
In conjunction with fig. 2, as shown in fig. 3, the interface circuit 110 includes an interface 111 for interfacing with an external device. An external device may establish a physical connection with the electronic device 100 by plugging into the interface 111.
In order to sense the insertion of the external device, the interface 111 is provided with a detection pin 111-1 for detecting the insertion of the external device, and the interface circuit 110 further includes a negative voltage unit 112.
The negative voltage unit 112 is a functional unit capable of outputting a negative voltage (i.e., a voltage value lower than 0V), and the negative voltage unit 112 is electrically connected to the detection pin 111-1 and outputs a negative voltage to the detection pin 111-1.
In order to output a negative voltage, in some embodiments, please refer to fig. 4 to 8, the negative voltage unit 112 may include: negative pressure source V1, and first voltage divider circuit 112-1.
The negative pressure source V1 is a power supply capable of outputting a negative voltage-VDD 1. For example, the negative pressure source V1 may be a charge pump, a buck-boost (buck-boost) circuit, or the like.
A first end of the first voltage division circuit 112-1 is electrically connected with a negative pressure source V1; the second end of the first voltage divider circuit 112-1 is electrically connected to an equal potential, which is usually ground GND, and the present example is described with the equal potential as ground GND, which is not described again; the voltage dividing output terminal of the first voltage dividing circuit 112-1 is electrically connected to the detection pin 111-1, and is used for dividing the negative voltage-VDD 1 output by the negative voltage source V1, and outputting a first voltage having a voltage value within the voltage domain of the identification cell, such as-1.8V.
In the embodiment of the present application, the first voltage divider circuit 112-1 may include a resistor R1 and a resistor R2. The first terminal of the resistor R1 forms the first terminal of the first voltage divider circuit 112-1 and is electrically connected to the negative pressure source V1. The second terminal of the resistor R2 forms the second terminal of the first voltage divider circuit 112-1 and is electrically connected to ground GND. The second terminal of the resistor R1 is electrically connected to the first terminal of the resistor R2 to form a voltage dividing output terminal of the first voltage dividing circuit 112-1 for outputting a negative voltage.
It should be understood that the resistor R1 and the resistor R2 in the first voltage divider circuit 112-1 may be alternatively implemented by a plurality of resistors connected in series and/or in parallel, which is not specifically limited in this embodiment of the present application. It should also be understood that in other embodiments, if the voltage output by the negative pressure source V1 is within the voltage domain of the identification unit, the negative pressure unit 112 may not be provided with the first voltage dividing circuit 112-1.
Based on this, when an external device is not inserted into the interface 111 (i.e., the interface 111 is not connected to an external device), the negative voltage unit 112 sets the pin voltage U1 of the detection pin 111-1 to the first voltage in the negative voltage state (it is understood that the first voltage is the negative voltage output by the negative voltage unit 112) by the negative voltage output by itself, so that the first voltage is in the region with a lower potential. Therefore, the detection pin 111-1 becomes an electron collection region, so that the detection pin 111-1 is not easy to lose electrons and is not easy to oxidize, and the risk of oxidation and corrosion can be greatly reduced. When an external device is plugged into the interface 111 (i.e., the interface 111 is connected to an external device), the detection pin 111-1 is coupled to the external device, in which case the pin voltage U1 of the detection pin 111-1 is pulled to a second voltage, for example, 0V, by the external device, thereby generating an interrupt to inform the processor 120 of the plugging action of the external device, to facilitate the establishment of handshaking communication between the processor 120 and the external device, and so on.
It can be seen that the detection pin 111-1 has a different pin voltage U1 when the external device is in both the unplugged and plugged-in states. Therefore, the pin voltage U1 of the detection pin 111-1 can represent the insertion condition of the external device, and the insertion condition of the external device can be known by acquiring, identifying and distinguishing the pin voltage U1 of the detection pin 111-1.
Considering that the pin voltage U1 of the detection pin 111-1 is in a negative voltage state when the external device is not plugged in, and is not in the voltage domain of the processor 120 in fig. 2 (the voltage domain of the processor 120 is a positive voltage, that is, the voltage value is greater than or equal to 0V), the processor 120 cannot respond thereto to obtain the plugging condition of the external device. Therefore, in order to enable the processor 120 to know the insertion condition of the external device based on the pin voltage U1 of the detection pin 111-1, referring to fig. 3, the interface circuit 110 further includes an identification unit 113.
The identification unit 113 is electrically connected to the detection pin 111-1, and is configured to obtain a pin voltage U1 of the detection pin 111-1, and output a first indication signal indicating that an external device is not inserted when the pin voltage U1 is set to a first voltage; when the pin voltage U1 is set to the second voltage, a second indication signal indicating insertion of an external device is output.
It should be noted that the first indication signal and the second indication signal output by the identification unit 113 are within the voltage domain of the processor 120, and therefore can be responded by the processor 120. Based on this, the processor 120 may be electrically connected to the recognition unit 113, may obtain a first indication signal and a second indication signal for indicating the insertion condition of the external device, and may obtain the insertion action of the external device based on the first indication signal and the second indication signal.
As shown in fig. 4 and 6, the recognition unit 113 may optionally include a reference unit 113-1 and a comparator 113-2.
The reference unit 113-1 is configured to output a reference voltage U2, where the reference voltage U2 is higher than the first voltage and lower than the second voltage. Continuing with the above example, the first voltage is-1.8V, the second voltage is 0V, and the reference voltage U2 can be any voltage greater than-1.8V and less than 0V, such as-1V.
For example, as shown in fig. 4 and 6, the reference unit 113-1 may include a negative pressure source V1 (i.e., a second negative pressure source) and a second voltage dividing circuit 113-11. The first end of the second voltage dividing circuit 113-11 is electrically connected to the negative pressure source V1, the second end of the second voltage dividing circuit 113-11 is electrically connected to the ground GND, and the voltage dividing output end of the second voltage dividing circuit 113-11 is electrically connected to the comparator 113-2. It should be understood that fig. 4 and 6 illustrate a case where the reference unit 113-1 and the negative pressure unit 112 may share the same negative pressure source, i.e., the second negative pressure source and the first negative pressure source are the negative pressure source V1. In other embodiments, the reference unit 113-1 and the negative pressure unit 112 may also use different negative pressure sources, which is not particularly limited in this embodiment.
In this example, the second voltage divider circuit 113-11 may include a resistor R3 and a resistor R4. The first terminal of the resistor R3 forms the first terminal of the second voltage divider 113-11 and is electrically connected to the negative pressure source V1. The second terminal of the resistor R4 forms the second terminal of the second voltage divider 113-11 and is electrically connected to ground GND. The second terminal of the resistor R3 is electrically connected to the first terminal of the resistor R4 to form a voltage dividing output terminal of the second voltage dividing circuit 113-11 for outputting the reference voltage U2. By adjusting the ratio of the resistor R3 and the resistor R4, the value of the reference voltage U2 can be adjusted to be between the first voltage and the second voltage.
It should be understood that the resistor R3 and the resistor R4 in the second voltage divider circuit 113-11 may alternatively be implemented by a plurality of resistors connected in series and/or in parallel, and this is not particularly limited in this embodiment of the present application. It should also be understood that in other embodiments, the reference unit 113-1 may not be provided with the second voltage divider circuit 113-11 if the voltage that the negative pressure source V1 can output is within the voltage domain of the comparator 113-2.
The comparator 113-2 has a power supply terminal, a ground terminal, and two input terminals. The power supply end is electrically connected to a positive voltage source V2, the positive voltage source V2 is a power supply capable of outputting a positive voltage (i.e., a voltage value is greater than 0V), for example, the positive voltage source V2 may be implemented by a low dropout regulator (LDO), a Boost (Buck) circuit, a Boost (Boost) circuit, a charge pump, and the like; the grounding end is electrically connected with the ground GND; the two input terminals are a non-inverting input terminal (+) and an inverting input terminal (-) respectively, and are used for receiving two inputs to be compared. The comparator 113-2 may compare the inputs of the two input terminals and output the voltage of the positive voltage source V2 when the voltage value of the non-inverting input terminal (+) is greater than the voltage value of the inverting input terminal (-); and outputs 0V when the voltage value of the non-inverting input terminal (+) is less than the voltage value of the inverting input terminal (-). As can be seen, the comparator 113-2 can output a positive voltage and by selecting the appropriate positive voltage source V2, the voltage domain output by the comparator 113-2 can be adjusted.
For the purposes of this application, a first input of comparator 113-2 is electrically connected to reference cell 113-1 for receiving reference voltage U2; a second input terminal of the comparator 113-2 is electrically connected to the detection pin 111-1 for receiving a pin voltage U1; an output end out of the comparator 113-2, configured to output a first indication signal when the pin voltage U1 is a first voltage; when the pin voltage U1 is the second voltage, a second indication signal is output.
It should be appreciated that, as shown in FIG. 4, in some examples, the first input of comparator 113-2 may be the non-inverting input (+) of comparator 113-2 and the second input of comparator 113-2 may be the inverting input (-) of comparator 113-2. That is, the non-inverting input terminal (+) of the comparator 113-2 is electrically connected to the reference unit 113-1 for receiving the reference voltage U2; the inverting input (-) of the comparator 113-2 is electrically connected to the sense pin 111-1 for receiving the pin voltage U1.
In the interface circuit 110 shown in fig. 4, since the reference voltage U2 is higher than the first voltage and lower than the second voltage, when the pin voltage U1 is the first voltage (i.e., no external device is inserted), the non-inverting input terminal (+) of the comparator 113-2 is the reference voltage U2, the inverting input terminal (-) of the comparator 113-2 is the first voltage, and the voltage at the non-inverting input terminal (+) is higher than the voltage at the inverting input terminal (-), in this case, the output terminal out of the comparator 113-2 outputs the voltage VDD2 of the positive voltage source V2, i.e., the voltage VDD2 of the positive voltage source V2 as the first indication signal. When the pin voltage U1 is the second voltage (i.e., the external device is plugged in), the non-inverting input terminal (+) of the comparator 113-2 is the reference voltage U2, the inverting input terminal (-) of the comparator 113-2 is the second voltage, and the voltage of the non-inverting input terminal (+) is lower than that of the inverting input terminal (-), in which case the output terminal out of the comparator 113-2 outputs 0V, i.e., the second indication signal is 0V.
As shown in FIG. 6, in other examples, the first input of comparator 113-2 may be the inverting input (-) of comparator 113-2 and the second input of comparator 113-2 may be the non-inverting input (+) of comparator 113-2. That is, the inverting input (-) of the comparator 113-2 is electrically connected to the reference cell 113-1 for receiving the reference voltage U2; the non-inverting input (+) of the comparator 113-2 is electrically connected to the sense pin 111-1 for receiving the pin voltage U1.
In the interface circuit 110 shown in fig. 6, since the reference voltage U2 is higher than the first voltage and lower than the second voltage, when the pin voltage U1 is the first voltage (i.e., no external device is inserted), the inverting input terminal (-) of the comparator 113-2 is the reference voltage U2, the non-inverting input terminal (+) of the comparator 113-2 is the first voltage, and the voltage of the non-inverting input terminal (+) is lower than that of the inverting input terminal (-), in which case the output terminal out of the comparator 113-2 outputs 0V, i.e., the first indication signal is 0V. When the pin voltage U1 is the second voltage (i.e., the external device is plugged in), the inverting input terminal (-) of the comparator 113-2 is the reference voltage U2, the non-inverting input terminal (+) of the comparator 113-2 is the second voltage, and the voltage at the non-inverting input terminal (+) is higher than that at the inverting input terminal (-), in which case the output terminal out of the comparator 113-2 outputs the voltage VDD2 of the positive voltage source V2, i.e., the second indication signal is the voltage VDD2 of the positive voltage source V2.
It can be seen that, in the interface circuit 110 shown in fig. 4 and fig. 6, the comparator 113-2 compares the pin voltage U1 of the detection pin 111-1 with the reference voltage U2, and in accordance with the type selection of the positive voltage source V2, the comparator 113-2 can output the first indication signal and the second indication signal within the voltage domain of the processor 120, so that the processor 120 can obtain the insertion action of the external device based on the first indication signal and the second indication signal.
As can be seen by comparing fig. 4 and 6, the interrupts generated by comparator 113-2 are diametrically opposed. Specifically, as shown in fig. 5, in the interface circuit 110 shown in fig. 4, when the pin voltage U1 is the first voltage (i.e. the external device 200 in fig. 1 is not inserted), the comparator 113-2 outputs the first indication signal as the voltage VDD2 (high level) of the positive voltage source V2; when the pin voltage U1 is the second voltage (i.e., the external device is plugged in), the comparator 113-2 outputs a second indication signal of 0V (low), thereby generating an interrupt from high to low. As shown in fig. 7, in the interface circuit 110 shown in fig. 6, when the pin voltage U1 is the first voltage (i.e., the external device is not plugged in), the comparator 113-2 outputs the first indication signal as 0V (low level); when the pin voltage U1 is the second voltage (i.e., the external device is plugged in), the comparator 113-2 outputs a second indication signal as the voltage VDD2 (high level) of the positive voltage source V2, thereby generating an interrupt from low level to high level. In particular embodiments, the interrupt scheme of using the interface circuit 110 of fig. 4 or fig. 6 may be selected according to the interrupt triggering mechanism of the processor 120.
In other embodiments of the present application, as shown in FIG. 8, the recognition unit 113 may include an inverting amplification circuit 113-3.
The input end of the inverting amplifying circuit 113-3 is electrically connected to the detection pin 111-1 and is used for receiving a pin voltage U1; the output terminal of the inverting amplifier circuit 113-3 is used for outputting a first indication signal with a polarity opposite to that of the first voltage when the pin voltage U1 is the first voltage, and outputting a second indication signal with a polarity opposite to that of the second voltage when the pin voltage U1 is the second voltage.
In this embodiment, the inverting amplifier circuit 113-3 may perform inverting amplification on the pin voltage U1 of the detection pin 111-1, so that the first indication signal and the second indication signal are positive voltages and are within a voltage domain of the processor 120, so that the processor 120 may obtain an insertion action of an external device based on the first indication signal and the second indication signal.
Illustratively, as shown in fig. 8, the inverting amplifier circuit 113-3 may include an inverting amplifier 113-31, a first resistance unit, and a second resistance unit. In the embodiment of the present application, the first resistor unit is the resistor R5, and the second resistor unit is the resistor R6.
Referring to fig. 8, the inverting amplifiers 113-31 have a positive power supply terminal, a negative power supply terminal, a non-inverting input terminal (+), and an inverting input terminal (-). Wherein, the power supply end is electrically connected with a positive voltage source V3; the negative power supply terminal is electrically connected with a negative pressure source V4. Specific definitions and implementations of the positive pressure source V3 and the negative pressure source V4 may refer to specific definitions and implementations of the positive pressure source V2 and the negative pressure source V1, respectively, and will not be described herein again.
Wherein the first terminal of the resistor R5 is electrically connected to the inverting input (-) of the inverting amplifier 113-31, and the second terminal of the resistor R5 forms the input of the inverting amplifier 113-3 for receiving the pin voltage U1.
The non-inverting input (+) of the inverting amplifier 113-31 may be electrically connected to ground GND through a resistor R7. In other embodiments, the non-inverting input (+) of the inverting amplifier 113-31 may also be electrically connected to the ground GND, which is not particularly limited in the embodiments of the present application.
The first terminal of the resistor R6 is electrically connected to the inverting input (-) of the inverting amplifier 113-31, and the second terminal of the resistor R6 is electrically connected to the output out of the inverting amplifier 113-31. The output terminal out of the inverting amplifier 113-31 forms the output terminal of the inverting amplifier circuit 113-3.
In this example, by adjusting the ratio of the resistor R5 to the resistor R6, the amplification factor of the inverting amplifier circuit 113-3 to the pin voltage U1 of the detection pin 111-1 can be adjusted so that the first indication signal and the second indication signal are within the voltage domain of the processor 120.
It should be understood that, in other embodiments, the first resistance unit and the second resistance unit may be alternatively implemented by a plurality of resistors connected in series and/or in parallel, which is not specifically limited in this embodiment of the application.
The embodiment of the application also provides an insertion identification method. The method may be applied to an interface circuit as shown in any one of fig. 3 to 8. As shown in fig. 9, the insertion recognition method includes:
s901, the identification unit acquires the pin voltage of the detection pin.
S902, when the pin voltage is a first voltage, the identification unit outputs a first indication signal, and the first indication signal is used for indicating that the external device is not inserted into the interface.
And S903, when the pin voltage is the second voltage, the identification unit outputs a second indication signal, and the second indication signal is used for indicating that the external equipment is inserted into the interface.
It should be noted that, in the insertion identification method shown in fig. 9, specific implementation of the identification unit obtaining the pin voltage of the detection pin and the identification unit outputting different indication signals based on the pin voltage of the detection pin may refer to specific implementation of the interface circuits shown in fig. 3 to fig. 8, and details are not repeated here.
The above is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An interface circuit, comprising:
an interface; the interface comprises a detection pin;
the negative pressure unit is electrically connected with the detection pin; when the interface is not connected with external equipment, the negative voltage unit is used for setting the pin voltage of the detection pin as a first voltage, and the first voltage is a negative voltage; when the interface is connected with the external equipment, the pin voltage is set to a second voltage by the external equipment;
the identification unit is electrically connected with the detection pin; when the pin voltage is set to be the first voltage, the identification unit is used for outputting a first indication signal; when the pin voltage is set to the second voltage, the identification unit is used for outputting a second indication signal.
2. The interface circuit of claim 1, wherein the negative voltage unit comprises:
a first negative pressure source and a first voltage dividing circuit; wherein the content of the first and second substances,
the first end of the first voltage division circuit is electrically connected with the first negative pressure source, the second end of the first voltage division circuit is electrically connected with an equal potential level, and the voltage division output end of the first voltage division circuit is electrically connected with the detection pin.
3. Interface circuit according to claim 1 or 2, characterized in that the identification unit comprises: a reference unit and a comparator;
the reference unit is used for outputting a reference voltage; wherein the reference voltage is higher than the first voltage and lower than the second voltage;
the first input end of the comparator is electrically connected with the reference unit and used for receiving the reference voltage;
the second input end of the comparator is electrically connected with the detection pin and used for receiving the pin voltage;
when the pin voltage is the first voltage, the output end of the comparator is used for outputting the first indication signal;
when the pin voltage is the second voltage, the output end of the comparator is used for outputting the second indication signal.
4. The interface circuit of claim 3, wherein the first input is a non-inverting input of the comparator;
the second input terminal is an inverting input terminal of the comparator.
5. The interface circuit of claim 3, wherein the first input is an inverting input of the comparator;
the second input end is a non-inverting input end of the comparator.
6. Interface circuit according to claim 4 or 5, characterized in that the reference unit comprises:
a second negative pressure source and a second voltage dividing circuit; wherein the content of the first and second substances,
the first end of the second voltage division circuit is electrically connected with the second negative pressure source, the second end of the second voltage division circuit is electrically connected with an equal potential level, and the voltage division output end of the second voltage division circuit is electrically connected with the detection pin.
7. Interface circuit according to claim 1 or 2, characterized in that the identification unit comprises an inverting amplification circuit;
the input end of the inverting amplifying circuit is electrically connected with the detection pin and used for receiving the voltage of the pin;
when the pin voltage is the first voltage, the output end of the inverting amplifying circuit is used for outputting the first indicating signal with the polarity opposite to that of the first voltage;
and when the pin voltage is the second voltage, the output end of the inverting amplifying circuit is used for outputting the second indicating signal with the polarity opposite to that of the second voltage.
8. The interface circuit of claim 7, wherein the inverting amplification circuit comprises:
the circuit comprises an inverting amplifier, a first resistance unit and a second resistance unit;
a first end of the first resistance unit is electrically connected with an inverting input end of the inverting amplifier, and a second end of the first resistance unit forms an input end of the inverting amplifier circuit;
the non-inverting input end of the inverting amplifier is electrically connected to an equipotential potential;
the second end of the second resistance unit is electrically connected with the inverting input end of the inverting amplifier; the first end of the second resistance unit is electrically connected with the output end of the inverting amplifier;
the output end of the inverting amplifier forms the output end of the inverting amplifying circuit.
9. An electronic device comprising a processor, and an interface circuit as claimed in any one of claims 1 to 8;
the processor is electrically connected to the interface circuit.
10. An insertion recognition method applied to the interface circuit according to any one of claims 1 to 8, the insertion recognition method comprising:
the identification unit acquires the pin voltage of the detection pin;
when the pin voltage is the first voltage, the identification unit outputs a first indication signal;
when the pin voltage is the second voltage, the identification unit outputs a second indication signal.
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| CN202110726885.3A CN113641609B (en) | 2021-06-29 | 2021-06-29 | Interface circuit, electronic device, and insertion recognition method |
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| CN202110726885.3A CN113641609B (en) | 2021-06-29 | 2021-06-29 | Interface circuit, electronic device, and insertion recognition method |
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