CN112817896A - Type-C interface protection circuit, method and device, storage medium and electronic equipment - Google Patents
Type-C interface protection circuit, method and device, storage medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application discloses Type-C interface protection circuit includes: the device comprises a Type-C interface, a comparator, a processor, a first voltage source and a second voltage source; the Type-C interface comprises a grounding pin, and the processor comprises a GPIO pin; the processor is used for stopping electrifying the Type-C interface when the GPIO pin receives the low level signal or electrifying the Type-C interface when the GPIO pin receives the high level signal. Adopt this application embodiment can reduce the probability that electrochemical corrosion takes place for the Type-C interface, effectively improve the life and the operational reliability of Type-C interface.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a Type-C interface protection circuit, a method, a device, a storage medium and electronic equipment.
Background
With the development of electronic technology and communication technology, the mobile communication industry has developed rapidly, and mobile terminals have become necessary for people to work and live in daily life. The Type-C interface supports double-sided insertion of the interface, the problem that the front side and the back side need to be distinguished when the previous interface is inserted is formally solved, and the front side and the back side can be inserted. And meanwhile, the data line matched with the data line is thinner and lighter. In the prior art, a periodic square wave with the amplitude of about 3V is always polled on the Type-C interface under a normal condition so as to detect whether the Type-C interface is in an insertion state. The user can produce sweat, water stain etc. unavoidably during Type-C interface when using for a long time, and these sweat, water stain have just become electrochemical corrosion's electrolyte, and metal PIN foot can take place electrochemical reaction when Type-C interface is gone up electricity, and the redox reaction of metal connector is accelerated, leads to metal PIN foot to corrode.
In view of the above, the present application proposes a method to solve the above problems or at least to solve some of the problems.
Disclosure of Invention
The embodiment of the application provides a Type-C interface protection circuit, a method, a device, a storage medium and electronic equipment, which can reduce the probability of electrochemical corrosion of a Type-C interface and effectively improve the service life and the service reliability of the Type-C interface. The technical scheme is as follows:
in a first aspect, the present application provides a Type-C interface protection circuit, including: the device comprises a Type-C interface, a comparator, a processor, a first voltage source and a second voltage source; the Type-C interface comprises a grounding pin, and the processor comprises a GPIO pin;
the non-inverting input end of the comparator is connected with the first voltage source, the inverting input end of the comparator is respectively connected with the grounding pin and the second voltage source, and the output end of the comparator is connected with the GPIO pin of the processor; when the Type-C interface is in an inserted state, the grounding pin is grounded so as to ground the inverting input terminal of the comparator, and when the Type-C interface is in an unplugged state, the grounding pin is suspended so as to load a second voltage signal output by the second voltage source to the inverting input terminal of the comparator;
the first voltage source is used for providing a first voltage signal to a non-inverting input end of the comparator; wherein a voltage value of the second voltage signal is greater than a voltage value of the first voltage signal;
the comparator is used for detecting the first voltage signal through the non-inverting input end and detecting the second voltage signal through the inverting input end; outputting a high level signal when the voltage value of the non-inverting input end is larger than that of the inverting input end, and outputting a low level signal when the voltage value of the non-inverting input end is smaller than that of the inverting input end;
the processor is used for stopping electrifying the Type-C interface when the GPIO pin receives the low level signal or electrifying the Type-C interface when the GPIO pin receives the high level signal.
In one or more possible embodiments, the present application further includes: a voltage limiting circuit;
the second voltage source is connected with the second end of the comparator through the voltage limiting circuit.
In one or more possible embodiments, the voltage limiting circuit includes: a first resistor and a second resistor;
the first end of the first resistor is connected with the second voltage source, the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded;
the grounding pin is connected with the second end of the first resistor.
In one or more possible embodiments, the present application further includes: an application processor and a power-on power supply;
the application processor is respectively connected with the processor and the power-on power supply;
the processor is used for sending a power-off instruction to the application processor when the low-level signal is received through the GPIO pin, or sending a power-on instruction to the application processor when the high-level signal is received;
the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface, and the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface.
In a second aspect, the present application provides a Type-C interface protection method, which is applied to the Type-C interface protection circuit according to the first aspect;
the method comprises the following steps:
receiving a level signal from the comparator through the GPIO pin;
when the level signal is the low level signal, stopping electrifying the Type-C interface;
and when the level signal is the high level signal, powering on the Type-C interface.
In one or more possible embodiments, the stopping the power on for the Type-C interface when the level signal is the low level signal includes:
when the level signal is the low level signal, sending a power-off instruction to an application processor; the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface;
when the level signal is the high level signal, for Type-C interface power-up includes:
when the level signal is the high level signal, sending a power-on instruction to an application processor; the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface.
In one or more possible embodiments, the present application further includes:
when the level signal is the high level signal, a first group of idle pins in the Type-C interface are connected to a power supply pin in the charging management chip, and a second group of idle pins in the Type-C interface is grounded.
In a third aspect, the present application provides a Type-C interface protection device, where the device includes:
the receiving module receives a level signal from the comparator through the GPIO pin;
the stopping module stops electrifying the Type-C interface when the level signal is the low level signal;
and the power-on module is used for powering on the Type-C interface when the level signal is the high level signal.
In a fourth aspect, the present application proposes a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the method steps of any one of the second aspects.
In a fifth aspect, the present application provides an electronic device, including any one of the Type-C interface protection circuits described in the first aspect, and applying any one of the Type-C interface protection methods described in the second aspect.
The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:
whether the grounding pin of the Type-C interface is grounded or not is detected through the comparator, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judgment mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a Type-C interface protection circuit provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of another Type-C interface protection circuit provided in an embodiment of the present application;
fig. 3 is a schematic flowchart of a Type-C interface protection method provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a Type-C interface protection device provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it is noted that, unless explicitly stated or limited otherwise, "including" and "having" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
The present application will be described in detail with reference to specific examples.
Electronic equipment, which may be understood as equipment having a Radio frequency port and a communication function, includes, but is not limited to, a Mobile Station (MS), a Mobile Terminal (Mobile Terminal), a Mobile phone (Mobile Telephone), a handset (handset), a portable device (portable equipment), and the like, where the Terminal equipment may communicate with one or more core networks via a Radio Access Network (RAN), for example, the Terminal equipment may be a Mobile phone (or referred to as a "cellular" phone), a computer with a wireless communication function, and the Terminal equipment may also be a portable, pocket, hand-held, computer-embedded or vehicle-mounted Mobile device or equipment.
As shown in fig. 1, a schematic structural diagram of a Type-C interface protection circuit provided in an embodiment of the present application includes: a Type-C interface (not shown), a comparator U1, a processor 104, a first voltage source 101, and a second voltage source 102. The Type-C interface includes a ground pin 103, and the processor 104 includes a GPIO pin.
The Type-C interface can be understood as one of the external standards of Universal Serial Bus (USB), and USB is a Serial Bus standard for connecting a computer system and external devices, and is also a technical specification of an input/output interface, and is widely applied to information communication products such as personal computers and mobile devices. On a mobile phone or other terminals, a Type-C interface is mainly welded on a flexible circuit board or a PCB through an SMT technology, and the charging or data transmission function of the mobile phone is realized through connecting a data line. It can be understood that the Type-C interface is used with the Type-C connecting line in a matched manner, and the following Type-C interface is in an insertion state and is normally connected with the Type-C connecting line, in other words, the Type-C interface is in a working state.
It should be noted that the Type-C interface includes 12 pins, including 4 ground pins, and the ground pin 103 shown in fig. 1 is any one of all ground pins of the Type-C interface. When the Type-C interface is in an insertion state, the grounding pin 103 is grounded through the grounding chip of the Type-C connecting line, and when the Type-C interface is in a non-insertion state, the grounding pin 103 is suspended.
The processor 104 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 104 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. It is understood that the processor 104 includes a General-purpose input/output (GPIO) interface, i.e. a General-purpose source I/O port, and at least one General-purpose IO port control register and a General-purpose I/O port data register for controlling the detection of signals of the GPIO interface.
The comparator U1 is understood to output an output value after comparing at least two input values based on the comparison op-amp rule. In the embodiment of the present application, the non-inverting input terminal of the comparator U1 is connected to the first voltage source 101, the inverting input terminal of the comparator U1 is connected to the ground pin 103 and the second voltage source 102, respectively, and the output terminal of the comparator U1 is connected to the GPIO pin of the processor 104.
A first voltage source 101 for providing a first voltage signal E to a non-inverting input of a comparator U11. A second voltage source 102 for providing a second voltage signal E to the inverting input of the comparator U12. In the present application, the first voltage signal E1Voltage value of < the second voltage signal E2Preferably, the first voltage signal E1Has a voltage value of 0.2V, a second voltage signal E2The voltage value of (1.8) is avoided, so that the excessive voltage value is loaded on the grounding pin 103, and the electrochemical corrosion on the grounding pin 103 is avoided.
The following illustrates the working principle of the present application: the first voltage source 101 outputs a first voltage signal E1And applies the first voltage signal E1The non-inverting input end of the comparator U1 is loaded; when the Type-C interface is in a non-plugged state, i.e. the ground pin 103 is in a floating state, the second voltage source 102 outputs a second voltage signal E2And applies a second voltage signal E2The inverting input end of the comparator U1 is loaded; the comparator U1 detects the voltage value of the non-inverting input terminal and the voltage value of the inverting input terminal, the voltage value of the non-inverting input terminal is smaller than the voltage value of the inverting input terminal, and outputs a low level signal to the GPIO pin of the processor 104; the processor 104 receives the low level signal through the GPIO pin and decodes the data register based on the general purpose I/O portAfter the low-level signal is analyzed, the Type-C interface is judged to be in a non-insertion state at the moment, the power-on of the Type-C interface is stopped, namely, the sending of a polling square wave to a CC1/CC2 interface of the Type-C interface is stopped; when the Type-C interface is in an insertion state, the grounding pin 103 is grounded through a grounding chip of the Type-C connecting line; the inverting input terminal of the comparator U1 is grounded, that is, the voltage value of the inverting input terminal of the comparator U1 is 0, and when the voltage value of the non-inverting input terminal is detected to be greater than the voltage value of the inverting input terminal, the comparator U1 outputs a high-level signal; the processor 104 receives the high level signal through the GPIO pin, and after analyzing the high level signal based on the general I/O port data register, determines that the Type-C interface is in an inserted state at this time, and normally powers on the Type-C interface, so that the Type-C connection line is normally paired with the electronic device.
In one embodiment, the present application further comprises: an application processor and a power-on power supply. The application processor is respectively connected with the processor and the power-on power supply. In this embodiment, the processor is configured to send a power-down instruction to the application processor when receiving a low-level signal through the GPIO pin, or send a power-up instruction to the application processor when receiving a high-level signal; the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface, and the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface. It will be appreciated that the application processor and the processor 103 described above are packaged on different chips, for example, the application processor is integrated on the overall processor chip of the electronic device and the processor 103 is packaged on a processor chip of the Type-C interface. By adopting the embodiment of the application, the processor and the application processor are separately arranged, and the requirement of a user for individually customizing the electronic equipment is met.
In another embodiment, the application processor and the processor are packaged on the same chip, and the processor sends a power-on instruction or a power-off instruction to the power-on power supply so that the power-on power supply powers on the Type-C interface. By adopting the embodiment of the application, the application processor and the processor are packaged on the same chip, which is beneficial to improving the integration of the processor and saving the installation space of the electronic equipment.
The comparator is used for detecting whether the grounding pin of the Type-C interface is grounded or not, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judging mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
As shown in fig. 2, a schematic structural diagram of another Type-C interface protection circuit provided in the embodiment of the present application includes: a voltage limiting circuit 201, a Type-C interface (not shown), a comparator U1, a processor 104, a first voltage source 101, and a second voltage source 102. The Type-C interface includes a ground pin 103, the processor 104 includes a GPIO pin, and the voltage limiting circuit 201 includes a first resistor R1 and a second resistor R2.
The first terminal of the first resistor R1 is connected to the second voltage source 102, the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is grounded, and the ground pin 103 is connected to the second terminal of the first resistor R1.
And the voltage limiting circuit 201 is used for reducing the voltage value of the voltage loaded to the inverting input terminal of the comparator U1 by the second voltage source 102, so that the voltage value of the inverting input terminal of the comparator U1 is only slightly larger than that of the non-inverting input terminal when the Type-C interface is in the insertion state. For example, the first resistance is 100k Ω, the second resistance is 20k Ω, and the first voltage signal E output by the first voltage source 1011Is 0.2V, and the second voltage signal E output by the second voltage source 1022The voltage value of (1.8) V; voltage value U of non-inverting input terminal of comparator U110.2V, the voltage value U of the inverting input terminal of the comparator U12It was 0.3V.
The application has at least the following advantages: the voltage value loaded to the inverting input end of the comparator by the second voltage source is reduced through the voltage limiting circuit, the voltage value loaded to the grounding pin by the second voltage source is reduced, the comparator is prevented from being damaged when the second voltage source works abnormally, and the degree of electrochemical corrosion on the grounding pin is reduced through reducing the voltage.
The comparator is used for detecting whether the grounding pin of the Type-C interface is grounded or not, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judging mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
As shown in fig. 3, a flow chart of a Type-C interface protection method provided for the embodiment of the present application is a flowchart, which can be implemented by a computer program and can run on an image source tracking device based on von neumann architecture. The computer program may be integrated into the application or may run as a separate tool-like application.
Specifically, the Type-C interface protection method comprises the following steps:
step S301: and receiving the level signal from the comparator through the GPIO interface.
The Type-C interface protection method is suitable for a Type-C interface protection circuit shown in fig. 1, and the processor may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. It is understood that the processor includes a General-purpose input/output (GPIO) interface, i.e. a General-purpose source I/O port, and at least one General-purpose IO port control register and General-purpose I/O port data register for controlling the detection of signals of the GPIO interface.
In the embodiment, the processor receives the level signal sent by the comparator through the GPIO interface, and the level signal is divided into a low level signal and a high level signal.
Step S302: and when the level signal is a low level signal, stopping electrifying the Type-C interface.
The processor generates a power-off instruction based on a low level signal when receiving the low level signal through instruction data stored in the general I/O port data register, and sends the power-off instruction to the power-on power supply based on direction data stored in the general IO port control register, and the power-on power supply is instructed to stop being powered on by a CC1/CC2 pin of the Type-C interface.
Step S303: when the level signal is a high level signal, the Type-C interface is powered on.
The processor generates a power-on instruction based on a high level signal when receiving the high level signal through instruction data stored in the general I/O port data register, sends the power-on instruction to a power-on power supply based on direction data stored in the general IO port control register, and indicates that the power-on power supply is powered on at a pin CC1/CC2 of a Type-C interface.
The following is the working principle of the application: the first voltage source outputs a first voltage signal E1And applies the first voltage signal E1The non-inverting input end of the comparator U1 is loaded; when the Type-C interface is in a non-insertion state, namely the grounding pin is in a suspension state, the second voltage source outputs a second voltage signal E2And applies a second voltage signal E2The inverting input end of the comparator U1 is loaded; the comparator U1 detects the voltage value of the non-inverting input end and the voltage value of the inverting input end, the voltage value of the non-inverting input end is smaller than the voltage value of the inverting input end, and a low level signal is output to the GPIO pin of the processor; the processor receives the low level signal through the GPIO pin, and after the low level signal is analyzed based on the general I/O port data register, the processor judges that the Type-C interface is in a non-insertion state at the moment, stops electrifying the Type-C interface, and stops sending a polling square wave to the CC1/CC2 interface of the Type-C interface; when the Type-C interface is in an inserting state, the grounding pin is grounded through a grounding chip of the Type-C connecting line; the inverting input terminal of the comparator U1 is grounded, that is, the voltage value of the inverting input terminal of the comparator U1 is 0, and when the voltage value of the non-inverting input terminal is detected to be greater than the voltage value of the inverting input terminal, the comparator U1 outputs a high-level signal; the processor receives the high level signal through the GPIO pin, and after the high level signal is analyzed based on the general I/O port data register, the processor judges that the Type-C interface is in an insertion state at the moment, so that the Type-C interface is normally powered onSo that the Type-C connecting line is normally paired with the electronic equipment.
In one embodiment, this embodiment further includes: an application processor and a power-on power supply. When the level signal is a low level signal in step S301, the power on of the Type-C interface is stopped, including: when the level signal is a low level signal, sending a power-off instruction to the application processor; and the power-off instruction is used for indicating the power-on power supply to stop powering on the Type-C interface. In step 302, when the level signal is a high level signal, the Type-C interface is powered on, including: when the level signal is a high level signal, sending a power-on instruction to the application processor; and the power-on instruction is used for indicating the application processor to indicate that a power-on power supply is powered on for a Type-C interface. It will be appreciated that the application processor and the above-described processor are packaged on separate chips, for example, the application processor is integrated on the overall processor chip of the electronic device and the processor 103 is packaged on the processor chip of the Type-C interface. By adopting the embodiment of the application, the processor and the application processor are separately arranged, and the requirement of a user for individually customizing the electronic equipment is met.
In one embodiment, further comprising: when the level signal is a high level signal, a first group of idle pins in the Type-C interface are connected to a power supply pin in the charging management chip, and a second group of idle pins in the Type-C interface is grounded. It should be noted that, the Type-C interface includes 12 pairs of pins, which are respectively (a1, B12), (a2, B11), (A3, B10), (a4, B9), (a5, B8), (A6, B7), (a7, B6), (A8, B5), (a9, B4), (a10, B3), (a11, B2), (a12, B1), and preferably, the idle pins include: the second, third, tenth and eleventh pairs of leads are (a2, B11), (A3, B10), (a10, B3), (a11, B2).
It can be understood that the Type-C interface supports positive and negative blind plugging, and there are four pins conventionally used for charging, including VBUS (a4, a9, B4, B9) and GND (a1, a12, B1, B12), and according to the calculation that one pin passes through a current of 1.25A, the four pins can only bear 5A of current at most theoretically, and the charging current exceeding 5A can cause scalding and even burning. And Type-C interface connection is to the management chip that charges, when adopting the USB2.0 agreement to charge, has a plurality of idle pins, through regard as power pin with a plurality of idle pins respectively, and connect to the power supply pin in the management chip that charges to and the ground pin that corresponds, combine four power pin that already exist, make Type-C interface can bear the electric current that is greater than 5A, pass through 1.25A electric current calculation according to a pin, 1.25AX8 is 10A, can bear 10A electric current promptly in theory.
The application has at least the following benefits: the idle pin through with the Type-C interface uses as power pin, has improved the maximum allowable current of USB end when charging to reduce the probability of generating heat of Type-C interface, reduced the emergence of the unusual circumstances of work appears in Type-C interface, effectively improved the life and the operational reliability of Type-C interface.
The comparator is used for detecting whether the grounding pin of the Type-C interface is grounded or not, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judging mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
Please refer to fig. 4, which shows a schematic structural diagram of a Type-C interface protection device according to an exemplary embodiment of the present application. The Type-C interface protection device can be implemented as all or part of the device through software, hardware or a combination of the two. The Type-C interface protection includes a receive module 401, a stop module 402, and a power-on module 403.
A receiving module 401, which receives the level signal from the comparator through the GPIO pin;
a stopping module 402, configured to stop powering on the Type-C interface when the level signal is the low level signal;
and a power-on module 403, configured to power on the Type-C interface when the level signal is the high level signal.
In one embodiment, the Type-C interface further comprises:
and when the level signal is the high level signal, a first group of idle pins in the Type-C interface are connected to power supply pins in the charging management chip, and a second group of idle pins in the Type-C interface is grounded.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The comparator is used for detecting whether the grounding pin of the Type-C interface is grounded or not, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judging mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the image source tracking method according to the embodiment shown in fig. 1 to fig. 2, and a specific execution process may refer to specific descriptions of the embodiment shown in fig. 1 to fig. 2, which is not described herein again.
The present application further provides a computer program product, where at least one instruction is stored, and the at least one instruction is loaded by the processor and executes the image source tracking method according to the embodiment shown in fig. 1 to fig. 2, where a specific execution process may refer to specific descriptions of the embodiment shown in fig. 1 to fig. 2, and is not described herein again.
Please refer to fig. 5, which is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 5, the electronic device 500 may include: at least one processor 501, at least one network interface 504, a user interface 503, memory 505, at least one communication bus 502. The electronic device 500 includes any Type of Type-C interface protection circuit described in fig. 1, and applies any Type of Type-C interface protection method described in fig. 3.
Wherein a communication bus 502 is used to enable connective communication between these components.
The user interface 503 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 503 may also include a standard wired interface and a wireless interface.
The network interface 504 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
The Memory 505 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable medium. The memory 505 may be used to store instructions, programs, code sets, or instruction sets. The memory 505 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 505 may alternatively be at least one memory device located remotely from the processor 501. As shown in FIG. 5, memory 505, which is one type of computer storage medium, may include an operating system, a network communication module, a user interface module, and an image source tracking application.
In the electronic device 500 shown in fig. 5, the user interface 503 is mainly used as an interface for providing input for a user, and acquiring data input by the user; the processor 501 may be configured to invoke the image source tracking application stored in the memory 505 and perform the following operations:
receiving a level signal from the comparator through the GPIO pin;
when the level signal is the low level signal, stopping electrifying the Type-C interface;
and when the level signal is the high level signal, powering on the Type-C interface.
In one embodiment, the processor 501 performs the stopping of the power on for the Type-C interface when the level signal is the low level signal, including:
when the level signal is the low level signal, sending a power-off instruction to an application processor; the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface;
the processor 501 executes the power up for the Type-C interface when the level signal is the high level signal, including:
when the level signal is the high level signal, sending a power-on instruction to an application processor; the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface.
In one embodiment, processor 501 also performs: when the level signal is the high level signal, a first group of idle pins in the Type-C interface are connected to a power supply pin in the charging management chip, and a second group of idle pins in the Type-C interface is grounded.
The comparator is used for detecting whether the grounding pin of the Type-C interface is grounded or not, so that whether the Type-C interface is in an inserted state or not is judged, the circuit structure and the judging mode are simple, and the cost is low; when detecting the Type-C interface and being in the non-inserted state, stop to be the electrification of Type-C interface, avoid exposing metal pin outside and produce electrochemical corrosion, effectively improve the life and the operational reliability of Type-C interface.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.
Claims (10)
1. A Type-C interface protection circuit, comprising: the device comprises a Type-C interface, a comparator, a processor, a first voltage source and a second voltage source; the Type-C interface comprises a grounding pin, and the processor comprises a GPIO pin;
the non-inverting input end of the comparator is connected with the first voltage source, the inverting input end of the comparator is respectively connected with the grounding pin and the second voltage source, and the output end of the comparator is connected with the GPIO pin of the processor; when the Type-C interface is in an inserted state, the grounding pin is grounded so as to ground the inverting input terminal of the comparator, and when the Type-C interface is in an unplugged state, the grounding pin is suspended so as to load a second voltage signal output by the second voltage source to the inverting input terminal of the comparator;
the first voltage source is used for providing a first voltage signal to a non-inverting input end of the comparator; wherein a voltage value of the second voltage signal is greater than a voltage value of the first voltage signal;
the comparator is used for detecting the first voltage signal through the non-inverting input end and detecting the second voltage signal through the inverting input end; outputting a high level signal when the voltage value of the non-inverting input end is larger than that of the inverting input end, and outputting a low level signal when the voltage value of the non-inverting input end is smaller than that of the inverting input end;
the processor is used for stopping electrifying the Type-C interface when the GPIO pin receives the low level signal or electrifying the Type-C interface when the GPIO pin receives the high level signal.
2. The Type-C interface protection circuit of claim 1, further comprising: a voltage limiting circuit;
the second voltage source is connected with the second end of the comparator through the voltage limiting circuit.
3. The Type-C interface protection circuit of claim 2, wherein the voltage limiting circuit comprises: a first resistor and a second resistor;
the first end of the first resistor is connected with the second voltage source, the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded;
the grounding pin is connected with the second end of the first resistor.
4. The Type-C interface protection circuit of claim 1, further comprising: an application processor and a power-on power supply;
the application processor is respectively connected with the processor and the power-on power supply;
the processor is used for sending a power-off instruction to the application processor when the low-level signal is received through the GPIO pin, or sending a power-on instruction to the application processor when the high-level signal is received;
the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface, and the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface.
5. A Type-C interface protection method is characterized by being applied to any Type-C interface protection circuit of claims 1-4;
the method comprises the following steps:
receiving a level signal from the comparator through the GPIO pin;
when the level signal is the low level signal, stopping electrifying the Type-C interface;
and when the level signal is the high level signal, powering on the Type-C interface.
6. The Type-C interface protection method according to claim 5, wherein the stopping of powering on the Type-C interface when the level signal is the low level signal includes:
when the level signal is the low level signal, sending a power-off instruction to an application processor; the power-off instruction is used for indicating the application processor to indicate the power-on power supply to stop powering on the Type-C interface;
when the level signal is the high level signal, for Type-C interface power-up includes:
when the level signal is the high level signal, sending a power-on instruction to an application processor; the power-on instruction is used for indicating the application processor to indicate the power-on power supply to power on the Type-C interface.
7. The Type-C interface protection method of claim 5, further comprising:
when the level signal is the high level signal, a first group of idle pins in the Type-C interface are connected to a power supply pin in the charging management chip, and a second group of idle pins in the Type-C interface is grounded.
8. The utility model provides a Type-C interface protection device which characterized in that, the device includes:
the receiving module receives a level signal from the comparator through the GPIO pin;
the stopping module stops electrifying the Type-C interface when the level signal is the low level signal;
and the power-on module is used for powering on the Type-C interface when the level signal is the high level signal.
9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any of claims 5-7.
10. An electronic device, characterized in that the electronic device comprises any Type-C interface protection circuit of claims 1-4, and the Type-C interface protection method of any claims 5-7 is applied.
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| CN202110128074.3A CN112817896A (en) | 2021-01-29 | 2021-01-29 | Type-C interface protection circuit, method and device, storage medium and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113641609A (en) * | 2021-06-29 | 2021-11-12 | 荣耀终端有限公司 | Interface circuit, electronic device, and insertion recognition method |
| CN113849438A (en) * | 2021-09-27 | 2021-12-28 | 浙江华创视讯科技有限公司 | Protection circuit, method of protecting circuit, storage medium, and electronic apparatus |
| CN116069697A (en) * | 2023-03-06 | 2023-05-05 | 荣耀终端有限公司 | Type-C interface level control method and related device |
| JP7522370B1 (en) | 2023-02-01 | 2024-07-25 | 富士通クライアントコンピューティング株式会社 | Electronics |
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| CN210983385U (en) * | 2020-02-19 | 2020-07-10 | 北京小米移动软件有限公司 | USBType-C interface module and electronic equipment |
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| CN210983385U (en) * | 2020-02-19 | 2020-07-10 | 北京小米移动软件有限公司 | USBType-C interface module and electronic equipment |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113641609A (en) * | 2021-06-29 | 2021-11-12 | 荣耀终端有限公司 | Interface circuit, electronic device, and insertion recognition method |
| CN113849438A (en) * | 2021-09-27 | 2021-12-28 | 浙江华创视讯科技有限公司 | Protection circuit, method of protecting circuit, storage medium, and electronic apparatus |
| CN113849438B (en) * | 2021-09-27 | 2024-03-08 | 浙江华创视讯科技有限公司 | Protection circuit, method of protecting circuit, storage medium, and electronic device |
| JP7522370B1 (en) | 2023-02-01 | 2024-07-25 | 富士通クライアントコンピューティング株式会社 | Electronics |
| CN116069697A (en) * | 2023-03-06 | 2023-05-05 | 荣耀终端有限公司 | Type-C interface level control method and related device |
| CN116069697B (en) * | 2023-03-06 | 2023-08-22 | 荣耀终端有限公司 | Type-C interface level control method and related device |
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