CN113641393A - Device and method for updating flash memory data on line during operation of single chip microcomputer - Google Patents
Device and method for updating flash memory data on line during operation of single chip microcomputer Download PDFInfo
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- CN113641393A CN113641393A CN202111208179.6A CN202111208179A CN113641393A CN 113641393 A CN113641393 A CN 113641393A CN 202111208179 A CN202111208179 A CN 202111208179A CN 113641393 A CN113641393 A CN 113641393A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/656—Updates while running
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
Abstract
The invention discloses a device and a method for updating flash memory data on line during the operation of a single chip microcomputer, and relates to the technical field of single chip microcomputers. The device comprises: a single chip microcomputer; the singlechip includes: the flash memory is used for storing the program codes, and the central processing unit is used for reading the program codes from the flash memory and executing the program codes; the peripheral module is respectively connected with the central processing unit and the flash memory and is used for carrying out flash memory operation, and a busy signal is generated in time sequence during flash memory operation so that the central processing unit stops reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the central processing unit to recover and continue to read the program codes from the flash memory and execute the program codes; and outputting various combination signals required by the flash memory during the flash memory operation to finish the flash memory operation. The embodiment of the invention can lead the central processing unit to conveniently control the reading, writing and modifying of the flash memory on line, thereby solving the defect that the program updating needs to be burnt by a burner and improving the research and development efficiency.
Description
Technical Field
The invention relates to the technical field of single-chip microcomputers, in particular to a device and a method for updating flash memory data on line during the operation of a single-chip microcomputer.
Background
When a CPU (Central Processing Unit) of the single chip microcomputer executes the program, a Read-Only Memory (ROM) is required to Read the program code from the ROM. The ROM codes are compiled by a compiler and then are written into the ROM of the singlechip in advance during tape-out or through a burner. Once set, the program code cannot be modified.
FLASH memory (FLASH) is widely used as ROM of various single-chip microcomputers because of its repeatedly erasable characteristics, so that the program of the single-chip microcomputer can be repeatedly modified. Conventionally, a burner is used to realize the repeated erasing and writing updating of the program in the flash memory.
However, in practical applications, there is a research and development requirement that a programmer needs to be completely removed to implement program updating, and a CPU of a single chip microcomputer needs to execute program codes on a flash memory on line and modify code data stored on the flash memory on line. Because the flash memory can not be simultaneously operated in time sequence during data reading operation and data erasing operation, the flash memory only uses a single chip microcomputer, and when the CPU executes online flash memory data modification, the CPU can not read program codes from the flash memory for a period of time, so that the CPU has no codes to cause execution errors, the research and development efficiency is reduced, and the user experience is influenced. At this time, the burner cannot be used to meet the above requirements, and a new method needs to be provided to achieve the above requirements.
Disclosure of Invention
The embodiment of the invention aims to provide a device and a method for updating flash memory data on line during the operation of a single chip microcomputer, which can enable a central processing unit in the single chip microcomputer to conveniently control the reading, writing and modifying of the flash memory on line so as to solve the defect that program updating needs to be carried out by a burner, improve the research and development efficiency and improve the user experience.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions: an apparatus for updating flash data online during operation of a single chip, the apparatus comprising: singlechip, wherein: the single chip microcomputer comprises a central processing unit, a flash memory and a peripheral module;
the flash memory is connected with the central processing unit and used for storing program codes;
the central processing unit is used for reading the program codes from the flash memory and executing the program codes;
the peripheral module is respectively connected with the central processing unit and the flash memory and is used for carrying out flash memory operation, and a busy signal is generated in time sequence during flash memory operation and can enable the central processing unit to suspend reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the central processing unit to recover and continue to read the program codes from the flash memory and execute the program codes; and the flash memory controller is used for outputting various combined signals required by the flash memory during the flash memory operation to finish the flash memory operation.
Optionally, the flashing operation comprises one of: parameter setting, time sequence setting, data reading, flash memory erasing, sector erasing and byte programming.
Optionally, the peripheral module includes at least one register, and the register is used for providing the cpu with timing parameters for setting the flash memory.
Optionally, the timing parameter comprises one of: the erasing time, the burning time and the recovery time.
Optionally, the peripheral module is configured to perform a flash memory operation, and generate a busy signal in a time sequence during the flash memory operation; the method comprises the following steps:
the peripheral module uses the starting bit of the register to generate a starting state mark and starts flash memory erasing operation, the peripheral module generates a busy signal in time sequence, and the busy signal can enable the central processing unit to suspend reading program codes from the flash memory and not execute the program codes any more.
Optionally, after the busy signal is started, the central processing unit does not read the program code from the flash memory any more, and does not execute the program code any more; during which triggered interrupt requests are encountered and no longer responded to.
Optionally, the peripheral module is configured to release the busy signal after the flash memory operation is completed; the method comprises the following steps:
in a clock cycle after the flash memory erasing operation is finished, the peripheral module changes a flash memory control signal to enable the flash memory to recover to a read data state;
in the next period after the flash memory erasing operation is finished, the peripheral module generates an end state mark by using the end state bit of the register and releases the busy signal at the same time.
Optionally, after the busy signal is released, the central processing unit starts to resume reading the program codes from the flash memory and continues to execute; and when a triggered interrupt request is encountered in the period, the central processor responds to the interrupt request.
Optionally, the peripheral module further comprises a signal generator for outputting various combination signals required by the flash memory during the operation of the flash memory.
In order to solve the above technical problems, embodiments of the present invention further provide the following technical solutions: a method for updating flash data online during the operation of a single chip microcomputer is characterized in that the method is applied to a device for updating flash data online during the operation of the single chip microcomputer, and the device comprises the following steps: the system comprises a singlechip and an external module; the single chip microcomputer comprises a central processing unit and a flash memory; the flash memory is respectively connected with the central processing unit and the peripheral module; wherein the method comprises the following steps:
the peripheral module generates a busy signal in time sequence when the flash memory operates;
after the busy signal is started, the central processing unit suspends the reading of the program codes from the flash memory;
the peripheral module outputs various combined signals required by the flash memory during the flash memory operation period to complete the flash memory operation;
releasing the busy signal after the flash memory operation of the peripheral module is finished;
and after the busy signal is released, the central processor resumes to continuously read the program codes from the flash memory and executes the program codes.
Compared with the prior art, the device and the method for updating the flash memory data on line during the operation of the singlechip provided by the embodiment of the invention have the advantages that the singlechip comprises a CPU, a flash memory and a peripheral module, and the flash memory is connected with the CPU and stores program codes; the CPU reads the program codes from the flash memory and executes the program codes; the peripheral module is respectively connected with the CPU and the flash memory and is used for carrying out flash memory operation, and a busy signal is generated in time sequence during flash memory operation and can enable the CPU to suspend reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the CPU to recover to continue reading the program codes from the flash memory and execute the program codes downwards; and the flash memory controller is used for outputting various combined signals required by the flash memory during the flash memory operation to finish the flash memory operation. Therefore, the program code data stored in the flash memory can be modified online without a burner during the operation of the single chip microcomputer, the burner is completely removed, the requirements of research and development of the program code data stored in the flash memory are met while the CPU of the single chip microcomputer executes the program code on the flash memory online, only one flash memory is used inside the single chip microcomputer, when the CPU executes the flash memory online modification, the CPU cannot read the program code from the flash memory for a period of time to cause execution errors, the CPU inside the single chip microcomputer can conveniently control the read-write and modification of the flash memory online, the defect that the ROM program needs to be updated through the burner is overcome, the research and development efficiency is improved, and the user experience is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of an apparatus for updating flash memory data online during operation of a single chip microcomputer according to the present invention.
FIG. 2 is a timing diagram of an apparatus for updating flash data online during the operation of a single chip microcomputer during flash erase operation according to the present invention.
Fig. 3 is a schematic flow chart of a method for updating flash memory data online during the operation of a single chip microcomputer according to the present invention.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. As used in this specification, the terms "upper," "lower," "inner," "outer," "bottom," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the invention and simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.
FLASH memory (FLASH) is widely used as ROM of various single-chip microcomputers because of its repeatedly erasable characteristics, so that the program of the single-chip microcomputer can be repeatedly modified.
The structure of the flash memory mainly comprises a MAIN area, an NVR area and an SFR. The MAIN area is mainly used for storing a MAIN program, and when the CPU executes normally, program codes are read from the MAIN area; the NVR area is used for storing fixed application parameters, and an application program can read data from the NVR area but cannot rewrite the data; the SFR is a configuration register of the flash memory, and the configuration register of the flash memory is mainly used for setting erasing voltage and programming voltage. These voltage settings can be measured in test mode and stored in the NVR region. The application program reads these voltage measurements during power-up and then writes them into the configuration register SFR of the flash memory.
The flash memory operation of the singlechip mainly comprises three operations of reading data, programming data and erasing data.
Since a memory cell of a flash memory can only write "1" to "0", data needs to be erased first when data is written, and a general flash memory is designed to be erased in a whole page (block, whole piece). After the data is erased, the data can be programmed at a certain byte address. The operations of reading data, programming data, and erasing a whole page (block, whole slice) of the flash memory cannot be performed simultaneously in terms of timing. Not only the data cannot be erased and written when the data is read, but also the data cannot be read when the data is erased and written, and the program codes in the MAIN area cannot be read by the CPU when the NVR data is read. This means that only one flash memory single chip is used inside, and when the CPU executes online modification of flash memory data, program codes cannot be read from the flash memory for a while, causing the CPU to have no codes, resulting in execution errors, and reducing the efficiency of research and development.
Based on the problems, the invention provides a device and a method for updating flash memory data on line during the operation of a single chip microcomputer, wherein a peripheral module is added to the single chip microcomputer, the peripheral module can complete flash memory operations such as parameter setting, time sequence setting, data reading, sector erasing, byte programming and the like under the control of a CPU, and the flash memory operations can be flexibly combined to realize various complex functions of the flash memory. Meanwhile, when the peripheral module operates in the flash memory, a very accurate busy signal can be generated in a time sequence, the busy signal can enable the CPU to suspend reading the program codes from the flash memory, and the CPU can continue reading the program codes from the flash memory and execute the program codes downwards until the flash memory operation is finished, so that when a single chip microcomputer chip is designed, the flash memory has a system programming function in advance and is integrated in a system, the CPU in the single chip microcomputer can conveniently control reading, writing and modifying of the flash memory on line, the defect that the ROM program needs to be updated through a burner is overcome, and the research and development efficiency is improved.
In one embodiment, as shown in fig. 1, the present invention provides an apparatus for updating flash data online during operation of a single chip microcomputer, the apparatus comprising: singlechip 1, wherein: the single chip microcomputer 1 comprises a Central Processing Unit (CPU) 11, a flash memory 12 and a peripheral module 13; the flash memory 12 is connected with the CPU 11 and is configured to store program codes; the CPU 11 is configured to read program codes from the flash memory and execute the program codes.
The peripheral module 13 is connected to the CPU 11 and the flash memory 12, respectively, and configured to perform a flash memory operation, and generate a busy signal in a time sequence during the flash memory operation, where the busy signal may cause the CPU 11 to suspend reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the CPU 11 to recover to continue reading the program code from the flash memory and execute the program code downwards; and the flash memory controller is used for outputting various combined signals required by the flash memory during the flash memory operation to finish the flash memory operation.
In the embodiment, the single chip microcomputer comprises a CPU, a flash memory and a peripheral module, wherein the flash memory is connected with the CPU and stores program codes; the CPU reads the program codes from the flash memory and executes the program codes; the peripheral module is respectively connected with the CPU and the flash memory and is used for carrying out flash memory operation, and a busy signal is generated in time sequence during flash memory operation and can enable the CPU to suspend reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the CPU to recover to continue reading the program codes from the flash memory and execute the program codes downwards; and the flash memory controller is used for outputting various combined signals required by the flash memory during the flash memory operation to finish the flash memory operation. Therefore, the program code data stored in the flash memory can be modified online without a burner during the operation of the single chip microcomputer, the burner is completely removed, the requirements of research and development of the program code data stored in the flash memory are met while the CPU of the single chip microcomputer executes the program code on the flash memory online, only one flash memory is used inside the single chip microcomputer, when the CPU executes the flash memory online modification, the CPU cannot read the program code from the flash memory for a period of time to cause execution errors, the CPU inside the single chip microcomputer can conveniently control the read-write and modification of the flash memory online, the defect that the ROM program needs to be updated through the burner is overcome, the research and development efficiency is improved, and the user experience is improved.
In one embodiment, the flashing operation comprises a flashing operation of one of: parameter setting, time sequence setting, data reading, flash memory erasing, sector erasing and byte programming.
The peripheral module 13 may complete flash memory operations such as parameter setting, timing setting, data reading, sector erasing, byte programming, etc. under the control of the CPU 11, and these flash memory operations may be flexibly combined to implement various complex functions of the flash memory.
In one embodiment, the peripheral module 13 is used for outputting various combination signals required by the flash memory 12 during the flash memory operation, so as to complete the flash memory operation.
The peripheral module 13 supports functions of the flash memory 12, such as reading data, programming data, erasing in one block (whole page), and the like. The peripheral module 13 may output various combination signals, such as various address values, data values and various control signals, required by the flash memory 12 to perform operations of various functions of the flash memory 12.
Since the sector in which the program is being executed cannot be updated when the flash data is updated, otherwise, the program easily runs off, resulting in an unexpected result. Therefore, the peripheral module may not need to support the full-chip erase function of the flash memory.
In one embodiment, as shown in fig. 1, the peripheral module 13 includes at least one register 131, and the register 131 is used for providing the CPU 11 with parameters for setting a flash operation, where the parameters for the flash operation include: timing parameters, address parameters, and flash data. Wherein the timing parameter comprises one of: the erasing time, the burning time and the recovery time.
In one embodiment, the peripheral module 13 is configured to perform a flash operation, and during the flash operation, a busy signal is generated in time sequence, and the busy signal can make the CPU suspend reading the program codes from the flash memory; the method comprises the following steps:
the peripheral module 13 uses the enable bit of the register 131 to generate an enable status flag to enable flash erase/write operations, and the peripheral module 13 generates a busy signal busy in time sequence, which enables the CPU 11 to suspend reading program codes from the flash memory and to execute the program codes no longer.
In one embodiment, after the busy signal busy is activated, the CPU 11 does not read a program code from the flash memory, and does not execute the program code; during which triggered interrupt requests are encountered and no longer responded to.
In one embodiment, the peripheral module 13 is configured to release the busy signal after the flash memory operation is completed, so that the CPU 11 resumes to continue reading the program code from the flash memory and execute the program code downwards; the method comprises the following steps:
and in a clock cycle after the flash memory erasing operation is finished, the peripheral module changes the flash memory control signal to enable the flash memory to be recovered to a read data state.
In the next period after the flash memory erasing operation is finished, the peripheral module generates an end state mark by using the end state bit of the register, and simultaneously releases the busy signal to enable the CPU to resume reading the program codes from the flash memory and execute the program codes downwards.
In one embodiment, after the flash erasing operation is finished and the busy signal is released, the CPU starts to recover and continue reading the program codes from the flash memory and continues to execute; during which a triggered interrupt request is encountered, the CPU responds to the interrupt request.
In one embodiment, as shown in fig. 1, the peripheral module 13 further includes a signal generator 132, and the signal generator 132 is configured to output various combination signals required by the flash memory during the flash memory operation to complete the flash memory operation.
Fig. 2 is a timing diagram of an apparatus for updating flash data online during the operation of a single chip microcomputer during flash erasing operation according to the present invention.
When flash erasing is started (e.g. PC = B in the command position of fig. 2), a busy signal busy is generated by the peripheral, which enables the CPU to suspend reading program code from the flash (e.g. PC = D' in the position of fig. 2), without executing code. And in a clock cycle after the erasing operation of the flash memory is finished, the peripheral module changes the flash memory control signal to enable the flash memory to be recovered to a read data state. In the next cycle, the peripheral module generates an end status flag while releasing the busy signal. After the busy signal is released, the CPU starts resuming reading the program code from the flash memory and executes the program down (e.g., the instruction position of PC = D, PC = E in fig. 2).
Based on the same concept, in one embodiment, as shown in fig. 3, the present invention provides a method for updating flash data online during operation of a single chip, which is applied to an apparatus for updating flash data online during operation of a single chip, the apparatus comprising: the system comprises a singlechip and an external module; the single chip microcomputer comprises a CPU and a flash memory; the flash memory is respectively connected with the CPU and the peripheral module; wherein the method comprises the following steps:
s1, when the peripheral module operates in the flash memory, a busy signal is generated in time sequence;
s2, after the busy signal is started, the CPU suspends the reading of the program codes from the flash memory;
s3, outputting various combined signals required by the flash memory by the peripheral module during the flash memory operation period to complete the flash memory operation;
s4, releasing the busy signal after the flash operation of the peripheral module is finished;
and S5, after the busy signal is released, the CPU resumes to continuously read the program codes from the flash memory and executes the program codes downwards.
In the embodiment, the single chip microcomputer comprises a CPU, a flash memory and a peripheral module, wherein the flash memory is respectively connected with the CPU and the peripheral module; the peripheral module generates a busy signal in time sequence when the flash memory operates; after the busy signal is started, the CPU suspends the reading of the program codes from the flash memory; the peripheral module outputs various combined signals required by the flash memory during the flash memory operation period to complete the flash memory operation; releasing the busy signal after the flash memory operation of the peripheral module is finished; and after the busy signal is released, the CPU resumes to continuously read the program codes from the flash memory and executes the program codes downwards. Therefore, the program code data stored in the flash memory can be modified online without a burner during the operation of the single chip microcomputer, the burner is completely removed, the requirements of research and development of the program code data stored in the flash memory are met while the CPU of the single chip microcomputer executes the program code on the flash memory online, only one flash memory is used inside the single chip microcomputer, when the CPU executes the flash memory online modification, the CPU cannot read the program code from the flash memory for a period of time to cause execution errors, the CPU inside the single chip microcomputer can conveniently control the read-write and modification of the flash memory online, the defect that the ROM program needs to be updated through the burner is overcome, the research and development efficiency is improved, and the user experience is improved.
In one embodiment, the flashing operation comprises a flashing operation of one of: parameter setting, time sequence setting, data reading, flash memory erasing, sector erasing and byte programming.
The peripheral module can complete flash memory operations such as parameter setting, time sequence setting, data reading, sector erasing, byte programming and the like under the control of the CPU, and the flash memory operations can be flexibly combined to realize various complex functions of the flash memory.
In one embodiment, in the step S3, the peripheral module outputs various combination signals required by the flash memory during the flash memory operation, so as to complete the flash memory operation; the method comprises the following steps:
the peripheral module supports the functions of reading data, programming data, erasing in a whole block (whole page) and the like of the flash memory. The peripheral module can output various combined signals required by the flash memory, such as various address values, data values and various control signals, and complete the operation of various functions of the flash memory.
Since the sector in which the program is being executed cannot be updated when the flash data is updated, otherwise, the program easily runs off, resulting in an unexpected result. Therefore, the peripheral module may not need to support the full-chip erase function of the flash memory.
In one embodiment, the peripheral module includes at least one register for providing the CPU with parameters for setting a flash operation, the parameters for the flash operation including: timing parameters, address parameters, and flash data. Wherein the timing parameter comprises one of: the erasing time, the burning time and the recovery time.
And setting registers required for modifying flash program data in the peripheral module. Some of the various time sequences required by the flash memory during operation need to be adjusted during operation, such as the time sequence parameters of the length of the erasing time, the length of the burning time, the length of the recovery time, and the like, and the setting of the time sequence parameters is performed by the CPU using the register. The NVR data read back is also read by the CPU via the register. The register includes a start bit and an end state bit that are settable by the CPU. The CPU can flexibly control the operation of the flash memory by selecting proper operation in a register control mode.
In one embodiment, in the step S1, the peripheral module generates a busy signal in time sequence during the flash memory operation; the method comprises the following steps:
the peripheral module uses the starting bit of the register to generate a starting state mark to start flash memory erasing operation, and the peripheral module generates a busy signal busy in time sequence, wherein the busy signal busy can enable the CPU to suspend reading program codes from the flash memory and not execute the program codes any more.
In one embodiment, in the step S2, the CPU suspends the reading of the program codes from the flash memory after the busy signal is activated; the method comprises the following steps:
after the busy signal busy is started, the CPU does not read the program codes from the flash memory any more and does not execute the program codes any more; during which triggered interrupt requests are encountered and no longer responded to.
In one embodiment, in the step S4, after the peripheral module flash memory operation is completed, the busy signal is released; the method comprises the following steps:
the peripheral module is used for releasing the busy signal after the flash memory operation is finished, so that the CPU recovers to continue reading the program code from the flash memory and executes the program code downwards; the method comprises the following steps:
and in a clock cycle after the flash memory erasing operation is finished, the peripheral module changes the flash memory control signal to enable the flash memory to be recovered to a read data state.
In the next period after the flash memory erasing operation is finished, the peripheral module generates an end state mark by using the end state bit of the register, and simultaneously releases the busy signal to enable the CPU to resume reading the program codes from the flash memory and execute the program codes downwards.
In one embodiment, in step S5, after the busy signal is released, the CPU resumes reading program codes from the flash memory and executing downwards; the method comprises the following steps:
after the flash memory erasing operation is finished and the busy signal is released, the CPU starts to recover and continuously reads the program codes from the flash memory and continuously executes the program codes; during which a triggered interrupt request is encountered, the CPU responds to the interrupt request.
It should be noted that the method embodiment and the apparatus embodiment belong to the same concept, and specific implementation processes thereof are described in the apparatus embodiment in detail, and technical features in the apparatus embodiment are correspondingly applicable in the method embodiment, and repeated details are omitted.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An apparatus for updating flash data online during operation of a single chip microcomputer, the apparatus comprising: singlechip, wherein: the single chip microcomputer comprises a central processing unit, a flash memory and a peripheral module;
the flash memory is connected with the central processing unit and used for storing program codes;
the central processing unit is used for reading the program codes from the flash memory and executing the program codes;
the peripheral module is respectively connected with the central processing unit and the flash memory and is used for carrying out flash memory operation, and a busy signal is generated in time sequence during flash memory operation and can enable the central processing unit to suspend reading program codes from the flash memory; after the flash memory operation is finished, releasing the busy signal to enable the central processing unit to recover and continue to read the program codes from the flash memory and execute the program codes; and the flash memory controller is used for outputting various combined signals required by the flash memory during the flash memory operation to finish the flash memory operation.
2. The apparatus of claim 1, wherein the flashing operation comprises one of: parameter setting, time sequence setting, data reading, flash memory erasing, sector erasing and byte programming.
3. The apparatus of claim 1, wherein the peripheral module comprises at least one register for providing the central processor with parameters for setting a flash operation, the parameters for the flash operation comprising: timing parameters, address parameters, and flash data.
4. The apparatus of claim 3, wherein the timing parameter comprises one of: the erasing time, the burning time and the recovery time.
5. The apparatus of claim 3, wherein the peripheral module is configured to perform a flash operation, and to generate a busy signal in a time sequence during the flash operation; the method comprises the following steps:
the peripheral module uses the starting bit of the register to generate a starting state mark and starts flash memory erasing operation, the peripheral module generates a busy signal in time sequence, and the busy signal can enable the central processing unit to suspend reading program codes from the flash memory and not execute the program codes any more.
6. The apparatus of claim 5, wherein after the busy signal is activated, the central processor no longer reads program code from the flash memory and no longer executes program code; during which triggered interrupt requests are encountered and no longer responded to.
7. The apparatus of claim 6, wherein the peripheral module is configured to release the busy signal after the flash operation is completed; the method comprises the following steps:
in a clock cycle after the flash memory erasing operation is finished, the peripheral module changes a flash memory control signal to enable the flash memory to recover to a read data state;
in the next period after the flash memory erasing operation is finished, the peripheral module generates an end state mark by using the end state bit of the register and releases the busy signal at the same time.
8. The apparatus of claim 7, wherein after the busy signal is released, the central processor starts resuming reading program code from the flash memory and continuing execution; and when a triggered interrupt request is encountered in the period, the central processor responds to the interrupt request.
9. The apparatus of claim 1, wherein the peripheral module further comprises a signal generator for outputting various combined signals required by the flash memory during operation of the flash memory.
10. A method for updating flash data online during operation of a single chip microcomputer, which is applied to the device for updating flash data online during operation of a single chip microcomputer according to any one of claims 1 to 9, and comprises the following steps: the system comprises a singlechip and an external module; the single chip microcomputer comprises a central processing unit and a flash memory; the flash memory is respectively connected with the central processing unit and the peripheral module; wherein the method comprises the following steps:
the peripheral module generates a busy signal in time sequence when the flash memory operates;
after the busy signal is started, the central processing unit suspends the reading of the program codes from the flash memory;
the peripheral module outputs various combined signals required by the flash memory during the flash memory operation period to complete the flash memory operation;
releasing the busy signal after the flash memory operation of the peripheral module is finished;
and after the busy signal is released, the central processor resumes to continuously read the program codes from the flash memory and executes the program codes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111208179.6A CN113641393A (en) | 2021-10-18 | 2021-10-18 | Device and method for updating flash memory data on line during operation of single chip microcomputer |
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| US5923838A (en) * | 1996-12-17 | 1999-07-13 | Mitsubishi Denki Kabushiki Kaisha | Microcomputer with built-in flash memory |
| US6567930B1 (en) * | 1998-11-13 | 2003-05-20 | Nec Corporation | Method and apparatus for controlling writing of flash EEPROM by microcomputer |
| US6636992B1 (en) * | 2000-09-08 | 2003-10-21 | Myson Century, Inc. | Method for renewing program code in an embedded micro-controller unit |
| CN1564131A (en) * | 2004-03-29 | 2005-01-12 | 中兴通讯股份有限公司 | Method and device of realizing uppdating of single processor software |
| US20060077721A1 (en) * | 2004-10-08 | 2006-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit with flash interface |
| CN111290772A (en) * | 2020-03-12 | 2020-06-16 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for updating CPLD |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923838A (en) * | 1996-12-17 | 1999-07-13 | Mitsubishi Denki Kabushiki Kaisha | Microcomputer with built-in flash memory |
| US6567930B1 (en) * | 1998-11-13 | 2003-05-20 | Nec Corporation | Method and apparatus for controlling writing of flash EEPROM by microcomputer |
| US6636992B1 (en) * | 2000-09-08 | 2003-10-21 | Myson Century, Inc. | Method for renewing program code in an embedded micro-controller unit |
| CN1564131A (en) * | 2004-03-29 | 2005-01-12 | 中兴通讯股份有限公司 | Method and device of realizing uppdating of single processor software |
| US20060077721A1 (en) * | 2004-10-08 | 2006-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit with flash interface |
| CN111290772A (en) * | 2020-03-12 | 2020-06-16 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for updating CPLD |
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