CN111290772A

CN111290772A - Method, system, device and medium for updating CPLD

Info

Publication number: CN111290772A
Application number: CN202010169548.4A
Authority: CN
Inventors: 谢武志
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-03-12
Filing date: 2020-03-12
Publication date: 2020-06-16
Anticipated expiration: 2040-03-12
Also published as: CN111290772B

Abstract

The invention discloses a method, a system, equipment and a storage medium for updating a CPLD, wherein the method comprises the following steps: locking the reset signal and writing the updated data into the peripheral memory; in response to the update data written into the peripheral memory being higher than a first threshold, packaging the update data and sending the packaged update data to a configuration flash memory; in response to detecting that update data in the peripheral memory is below a second threshold, writing remaining update data to the peripheral memory; and in response to the step being repeated for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal. The method, the system, the equipment and the medium for updating the CPLD can complete the updating of the CPLD under the condition of not switching and configuring the flash memory under the protection and recovery architecture of the platform firmware by locking the reset signal.

Description

Method, system, device and medium for updating CPLD

Technical Field

The present invention relates to the field of CPLDs, and more particularly, to a method, a system, a computer device and a readable medium for updating a CPLD.

Background

In the era of major information outbreak, information security is more and more emphasized by international factories. In order to avoid the server from being attacked to cause system abnormality or hacking, the National Institute of Standards and Technology (NIST) issued the NIST SP 800193 standard in 2018, which mainly defines a standard security mechanism for preventing the device from being attacked and how to recover the attacked system to a normal state.

The NIST SP 800193 standard, also known as Platform firmware protection recovery (PFR), is mainly defined based on the following three principles: 1. protection: when the system writes the equipment, the action can be allowed only after the authentication of a set of security algorithm; 2. and (3) detection: the system can continuously monitor the equipment to ensure the safety of the equipment interface; 3. and (3) recovering: if tampering with the device is detected, a reversion to the last secure version may be performed. Under the platform firmware protection and recovery architecture, the instructions of the NI OS II (soft core processor) CPU are stored in the currently configured CFM (configuration flash memory), for example, CPLD Active FW corresponds to CFM1, and Factory FW corresponds to CFM 0. If the NIOS II CPU runs CFM1 and updates CFM1, it will cause the NIOS II CPU to be abnormal, and further cause the NIOS II to stop running. Thus, if Active FW (Active firmware CFM1) is to be updated, CPLD FW must be switched to Recovery FW (Recovery firmware CFM0) before CFM1 can be updated. After the CFM1 update is completed, the CPLD FW can be switched back to the CFM 1. Thus CPLD updates are very trivial.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for updating a CPLD, which can complete the updating of the CPLD without switching a configuration flash memory under a platform firmware protection recovery architecture by locking a reset signal and writing update data into an external memory.

Based on the above object, an aspect of the embodiments of the present invention provides a method for updating a CPLD, including the following steps: locking the reset signal and writing the updated data into the peripheral memory; in response to the update data written into the peripheral memory being higher than a first threshold, packaging the update data and sending the packaged update data to a configuration flash memory; in response to detecting that update data in the peripheral memory is below a second threshold, writing remaining update data to the peripheral memory; and in response to the step being repeated for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

In some embodiments, the writing the update data in the configuration flash to the CPLD includes: updating the configuration flash memory based on the update data; and in response to the configuration flash updating being completed, sending a reload signal to enable the CPLD to reload the update data in the configuration flash.

In some embodiments, said updating the configuration flash based on the update data comprises: and classifying the updating data, and respectively updating the first configuration flash memory and the second configuration flash memory according to the classification.

In some embodiments, further comprising: the predetermined number of times is determined based on a size of the update data and a capacity of the memory.

In another aspect of the embodiments of the present invention, a system for updating a CPLD is further provided, including: the locking module is configured to lock the reset signal and write the update data into the peripheral memory; the packaging module is configured to package the update data written into the peripheral memory in response to the update data being higher than a first threshold value, and send the update data to the configuration flash memory; a write module configured to write remaining update data to the peripheral memory in response to detecting that update data in the peripheral memory is below a second threshold; and the updating module is configured for responding to the repeated steps for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

In some embodiments, the update module is further configured to: updating the configuration flash memory based on the update data; and in response to the configuration flash updating being completed, sending a reload signal to enable the CPLD to reload the update data in the configuration flash.

In some embodiments, the update module is further configured to: and classifying the updating data, and respectively updating the first configuration flash memory and the second configuration flash memory according to the classification.

In some embodiments, further comprising: a calculation module configured to determine the predetermined number of times based on a size of the update data and a capacity of the memory.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: the updating of the CPLD can be completed under the condition that the flash memory is not switched and configured under the protection and recovery architecture of the platform firmware by locking the reset signal and writing the updated data into the peripheral memory.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of a CPLD under a platform firmware protection recovery architecture;

fig. 2 is a schematic diagram of an embodiment of a method for updating a CPLD according to the present invention;

FIG. 3 is a schematic diagram of a CPLD according to the present invention;

fig. 4 is a schematic hardware structure diagram of an embodiment of the computer device for updating a CPLD provided in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Fig. 1 is a schematic diagram of a CPLD under a platform firmware protection recovery architecture. NIOS-II provides a RISC soft-core processor for INTEL to manage data movement, control, operation, etc. of the whole system. The instructions of the CPU are configured on the first configuration flash CFM0 or the second configuration flash CFM1, and the transmission target of the instructions is determined according to the configuration flash operated by the CPLD currently. The counter in fig. 1 is used to count time; the memory is used for temporarily storing data; the CPU reset control is used for controlling the reset of the CPU; the embedded memory is used for temporarily storing data for the CPU and disappears after the power is turned off; the user flash memory is used for storing events, records and the like; the MAX10 dual slave configuration module is mainly provided for software to control the configuration of the CPLD; the SMBus master module is an SMBus active end module, and the SMBus slave module is an SMBus passive end module; the SPI master module is an SPI Bus passive end module, when the SPI master module enters a system, the CPLD can monitor the external flash memory through the SPI Bus passive end module, and when the SPI slave module is an SPI Bus active end module, the CPLD can read data of the external flash memory through the SPI Bus passive end module to confirm data security; the Avalon MM bus is an Avalon MM bus interface; the Avalon MM master module is an Avalon MM master end control module; the universal input and output is a universal pin control module; the cryptographic accelerator is used for encryption.

In view of the above objects, a first aspect of the embodiments of the present invention proposes an embodiment of a method for updating a CPLD. Fig. 2 is a schematic diagram illustrating an embodiment of the method for updating a CPLD provided in the present invention. As shown in fig. 2, the embodiment of the present invention includes the following steps:

s1, locking the reset signal and writing the updated data into the peripheral memory;

s2, in response to the fact that the update data written into the peripheral memory is higher than a first threshold value, packaging the update data and sending the update data to the configuration flash memory;

s3, in response to the fact that the updating data in the peripheral memory are detected to be lower than a second threshold value, writing the residual updating data into the peripheral memory; and

and S4, in response to the step being repeated for the preset times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

Fig. 3 shows a schematic diagram of an improved CPLD provided by the present invention. As shown in fig. 3, a set of update modules (CPLD update function blocks) is added on the basis of the prior art, and the NIOS II processor is bypassed to directly update the first configuration flash CFM0 or the second configuration flash CFM1, and the operation of the NIOS II processor is stopped at the same time, so as to avoid interference generated during the circuit update period of the NIOS II processor. The external interface is an SMBus interface, and the BMC can update CFM0 or CFM1 through the interface, reset CPU action and reload CPLD FW. The system can update the Active FW without switching to Factory FW.

The technical solution of the present invention is further described below with reference to fig. 3:

the reset signal is locked and the update data is written to the peripheral memory. The BMC locks the reset signal of the NIOS II processor through the SMBus interface to enable the NIOS II CPU to be incapable of running. The update data may be written to a peripheral memory (i.e., the memory in fig. 3), which may be, for example, a FIFO (first-in-first-out memory), to which the BMC moves data through the SMBus interface.

And in response to the update data written into the peripheral memory being higher than the first threshold, packaging the update data and sending the update data to the configuration flash memory. And when the updating data written into the FIFO reaches a certain amount, issuing an updating CFM action to the Avalon MM master module. After receiving the CFM updating action, the Avalon MM master module can read out the data of the memory, and then pack the data into a packet of an Avalon MM bus, so as to write in the CFM.

In response to detecting that the update data in the memory is below the second threshold, writing remaining update data to the peripheral memory. When the updating data in the peripheral memory is too little, the rest updating data can be continuously read, and when the updating data in the memory is too much, the packaging and sending are continuously carried out. Of course, it is also possible to pack the update data in the memory at a time and then pack the data of the next batch.

And in response to the step being repeated for the preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal. In some embodiments, further comprising: the predetermined number of times is determined based on a size of the update data and a capacity of the memory. If the updating data is fully stored in the memory, then the updating data is packaged, and then the next packaging is carried out, then the size of the updating data and the capacity of the memory are obtained, and then the preset times can be obtained by calculation. The BMC records the update record to the user flash memory through SMBus, so that the system can know whether there is an action to update the CPLD.

In some embodiments, the writing the update data in the configuration flash to the CPLD includes: updating the configuration flash memory based on the update data; and in response to the configuration flash updating being completed, sending a reload signal to enable the CPLD to reload the update data in the configuration flash. The BMC sends a reloading command to the MAX10 slave configuration module, so that the CPLD FW can reload new CFM information.

It should be particularly noted that, the steps in the embodiments of the method for updating a CPLD described above can be mutually intersected, replaced, added, and deleted, so that these methods for updating a CPLD that are reasonably arranged and combined to transform also belong to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a system for updating a CPLD, including: the locking module is configured to lock the reset signal and write the update data into the peripheral memory; the packaging module is configured to package the update data written into the peripheral memory in response to the update data being higher than a first threshold value, and send the update data to the configuration flash memory; a write module configured to write remaining update data to the peripheral memory in response to detecting that update data in the peripheral memory is below a second threshold; and the updating module is configured for responding to the repeated steps for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, locking the reset signal and writing the updated data into the peripheral memory; s2, in response to the fact that the update data written into the peripheral memory is higher than a first threshold value, packaging the update data and sending the update data to the configuration flash memory; s3, in response to the fact that the updating data in the peripheral memory are detected to be lower than a second threshold value, writing the residual updating data into the peripheral memory; and S4, in response to the steps being repeated for the preset times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

Fig. 4 is a schematic hardware structure diagram of an embodiment of the computer device for updating a CPLD according to the present invention.

Taking the apparatus shown in fig. 4 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.

The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 4 illustrates the connection by a bus as an example.

The memory 302, which is a non-volatile computer-readable storage medium, can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for updating a CPLD in the embodiment of the present application. The processor 301 executes various functional applications of the server and data processing by running the nonvolatile software programs, instructions and modules stored in the memory 302, that is, implements the method for updating the CPLD of the above-described method embodiment.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of updating the CPLD, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.

One or more program instructions/modules corresponding to the method of updating the CPLD are stored in the memory 302 and, when executed by the processor 301, perform the method of updating the CPLD in any of the method embodiments described above.

Any embodiment of a computer device that performs the above-described method for updating a CPLD may achieve the same or similar effects as any of the preceding method embodiments that correspond thereto.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for updating the CPLD can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for updating a CPLD, comprising the steps of:

locking the reset signal and writing the updated data into the peripheral memory;

in response to the update data written into the peripheral memory being higher than a first threshold, packaging the update data and sending the packaged update data to a configuration flash memory;

in response to detecting that update data in the peripheral memory is below a second threshold, writing remaining update data to the peripheral memory; and

and in response to the step being repeated for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

2. The method of claim 1, wherein writing the update data in the configuration flash to the CPLD comprises:

updating the configuration flash memory based on the update data; and

in response to the configuration flash updating being completed, issuing a reload signal to enable the CPLD to reload the update data in the configuration flash.

3. The method of claim 2, wherein the updating the configuration flash based on the update data comprises:

and classifying the updating data, and respectively updating the first configuration flash memory and the second configuration flash memory according to the classification.

4. The method of claim 1, further comprising:

the predetermined number of times is determined based on a size of the update data and a capacity of the memory.

5. A system for updating a CPLD, comprising:

the locking module is configured to lock the reset signal and write the update data into the peripheral memory;

the packaging module is configured to package the update data written into the peripheral memory in response to the update data being higher than a first threshold value, and send the update data to the configuration flash memory;

a write module configured to write remaining update data to the peripheral memory in response to detecting that update data in the peripheral memory is below a second threshold; and

and the updating module is configured for responding to the repeated steps for a preset number of times, writing the updating data in the configuration flash memory into the CPLD, and releasing the locking of the reset signal.

6. The system of claim 5, wherein the update module is further configured to:

updating the configuration flash memory based on the update data; and

7. The system of claim 6, wherein the update module is further configured to:

8. The system of claim 5, further comprising:

a calculation module configured to determine the predetermined number of times based on a size of the update data and a capacity of the memory.

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.