CN113625527B - Method for setting alignment mark of warpage wafer - Google Patents
Method for setting alignment mark of warpage wafer Download PDFInfo
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- CN113625527B CN113625527B CN202110811805.4A CN202110811805A CN113625527B CN 113625527 B CN113625527 B CN 113625527B CN 202110811805 A CN202110811805 A CN 202110811805A CN 113625527 B CN113625527 B CN 113625527B
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000006073 displacement reaction Methods 0.000 claims abstract description 74
- 238000010586 diagram Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 13
- 230000000295 complement effect Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
- G03F9/7023—Aligning or positioning in direction perpendicular to substrate surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Multimedia (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for setting alignment marks of a warping wafer. Comprising the following steps: obtaining the warpage data of the target wafer, and calculating the warpage direction of the target wafer according to the warpage data; acquiring an actual alignment mark distribution diagram of a target wafer, and judging an invalid alignment mark and an effective alignment mark in the actual alignment mark distribution diagram according to the ideal alignment mark distribution diagram; determining a first direction displacement area and a second direction displacement area of the target wafer, wherein an actual alignment mark in the first direction displacement area is displaced along the first direction relative to an ideal alignment mark, and an actual alignment mark in the second direction displacement area is displaced along the second direction relative to the ideal alignment mark; and (3) remaining the effective alignment marks, and setting the supplementary alignment marks at the positions of the ineffective alignment marks, so that the supplementary alignment marks in the first direction displacement area extend along the first direction, and the supplementary alignment marks in the second direction displacement area extend along the second direction.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for setting alignment marks of a warping wafer.
Background
In the manufacturing process of semiconductor integrated circuits, a large amount of photolithography is required. The lithography of each level requires alignment of the pattern of the layer with the pattern of the preceding layer, i.e. lithography alignment, prior to exposure. The purpose of this alignment process is to overlay the pattern on the reticle with maximum accuracy over the existing pattern of the wafer. In particular, for a multilayer structure, the layers are required to be precisely aligned when being superposed by interlayer recombination, so that the problem of interlayer connection is avoided.
In the related art, to assist in interlayer alignment of a semiconductor device, alignment marks are generally printed in a dielectric layer, so that a subsequent hierarchical structure is aligned and overlapped with the dielectric layer according to the alignment marks.
However, due to the stress difference between the film layers on the wafer, the wafer is warped under the stress effect, and the larger the wafer size is, the more obvious the warpage is on the wafer, so that the pattern displacement of the alignment mark on the wafer is aggravated, and the interlayer alignment between the layers is affected.
Disclosure of Invention
The application provides a method for setting alignment marks of a warped wafer, which can solve the problem that the pattern displacement of the alignment marks of the warped wafer is aggravated to cause interlayer alignment failure in the related art.
In order to solve the technical problems in the background art, the application provides a method for setting alignment marks of a warped wafer, which comprises the following steps:
obtaining warp data of a target wafer, and calculating the warp direction of the target wafer according to the warp data;
acquiring an actual alignment mark distribution diagram of the target wafer, and judging an invalid alignment mark and an effective alignment mark in the actual alignment mark distribution diagram according to an ideal alignment mark distribution diagram;
determining a first direction displacement area and a second direction displacement area of the target wafer, wherein an actual alignment mark in the first direction displacement area is displaced along a first direction relative to an ideal alignment mark, and an actual alignment mark in the second direction displacement area is displaced along a second direction relative to the ideal alignment mark, and the first direction and the second direction are mutually perpendicular;
and (3) remaining effective alignment marks, and setting supplementary alignment marks at the positions of the ineffective alignment marks, so that the supplementary alignment marks in the first direction displacement area extend along the first direction, and the supplementary alignment marks in the second direction displacement area extend along the second direction.
Optionally, the first direction is the same as a warp direction of the target wafer.
Optionally, the boundary of the first direction displacement area is located at a position where the first angles at two sides of the warp direction are located, wherein the vertex is the center of the target wafer.
Optionally said first angle is 45 °.
Optionally, the first direction displacement areas include two, and the two first direction displacement areas use the center of the target wafer as a common vertex.
Optionally, the second direction displacement region is located in a target wafer region between the two first direction displacement regions.
Optionally, the effective alignment mark is reserved, and a supplementary alignment mark is arranged at the position of the ineffective alignment mark, so that the supplementary alignment mark in the first direction displacement area extends along the first direction, and the displacement direction of the supplementary alignment mark relative to the ideal alignment mark is consistent with the extending direction of the supplementary alignment mark in the step of extending the supplementary alignment mark in the second direction displacement area along the second direction.
The technical scheme of the application at least comprises the following advantages: according to the application, the original invalid alignment mark in the first direction displacement area is replaced by the Y-direction extending complementary alignment mark, and the original invalid alignment mark in the second direction displacement area is replaced by the X-direction extending complementary alignment mark, so that the displacement of the alignment marks in the first direction displacement area and the second direction displacement area relative to the ideal alignment mark is consistent with the extending direction of the alignment marks, and even if a wafer is warped, accurate alignment can be performed according to the alignment marks.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a method for positioning alignment marks on a warped wafer according to one embodiment of the present application;
FIG. 2a shows a comparison of a target wafer and an ideal wafer provided by an embodiment of the present application;
FIG. 2b shows the warped target wafer of FIG. 2a with a cross-sectional view of the enclosed area A1A2A3A 4;
FIG. 2c shows a distribution diagram of the actual alignment marks of the target wafer obtained in step S12 according to an embodiment of the present application;
fig. 2d shows a schematic diagram after step S14 based on fig. 2 c.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Fig. 1 shows a method for setting a warpage wafer alignment mark according to an embodiment of the present application, and as can be seen from fig. 1, the method for setting a warpage wafer alignment mark includes the following steps S11 to S14, which are sequentially performed, wherein:
step S11: and obtaining the warpage data of the target wafer, and calculating the warpage direction of the target wafer according to the warpage data.
FIG. 2a shows a comparison of a target wafer and an ideal wafer provided by an embodiment of the present application. Fig. 2b shows the warped target wafer of fig. 2a with a cross-sectional view of the enclosed area A1A2A3 A4. The ideal wafer is a wafer which is not warped, and the target wafer is a wafer which is warped. As can be seen in fig. 2a and 2b, comparing an ideal wafer 110 that is not warped with a target wafer 120 that is warped, it can be seen that the target wafer 120 that is warped toward the front along a warp direction 130. The warp direction 130 in this embodiment is the Y direction in fig. 2 a.
Step S12: and acquiring an actual alignment mark distribution diagram of the target wafer, and judging an invalid alignment mark and an effective alignment mark in the actual alignment mark distribution diagram according to the ideal alignment mark distribution diagram.
The ideal alignment mark distribution map comprises a plurality of ideal alignment marks, and the actual alignment mark distribution map comprises a plurality of actual alignment marks. The ideal alignment mark distribution diagram is used for manufacturing alignment marks of a target wafer, but the target wafer is warped, so that part of the actual alignment marks in the actual alignment mark distribution diagram are displaced. The displacement takes place so that the actual alignment mark which cannot form effective alignment is an invalid alignment mark, and the displacement takes place so that the actual alignment mark which can form effective alignment is an effective alignment mark.
With continued reference to fig. 2a, the ideal wafer 110 includes first and second ideal alignment marks 111 and 112 thereon, and the target wafer 120 includes first and second actual alignment marks 121 and 122 thereon. The first actual alignment marks 121 correspond to the first ideal alignment marks 111, and each extend in the Y direction. The second actual alignment marks 122 correspond to the second ideal alignment marks 112, and each extend in the X direction. The X direction and the Y direction are mutually perpendicular.
The first physical alignment mark 121 is displaced inward in the X direction relative to the first ideal alignment mark 111 and the second physical alignment mark 122 is also displaced inward in the X direction relative to the second ideal alignment mark 112 due to the warpage of the target wafer 120 relative to the ideal wafer 110.
In this embodiment, since the warp direction 130 of the target wafer 120 is the Y direction, the first actual alignment mark 121 and the first ideal alignment mark 111 extend in the Y direction, and the displacement of the first actual alignment mark 121 along the X direction relative to the first ideal alignment mark 111 is inconsistent with the displacement direction, the back layer cannot achieve accurate alignment with the current layer through the first actual alignment mark 121, i.e. the first actual alignment mark 121 is an ineffective alignment mark.
Conversely, the second actual alignment mark 122 and the second ideal alignment mark 112 both extend in the X direction, and the second actual alignment mark 122 is also displaced along the X direction relative to the second ideal alignment mark 112, and the extending direction is consistent with the displacement direction, so that the subsequent layer can achieve accurate alignment with the current layer through the second actual alignment mark 122, that is, the second actual alignment mark 122 is an effective alignment mark.
FIG. 2c shows the actual alignment mark distribution of the target wafer obtained in step S12 according to one embodiment of the present application, wherein FIG. 2c shows the actual alignment mark distribution of the target wafer based on FIG. 2 a. As can be seen in fig. 2c, the actual alignment mark distribution map of the target wafer includes a plurality of actual alignment marks, i.e., a plurality of first actual alignment marks 121 and a plurality of second actual alignment marks 122 as shown in fig. 2 a. In fig. 2c, the actual alignment marks filled with the grid lines are invalid alignment marks determined according to the ideal alignment mark distribution diagram, and the actual alignment marks without filling are valid alignment marks determined according to the ideal alignment mark distribution diagram.
Step S13: and determining a first direction displacement area and a second direction displacement area of the target wafer. The actual alignment mark in the first direction displacement area is displaced along a first direction relative to the ideal alignment mark, the actual alignment mark in the second direction displacement area is displaced along a second direction relative to the ideal alignment mark, and the first direction and the second direction are mutually perpendicular.
With continued reference to fig. 2c, the target wafer is divided into two first direction displacement regions 210 and two second direction displacement regions 220, wherein the two first direction displacement regions 210 are opposite corners, a common vertex thereof is a center of the target wafer, and the two second direction displacement regions 220 are opposite corners, a common vertex thereof is a center of the target wafer. And the adjacent first direction displacement region 210 and second direction displacement region 220 are complementary angles.
In fig. 2c, the first direction is the Y direction, the second direction is the X direction, and the warp direction 130 of the target wafer 120 is the Y direction.
As can be seen in fig. 2c, the invalid alignment marks in the first direction displacement zone 210 are the second actual alignment marks 122. The reason is that: the actual alignment marks in the first direction displacement area 210 are displaced along the Y direction relative to the ideal alignment marks, wherein the second actual alignment marks 122 extend along the X direction, and the extending direction of the second actual alignment marks 122 is different from the displacement direction thereof, so that the displacement of the second actual alignment marks 122 along the Y direction is not effective.
As can also be seen in fig. 2c, the invalid alignment marks in the second direction displacement zone 220 are first actual alignment marks 121. The reason is that: the actual alignment marks in the second direction displacement area 220 are displaced along the X-direction relative to the ideal alignment marks, wherein the first actual alignment marks 121 extend along the Y-direction, and the first actual alignment marks 121 extend along the X-direction, and the extending direction of the second actual alignment marks 122 is different from the displacement direction thereof, so that the displacement of the first actual alignment marks 121 along the X-direction cannot be effectively aligned.
With continued reference to fig. 2c, in this embodiment, the boundary of the first direction displacement region 210 is located at the center of the target wafer as a vertex, and the first angles α are located at two sides of the warp direction 130. Optionally, the first angle α is 45 °. The second direction displacement zone 220 is located in the target wafer area between the two first direction displacement zones 210.
Step S14: and (3) remaining effective alignment marks, and setting supplementary alignment marks at the positions of the ineffective alignment marks, so that the supplementary alignment marks in the first direction displacement area extend along the first direction, and the supplementary alignment marks in the second direction displacement area extend along the second direction.
Optionally, an alignment layer may be manufactured again on the target wafer surface shown in fig. 2c, where the alignment layer includes a plurality of alignment marks, where the alignment marks include the reserved valid alignment marks and the newly added supplementary alignment marks, and the supplementary alignment marks may be set at the positions of the original invalid alignment marks.
Referring to fig. 2d, which is a schematic diagram of the step S14 based on fig. 2c, it can be seen from fig. 2d that the alignment marks with dot-like filling are complementary alignment marks, and the unfilled alignment marks are original effective alignment marks. The original invalid alignment mark in the first direction displacement region 210 in fig. 2d is replaced with the complementary alignment mark extending in the Y direction, and the original invalid alignment mark in the second direction displacement region 220 in fig. 2d is replaced with the complementary alignment mark extending in the X direction, so that the displacement of the alignment marks in the first direction displacement region 210 and the second direction displacement region 220 relative to the ideal alignment mark is consistent with the extending direction of the alignment mark, and even if the wafer is warped, accurate alignment can be performed according to the alignment mark.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (6)
1. The method for setting the alignment mark of the warped wafer is characterized by comprising the following steps of:
obtaining warp data of a target wafer, and calculating the warp direction of the target wafer according to the warp data;
acquiring an actual alignment mark distribution diagram of the target wafer, and judging an invalid alignment mark and an effective alignment mark in the actual alignment mark distribution diagram according to an ideal alignment mark distribution diagram; the method comprises the steps of defining an actual alignment mark, of which the extending direction is consistent with the displacement direction relative to an ideal alignment mark, as an effective alignment mark, and defining an actual alignment mark, of which the extending direction is inconsistent with the displacement direction, as an ineffective alignment mark;
determining a first direction displacement area and a second direction displacement area of the target wafer, wherein an actual alignment mark in the first direction displacement area is displaced along a first direction relative to an ideal alignment mark, and an actual alignment mark in the second direction displacement area is displaced along a second direction relative to the ideal alignment mark, and the first direction and the second direction are mutually perpendicular;
a valid alignment mark is reserved, and a supplementary alignment mark is arranged at the position of the invalid alignment mark, so that the supplementary alignment mark in the first direction displacement area extends along the first direction, and the supplementary alignment mark in the second direction displacement area extends along the second direction; the displacement direction of the supplementary alignment mark relative to the ideal alignment mark is consistent with the extension direction of the supplementary alignment mark.
2. The method of claim 1, wherein the first direction is the same as the warp direction of the target wafer.
3. The method of claim 1, wherein the boundary of the first direction displacement zone is located at a position where the first angles on both sides of the warp direction are located with the center of the target wafer as a vertex.
4. The method of claim 3, wherein the first angle is 45 °.
5. The method of claim 3, wherein the first direction displacement regions comprise two first direction displacement regions, and the center of the target wafer is a common vertex.
6. The method of claim 5, wherein the second direction displacement zone is located in a target wafer area between the two first direction displacement zones.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110811805.4A CN113625527B (en) | 2021-07-19 | 2021-07-19 | Method for setting alignment mark of warpage wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110811805.4A CN113625527B (en) | 2021-07-19 | 2021-07-19 | Method for setting alignment mark of warpage wafer |
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| CN113625527B true CN113625527B (en) | 2023-11-07 |
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| CN114038776B (en) * | 2022-01-11 | 2022-06-03 | 广州粤芯半导体技术有限公司 | Method for solving alignment deviation caused by wafer warping deformation |
| CN114373707B (en) * | 2022-03-22 | 2022-06-03 | 广州粤芯半导体技术有限公司 | Taiko wafer conveying method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1019512A (en) * | 1996-07-09 | 1998-01-23 | Nikon Corp | Method for alignment |
| JPH1154407A (en) * | 1997-08-05 | 1999-02-26 | Nikon Corp | Method of registration |
| DE102013017878A1 (en) * | 2013-10-28 | 2015-04-30 | Mühlbauer Ag | Deflection compensation for inscribing plate or bar-shaped objects |
| CN107219721A (en) * | 2012-07-10 | 2017-09-29 | 株式会社尼康 | Mark forming method and device making method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7068833B1 (en) * | 2000-08-30 | 2006-06-27 | Kla-Tencor Corporation | Overlay marks, methods of overlay mark design and methods of overlay measurements |
| US20160048087A1 (en) * | 2014-08-12 | 2016-02-18 | Macronix International Co., Ltd. | Scanner and method for performing exposure process on wafer |
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- 2021-07-19 CN CN202110811805.4A patent/CN113625527B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1019512A (en) * | 1996-07-09 | 1998-01-23 | Nikon Corp | Method for alignment |
| JPH1154407A (en) * | 1997-08-05 | 1999-02-26 | Nikon Corp | Method of registration |
| CN107219721A (en) * | 2012-07-10 | 2017-09-29 | 株式会社尼康 | Mark forming method and device making method |
| DE102013017878A1 (en) * | 2013-10-28 | 2015-04-30 | Mühlbauer Ag | Deflection compensation for inscribing plate or bar-shaped objects |
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