CN113612484A - Method for realizing high-efficiency LDPC error correction algorithm combining hard decision and soft decision - Google Patents

Method for realizing high-efficiency LDPC error correction algorithm combining hard decision and soft decision Download PDF

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CN113612484A
CN113612484A CN202110855199.6A CN202110855199A CN113612484A CN 113612484 A CN113612484 A CN 113612484A CN 202110855199 A CN202110855199 A CN 202110855199A CN 113612484 A CN113612484 A CN 113612484A
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data
decision
read
flash
flash memory
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李国强
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Shenzhen Demingli Electronics Co Ltd
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Shenzhen Demingli Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms

Abstract

The invention discloses a method for realizing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision, which comprises the following steps: under the condition that the read flash data cannot be corrected by the low-density parity check code hard decision mode, continuing to read data behind the flash data which cannot be corrected from the flash, and after the whole page of data read from the flash is read, re-reading from the data section corresponding to the first flash data which cannot be corrected by the hard decision mode through a soft decision mode, and during re-reading, not rewriting the data in the corresponding buffer register for the data section of the correctly read flash data. By the method, the efficiency of reading data from the flash memory can be improved, the reading delay is reduced, and the data throughput rate is improved by improving the decoding efficiency of the low-density parity check code error correction algorithm combining hard decision and soft decision.

Description

Method for realizing high-efficiency LDPC error correction algorithm combining hard decision and soft decision
Technical Field
The invention relates to the technical field of error correction algorithms, in particular to a method for realizing a high-efficiency LDPC error correction algorithm by combining hard decision and soft decision.
Background
In the related art, Error Correction Code (ECC) algorithms are required to correct data stored in a flash memory to ensure that the data is free of errors, and commonly used ECC algorithms include BCH (Bose, Ray-Chaudhuri, and Hocquenghem), a multi-stage, cyclic, Error correction, variable length digital coding (LDPC) algorithm for Correcting multiple random Error patterns, a Low Density Parity Check Code (LDPC) algorithm, and the like.
The existing relatively common flash memories basically need LDPC algorithm with stronger error correction capability. When reading data from the flash memory, the error data is found and corrected after LDPC decoding. The LDPC decoding has two modes of hard decision and soft decision, wherein the hard decision mode is to decode the data read back from the flash memory, if the error data amount is in the error correction capability range, the error correction is directly corrected, if the error correction capability range is exceeded, the error correction failure is reported, and if only the hard decision mode is adopted, the data can not be recovered under the condition. The soft decision mode is that under the condition that the error data amount exceeds the error correction capability range, parameters such as a flash memory reading threshold value and the like are modified and then re-read is carried out, data error probability information is judged according to re-read data, and then the information is input into an LDPC algorithm to be decoded, so that the error correction capability of the LDPC algorithm can be improved, and more error data can be corrected. From the foregoing description, the error correction capability of the soft decision method is stronger, but the error correction time is longer, which results in the decrease of the throughput rate of the LDPC algorithm and sacrifices the highest performance of the error correction algorithm.
The read-write operation of the flash memory is performed in units of pages, the size of one page is generally 4KB (Kilobyte), 8KB or 16KB, and the length of the data coded and decoded by the LDPC algorithm, i.e. the code length, is generally 1KB, 2KB or 4KB, that is, the data read-write of one page is generally performed by multiple LDPC coding and decoding, taking the case of reading one 16KB page of data by 2KB LDPC, the data read of one page needs to be performed by at least 8 times of LDPC decoding, and if the data in error each time is within the error correction capability range of hard decision, the correct data can be recovered by performing the 8 times of LDPC decoding.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an embodiment of an implementation of a conventional LDPC error correction algorithm. As shown in fig. 1, error correction is performed on 7 data in total, D1, D2, D3, D4, D5, D6, and D7. As shown in fig. 1, if the 2 nd decoding D1 exceeds the error correction capability and cannot correct the error, the subsequent data reading operation is stopped, the data corresponding to D1 is re-read after modifying parameters such as flash memory reading threshold, and assuming that the data of D1 is recovered correctly by soft decision after 4 re-reads, the subsequent data can be read continuously from D2. If the error correction cannot be performed again after the D4 is read, then the subsequent data needs to be stopped being read, re-reading the D4, and so on, and if the number of re-reading times is 4, in the above figure, under the condition that the error correction cannot be performed by using hard decisions of D1, D4, and D6, the correct data of the whole page needs to be read by re-reading 12 times in total, the error correction decoding efficiency is general, so that the efficiency of reading data from the flash memory is general, the reading delay is increased, and the data throughput rate is general.
Disclosure of Invention
In view of the above, the present invention provides a method for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision, which can implement improving the efficiency of reading data from a flash memory, reducing read latency, and improving the data throughput by improving the decoding efficiency of a low-density parity-check code error correction algorithm combining hard decision and soft decision.
According to an aspect of the present invention, there is provided a method for implementing an efficient LDPC error correction algorithm combining hard decision and soft decision, comprising: under the condition that the read flash data cannot be corrected in a low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash; after the whole page of data read from the flash memory is read, re-reading is started from a data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode; and during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly.
Wherein, when the low density parity check code hard decision mode fails to correct the error of the read flash memory data, the method for continuously reading the data after the flash memory data which cannot be corrected from the flash memory comprises the following steps: and under the condition that the read flash data cannot be corrected in the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash in a mode of not stopping subsequent data reading from the flash.
After the whole page of data read from the flash memory is completely read, re-reading is started from a data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode, wherein the re-reading comprises the following steps: and after the whole page of data read from the flash memory is completely read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode according to the configured sequence number.
When the flash memory data is read again, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly, and the method comprises the following steps: during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly by marking the data section of the flash memory data which is read correctly according to the marking.
According to another aspect of the present invention, there is provided an apparatus for implementing an efficient LDPC error correction algorithm combining hard decision and soft decision, comprising: the device comprises a reading module, a rereading module and a non-rewriting module; the reading module is used for continuously reading data behind the flash memory data which cannot be corrected from the flash memory under the condition that the read flash memory data cannot be corrected in the low-density parity check code hard judgment mode; the re-reading module is used for starting re-reading from a data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode after the whole page of data read from the flash memory is read; and the non-rewriting module is used for not rewriting the data in the corresponding buffer register for the data section of the flash memory data which is read correctly during the rereading.
The reading module is specifically configured to: and under the condition that the read flash data cannot be corrected in the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash in a mode of not stopping subsequent data reading from the flash.
The rereading module is specifically configured to: and after the whole page of data read from the flash memory is completely read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode according to the configured sequence number.
Wherein the no-rewrite module is specifically configured to: during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly by marking the data section of the flash memory data which is read correctly according to the marking.
According to yet another aspect of the present invention, there is provided a computer apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method for implementing a hard-decision and soft-decision combined efficient LDPC error correction algorithm as described in any one of the above.
According to still another aspect of the present invention, there is provided a computer-readable storage medium storing a computer program, which when executed by a processor, implements a method for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as described in any one of the above.
It can be found that, according to the above scheme, when the read flash data cannot be corrected in the low density parity check code hard decision mode, data after the flash data that cannot be corrected is continuously read from the flash, and after the whole page of data read from the flash is completely read, re-reading is started from the data segment corresponding to the first flash data that cannot be corrected in the hard decision mode in the soft decision mode, and when re-reading is possible, data in the corresponding buffer register is not rewritten for the data segment of the flash data that has been correctly read, so that a mode of improving the decoding efficiency of the low density parity check code error correction algorithm combining hard decision and soft decision can be realized, thereby improving the efficiency of reading data from the flash, reducing the reading delay, and improving the data throughput rate.
Furthermore, the above scheme can continue to read the data after the flash memory data that cannot be corrected from the flash memory without stopping the subsequent data reading from the flash memory under the condition that the read flash memory data cannot be corrected by the low-density parity-check code hard decision mode, so that the advantages of reducing the number of re-reading times of reading the data from the flash memory and improving the decoding efficiency of the hard-decision low-density parity-check code error correction algorithm can be realized.
Furthermore, the above scheme may adopt a manner of configuring the sequential serial numbers for the data segments corresponding to the flash memory data that cannot be subjected to hard decision error correction, and after the whole page of data read from the flash memory is completed, re-reading is started from the data segment corresponding to the first flash memory data that cannot be subjected to hard decision error correction through a soft decision manner according to the configured sequential serial numbers.
Furthermore, according to the scheme, when the data is reread, the data section of the flash memory data which is read correctly is marked, and the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly according to the marked data, so that the advantages of improving the efficiency of reading the data from the flash memory, reducing the reading delay and improving the data passing and spitting rate can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating an embodiment of an implementation of a conventional LDPC error correction algorithm;
FIG. 2 is a flow chart of an embodiment of a method for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention;
FIG. 3 is a schematic diagram illustrating an embodiment of a method for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention;
FIG. 4 is a schematic structural diagram of an embodiment of an apparatus for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of the computer apparatus of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
The invention provides a method for realizing a high-efficiency LDPC error correction algorithm by combining hard decision and soft decision, which can improve the efficiency of reading data from a flash memory, reduce the reading delay and improve the data throughput and spitting rate.
Referring to fig. 2, fig. 2 is a flowchart illustrating an embodiment of a method for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 2 if the results are substantially the same. As shown in fig. 1, the method comprises the steps of:
s201: and under the condition that the read flash data cannot be corrected by the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash.
Wherein, when the low density parity check code hard decision mode fails to correct the error of the read flash memory data, continuing to read data after the flash memory data that fails to correct the error from the flash memory may include:
under the condition that the read flash data cannot be corrected by the low-density parity check code hard decision mode, the subsequent data reading from the flash is not stopped, and the data behind the flash data which cannot be corrected is continuously read from the flash, so that the advantages of reducing the re-reading times of the data read from the flash and improving the decoding efficiency of the hard-decision low-density parity check code error correction algorithm can be realized.
S202: after the whole page of data read from the flash memory is read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode.
After the whole page of data read from the flash memory is completely read, re-reading is started from a data segment corresponding to the first flash memory data which cannot be subjected to hard decision error correction in a soft decision manner, and the method may include:
the method has the advantages that the re-reading times of the data read from the flash memory can be reduced, and the decoding efficiency of the soft-decision low-density parity check code error correction algorithm can be improved.
S203: when the flash memory is read again, the data in the corresponding buffer (buffer register) is not overwritten on the data section of the flash memory data which has been read correctly.
When the data segment of the flash memory data that has been correctly read is not overwritten with the data in the corresponding buffer (buffer register), the method may include:
during rereading, the data section of the flash memory data which is read correctly is marked, and the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly according to the marked data section, so that the advantages of improving the efficiency of reading the data from the flash memory, reducing the reading delay and improving the data passing rate can be realized.
It can be found that, in this embodiment, when the read flash data cannot be corrected in the low density parity check code hard decision manner, data after the flash data that cannot be corrected is continuously read from the flash memory, and after the whole page of data read from the flash memory is completed, re-reading is started from the data segment corresponding to the first flash data that cannot be corrected in the hard decision manner in the soft decision manner, and when re-reading is completed, data in the corresponding buffer register is not rewritten for the data segment of the flash data that has been correctly read, so that a manner of improving the decoding efficiency of the low density parity check code error correction algorithm combining hard decision and soft decision can be implemented, thereby improving the efficiency of reading data from the flash memory, reducing the reading delay, and improving the data throughput rate.
Further, in this embodiment, when the read flash data cannot be corrected in the low density parity check code hard decision manner, the subsequent data reading from the flash memory is not stopped, and the data after the flash data that cannot be corrected is continuously read from the flash memory.
Furthermore, in this embodiment, a method of configuring a sequential number for a data segment corresponding to flash memory data that cannot be subjected to hard decision error correction may be adopted, and after the whole page of data read from the flash memory is completed, re-reading is started from a data segment corresponding to the first flash memory data that cannot be subjected to hard decision error correction in a soft decision manner according to the configured sequential number.
Further, in this embodiment, when the flash memory data is reread, the data segment of the flash memory data that has been read correctly is marked, and the data in the corresponding buffer register is not overwritten to the data segment of the flash memory data that has been read correctly according to the marked data segment, so that the advantages of improving the efficiency of reading data from the flash memory, reducing the reading delay, and improving the data throughput and throughput rate can be achieved.
The present embodiment is illustrated below:
referring to fig. 3, fig. 3 is a schematic diagram illustrating an embodiment of a method for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention. As shown in fig. 3, assuming that D1 still needs to re-read 4 times to obtain correct data, in the best case, the data of D4 and D6 also obtain correct data in the 4 re-reading processes, and then obtain correct data of the whole page only by re-reading 4 times, which greatly improves the efficiency of reading data from the flash memory, reduces the reading delay, and improves the data throughput rate compared with the prior art.
As shown in fig. 3, error correction is performed on 7 data in total, D1, D2, D3, D4, D5, D6, and D7. As shown in fig. 3, after the data read from the whole page is decoded in a hard decision manner, D1, D4, and D6 cannot correct errors and need to be reread, and then the data D1 to D7 are reread from D1, because the data in D2, D3, D5, and D7 in the buffer are already the recovered correct data, the reread data does not overwrite the data in D2, D3, D5, and D7 in the buffer, and only covers the data segments of D1, D4, and D6. By doing so, it is also possible to prevent the originally correct data segments of D2, D3, D5, and D7 from being read incorrectly during the re-reading process, and rewrite the data in the buffer into erroneous data, so as to improve the efficiency of reading data from the flash memory, reduce the reading delay, and improve the data throughput rate by improving the decoding efficiency of the error correction algorithm of the low density parity check code combining hard decision and soft decision.
The invention also provides a device for realizing the high-efficiency LDPC error correction algorithm by combining hard decision and soft decision, which can improve the efficiency of reading data from the flash memory, reduce the reading delay and improve the data throughput and spitting rate.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of an apparatus for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision according to the present invention. In this embodiment, the device 40 for implementing the high-efficiency LDPC error correction algorithm combining hard decision and soft decision includes a reading module 41, a re-reading module 42, and an overwriting module 43.
The reading module 41 is configured to continue reading data subsequent to the flash data that cannot be error-corrected from the flash memory when the flash data that is read cannot be error-corrected in the low density parity check code hard decision manner.
The rereading module 42 is configured to start rereading from a data segment corresponding to the first flash data that cannot be corrected by hard decision in a soft decision manner after the whole page of data read from the flash memory is read.
The non-rewrite module 43 is configured to, during rereading, not rewrite data in the corresponding buffer register with a data segment of the flash data that has been correctly read.
Optionally, the reading module 41 may be specifically configured to:
and under the condition that the read flash data cannot be corrected by the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash by adopting a mode of not stopping subsequent data reading from the flash.
Optionally, the rereading module 42 may be specifically configured to:
and after the data of the whole page read from the flash memory is read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode according to the configured sequence number.
Optionally, the non-writing-over module 43 may be specifically configured to:
during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly by marking the data section of the flash memory data which is read correctly according to the marking.
Each unit module of the apparatus 40 for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision may respectively execute corresponding steps in the above method embodiments, and therefore, details of each unit module are not described herein, and please refer to the description of the corresponding steps above in detail.
The present invention further provides a computer device, as shown in fig. 5, comprising: at least one processor 51; and a memory 52 communicatively coupled to the at least one processor 51; the memory 52 stores instructions executable by the at least one processor 51, and the instructions are executed by the at least one processor 51 to enable the at least one processor 51 to perform the implementation of the above-described hard-decision and soft-decision combined high efficiency LDPC error correction algorithm.
Wherein the memory 52 and the processor 51 are coupled in a bus, which may comprise any number of interconnected buses and bridges, which couple one or more of the various circuits of the processor 51 and the memory 52 together. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 51 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 51.
The processor 51 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And the memory 52 may be used to store data used by the processor 51 in performing operations.
The present invention further provides a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.
It can be found that, according to the above scheme, when the read flash data cannot be corrected in the low density parity check code hard decision mode, data after the flash data that cannot be corrected is continuously read from the flash, and after the whole page of data read from the flash is completely read, re-reading is started from the data segment corresponding to the first flash data that cannot be corrected in the hard decision mode in the soft decision mode, and when re-reading is possible, data in the corresponding buffer register is not rewritten for the data segment of the flash data that has been correctly read, so that a mode of improving the decoding efficiency of the low density parity check code error correction algorithm combining hard decision and soft decision can be realized, thereby improving the efficiency of reading data from the flash, reducing the reading delay, and improving the data throughput rate.
Furthermore, the above scheme can continue to read the data after the flash memory data that cannot be corrected from the flash memory without stopping the subsequent data reading from the flash memory under the condition that the read flash memory data cannot be corrected by the low-density parity-check code hard decision mode, so that the advantages of reducing the number of re-reading times of reading the data from the flash memory and improving the decoding efficiency of the hard-decision low-density parity-check code error correction algorithm can be realized.
Furthermore, the above scheme may adopt a manner of configuring the sequential serial numbers for the data segments corresponding to the flash memory data that cannot be subjected to hard decision error correction, and after the whole page of data read from the flash memory is completed, re-reading is started from the data segment corresponding to the first flash memory data that cannot be subjected to hard decision error correction through a soft decision manner according to the configured sequential serial numbers.
Furthermore, according to the scheme, when the data is reread, the data section of the flash memory data which is read correctly is marked, and the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly according to the marked data, so that the advantages of improving the efficiency of reading the data from the flash memory, reducing the reading delay and improving the data passing and spitting rate can be realized.
In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A method for realizing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision is characterized by comprising the following steps:
under the condition that the read flash data cannot be corrected in a low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash;
after the whole page of data read from the flash memory is read, re-reading is started from a data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode;
and during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly.
2. The method for implementing a hard-decision and soft-decision combined high-efficiency LDPC error correction algorithm as claimed in claim 1, wherein when the low-density parity-check code hard-decision manner fails to correct errors in the read flash data, continuing to read data subsequent to the flash data that fails to correct errors from the flash memory comprises:
and under the condition that the read flash data cannot be corrected in the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash in a mode of not stopping subsequent data reading from the flash.
3. The method for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as claimed in claim 1, wherein the re-reading from the data segment corresponding to the first flash data that cannot be error-corrected by hard-decision in a soft-decision manner after the whole page of data read from the flash memory is completed, comprises:
and after the whole page of data read from the flash memory is completely read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode according to the configured sequence number.
4. The method for implementing a hard-decision and soft-decision combined high-efficiency LDPC error correction algorithm as claimed in claim 1, wherein the step of not overwriting data in a corresponding buffer register with respect to a data segment of flash memory data that has been correctly read during the re-reading comprises:
during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly by marking the data section of the flash memory data which is read correctly according to the marking.
5. An apparatus for implementing a high-efficiency LDPC error correction algorithm combining hard decision and soft decision, comprising:
the device comprises a reading module, a rereading module and a non-rewriting module;
the reading module is used for continuously reading data behind the flash memory data which cannot be corrected from the flash memory under the condition that the read flash memory data cannot be corrected in the low-density parity check code hard judgment mode;
the re-reading module is used for starting re-reading from a data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode after the whole page of data read from the flash memory is read;
and the non-rewriting module is used for not rewriting the data in the corresponding buffer register for the data section of the flash memory data which is read correctly during the rereading.
6. The apparatus for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as claimed in claim 5, wherein the reading module is specifically configured to:
and under the condition that the read flash data cannot be corrected in the low-density parity check code hard decision mode, continuously reading data behind the flash data which cannot be corrected from the flash in a mode of not stopping subsequent data reading from the flash.
7. The apparatus for implementing a hard-decision and soft-decision combined high-efficiency LDPC error correction algorithm as claimed in claim 5, wherein the re-reading module is specifically configured to:
and after the whole page of data read from the flash memory is completely read, re-reading is started from the data segment corresponding to the first flash memory data which can not be subjected to hard decision error correction in a soft decision mode according to the configured sequence number.
8. The apparatus for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as claimed in claim 5, wherein said non-write module is specifically configured to:
during rereading, the data in the corresponding buffer register is not rewritten for the data section of the flash memory data which is read correctly by marking the data section of the flash memory data which is read correctly according to the marking.
9. A computer device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as claimed in any one of claims 1 to 4.
10. A computer-readable storage medium, characterized in that a computer program is stored, which when executed by a processor implements the method for implementing a hard-decision and soft-decision combined high efficiency LDPC error correction algorithm as claimed in any one of claims 1 to 4.
CN202110855199.6A 2021-07-27 2021-07-27 Method for realizing high-efficiency LDPC error correction algorithm combining hard decision and soft decision Pending CN113612484A (en)

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