CN113611735A - Stacked grid MOS field effect transistor based on SOI process and preparation method - Google Patents

Stacked grid MOS field effect transistor based on SOI process and preparation method Download PDF

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CN113611735A
CN113611735A CN202110893933.8A CN202110893933A CN113611735A CN 113611735 A CN113611735 A CN 113611735A CN 202110893933 A CN202110893933 A CN 202110893933A CN 113611735 A CN113611735 A CN 113611735A
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photoresist
sio
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buffer layer
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刘红侠
杨亚芳
陈树鹏
王树龙
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention relates to a stacked grid MOS field effect transistor based on an SOI process and a preparation method thereof, which mainly solve the problem of poor reliability of conventional devices. It includes from bottom to top: the transistor comprises an N-type substrate layer (1), a buried oxide layer (2), a body region (3), a gate oxide layer (8), a silicon nitride resistance layer (9) and a polycrystalline silicon layer (10); shallow trench isolation structures (4) are arranged on two sides of the body region (3); both sides of the polysilicon layer (10) are Si3N4A sidewall (11); si3N4A lightly doped source drain region (5) is arranged below the side wall (11); a source active region (7) is arranged between the left side of the lightly doped source drain region (5) and the right side of the shallow trench isolation structure (4), and a drain active region (6) is arranged between the right side of the lightly doped source drain region (5) and the left side of the shallow trench isolation structure (4). The invention is due to the guideThe silicon nitride resistance layer is added, so that the NBTI effect in the device is effectively inhibited, the reliability of the device is improved, and the silicon nitride resistance layer can be used for manufacturing a semiconductor integrated circuit.

Description

Stacked grid MOS field effect transistor based on SOI process and preparation method
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a MOS field effect transistor which can be used for manufacturing a semiconductor integrated circuit.
Background
As the integration degree of semiconductor integrated circuits is continuously increased, the feature size of MOS devices is smaller, however, the operating voltage of the MOS devices cannot be reduced proportionally while the device size is reduced, which causes the electric field of the gate oxide layer to be relatively increased, thereby causing some device reliability problems, such as hot carrier effect HCI and negative bias instability effect NBTI, to become more serious. The NBTI effect is degradation of a series of electrical parameters caused by applying a negative bias voltage to the PMOS device at a high temperature, and includes negative drift of a threshold voltage, reduction of transconductance, reduction of leakage current, and the like, so that the PMOS device is more prone to failure and has lower reliability.
The NBTI effect is mainly due to Si/SiO2The formation of interface states, in which hydrogen and water vapor are the two main species responsible for the NBTI effect. As the thickness of the gate oxide layer is reduced, the NBTI effect has a greater and greater influence on the reliability of the PMOS device, and how to effectively suppress the NBTI effect becomes a serious challenge in the semiconductor industry.
In the prior art, NBTI effect in PMOS devices is usually suppressed by two methods, wherein the first method is to improve PMOS device reliability by reducing boron diffusion in PMOS by nitrogen doping and nitridation processes in gate oxide, but the nitrogen content needs to be controlled because nitrogen above the nominal concentration leads to enhanced NBTI degradation due to increased fixed charge density in the dielectric layer. The second method is to inject fluorine ions into the gate oxide layer to inhibit the NBTI effect in the PMOS device, but the Si-F bond may become a defect source in the gate dielectric layer due to the excessively high fluorine content to cause the breakdown of the gate oxide layer, thereby reducing the reliability of the device.
Both of the above methods require precise control of the concentration of the doped ions, increasing process difficulty and manufacturing cost.
Disclosure of Invention
The invention aims to provide a stacked gate MOS field effect transistor based on an SOI (silicon on insulator) process and a preparation method thereof, aiming at overcoming the defects of the prior art, so that the NBTI (negative bias temperature instability) effect in an MOS (metal oxide semiconductor) device is inhibited by a gate structure formed by combining a polycrystalline silicon layer and a titanium nitride barrier layer, the reliability of the MOS device is improved, and the process difficulty and the cost in the manufacturing process of the device are reduced.
The technical scheme for realizing the purpose of the invention is as follows:
1. a stacked layer grid MOS field effect transistor based on SOI technology comprises an N-type substrate layer (1), a buried oxide layer (2), a body region (3), a gate oxide layer (8) and a polysilicon layer (10) from bottom to top; the two sides of the body region (3) are provided with shallow groove isolation structures (4); the polysilicon layer (10) is flanked by Si3N4A sidewall (11); the Si is3N4A lightly doped source drain region (5) is arranged below the side wall (11); source electrode active region (7) is between this light doping source drain region (5) left side and shallow slot isolation structure (4) right side, is drain electrode active region (6) between this light doping source drain region (5) right side and shallow slot isolation structure (4) left side, its characterized in that:
a titanium nitride barrier layer (9) with the thickness of 2-5nm is added between the gate oxide layer (8) and the polycrystalline silicon layer (10) to inhibit the NBTI effect in the MOS device and improve the reliability of the MOS device.
Preferably, the N-type substrate layer (1) is doped with a dopant concentration of 1 × 1015cm-3An N-type ion of (1); the body region (3) is doped with a concentration of 5 × 1017cm-3Arsenic ion of (4); the polysilicon layer (10) is doped with a concentration of 1 × 1019cm-3-1×1020cm-3Boron ions of (2);
preferably, the lightly doped source/drain region (5) is doped with a dopant concentration of 1 × 1018-1×1019cm-3Boron ions of (2); the drain active region (6) and the source active region (7) are doped with a concentration of 1 × 1019-1×1020cm-3Boron ions of (2).
Preferably, the thickness of the buried oxide layer (2) is 100-200 nm; the thickness of the gate oxide layer (8) is 2-4 nm.
2. A preparation method of a stacked grid MOS field effect transistor based on an SOI process is characterized by comprising the following steps:
1) preparing an SOI substrate:
1a) selecting two silicon wafers with the same size, forming a buried oxide layer (2) on the first silicon wafer by using a dry oxygen oxidation method, and then carrying out activation treatment on the silicon wafers;
1b) h is to be+Implanting ions into a second silicon wafer, and performing low-temperature bonding treatment and heat treatment on the activated first silicon wafer and the silicon wafer to form an SOI (silicon on insulator) substrate;
2) removing the silicon layer on the SOI substrate by a wet etching process, and then carrying out ion doping on the SOI substrate to obtain an N-type substrate layer (1);
3) epitaxially growing a silicon layer on the buried oxide layer (2), and doping the silicon layer to form a body region (3);
4) preparing a shallow trench isolation structure (4):
4a) growing a first SiO layer over the body region (3) by dry oxygen oxidation2A buffer layer of SiO2Growing first Si on the buffer layer3N4A protective layer on the Si3N4Coating photoresist on the protective layer;
4b) removing the single crystal silicon layer and the first SiO on both sides of the body region (3) by exposure and etching2Buffer layer, first Si3N4Forming an isolation region groove by the protective layer and the photoresist;
4c) filling SiO in the isolation region groove2Forming a shallow trench isolation structure (4);
5) preparing a gate oxide layer (8) above the body region (3) by using a dry oxygen oxidation method;
6) preparing a stacked gate:
6a) generating a titanium nitride barrier layer (9) on the gate oxide layer (8) by using a radio frequency sputtering method;
6b) depositing a layer of polycrystalline silicon on the barrier layer (9) of titanium nitride by chemical vapour deposition and growing a second SiO on top of the polycrystalline silicon by a dry oxygen oxidation process2A buffer layer, and spin-coating photoresist on the buffer layer;
6c) etching an injection window of the grid on the photoresist by exposure, then carrying out ion injection on the window to form a heavily doped polysilicon layer (10), completing the preparation of the stacked grid, and removing the residual photoresist and the second SiO2A buffer layer;
7) preparing a lightly doped source drain region (5):
7a) growing a third SiO layer over the polysilicon layer (10) and the body region (3) by dry oxygen oxidation2A buffer layer on the SiO2Photoresist is coated on the buffer layer in a spinning mode;
7b) etching an injection window of the lightly doped source/drain region on the photoresist on the two sides of the polysilicon layer (10) and above part of the body region (3) by exposure, then carrying out ion injection on the window to obtain the lightly doped source/drain region (5), and removing the residual photoresist and the third SiO2A buffer layer;
8) preparation of Si3N4A sidewall (11);
8a) growing fourth SiO on two sides of the grid and above the body region (3) by a dry oxygen oxidation method2A buffer layer, and growing a second Si on the buffer layer3N4A protective layer, and coating photoresist on the protective layer;
8b) etching an injection window on the photoresist above the lightly doped source drain region (5) by exposure, and aligning Si in the window3N4The protective layer is subjected to reactive ion etching to form Si3N4Side wall (11) and removing residual fourth SiO2Buffer layer, second Si3N4A protective layer and a photoresist;
9) preparing a drain active region (6) and a source active region (7):
9a) by dry oxygen oxidation on Si3N4Fifth SiO grows on two sides of the side wall (11) and above the body region (3)2A buffer layer, wherein photoresist is spin-coated on the buffer layer;
9b) by exposure to Si3N4Etching an injection window on the photoresist on the two sides of the side wall (11), then carrying out ion injection on the injection window to form a drain active region (6) and a source active region (7), and removing the residual fifth SiO2Buffer layerAnd photoresist to complete the device fabrication.
Compared with the prior art, the invention has the following advantages:
1. because the stacked gate structure is introduced, the diffusion of impurities in the gate can be blocked by the titanium nitride barrier layer, and the Si/SiO ratio is improved2The interface quality reduces fixed charges in the gate oxide layer and trap charges at the interface, further inhibits the NBTI effect in the MOS device, and enhances the reliability of the MOS device.
2. Compared with the prior art, the invention only adds a titanium nitride barrier layer generated by a radio frequency sputtering method, thereby not increasing complex process and high cost, and not increasing area, and not influencing the integration level of the integrated circuit.
Drawings
FIG. 1 is a schematic diagram of a conventional device structure in the prior art;
FIG. 2 is a block diagram of a stacked gate MOS FET based on SOI process according to the present invention;
fig. 3 is an enlarged partial cross-sectional view of the field effect transistor of fig. 2;
FIG. 4 is a schematic flow chart of a method of fabricating the field effect transistor of FIG. 2 according to the present invention;
FIG. 5 is a graph showing the time-dependent change in interface trap concentration for a device of the present invention;
FIG. 6 is a graph showing the results of comparison of a conventional device with a device of example 1 of the present invention with respect to NBTI degradation;
FIG. 7 is a graph showing the results of comparison between a conventional device and a device according to example 2 of the present invention with respect to NBTI degradation.
Detailed Description
The following describes in detail specific embodiments and effects of the present invention with reference to the drawings.
Referring to fig. 1, the conventional device structure includes, from bottom to top: the structure comprises an N-type substrate layer 1, a buried oxide layer 2, a body region 3, a gate oxide layer 8 and a polycrystalline silicon layer 10; shallow trench isolation structures 4 are arranged on two sides of the body region 3; the polysilicon layer 10 is Si on both sides3N4 A side wall 11; the Si is3N4A lightly doped source/drain region 5 is arranged below the side wall 11;a source active region 7 is arranged between the left side of the lightly doped source drain region 5 and the right side of the shallow trench isolation structure 4, and a drain active region 6 is arranged between the right side of the lightly doped source drain region 5 and the left side of the shallow trench isolation structure 4.
Referring to fig. 2 and fig. 3, the device structure of the present invention is that a titanium nitride barrier layer 9 with a thickness of 2-5nm is added between the gate oxide layer 8 and the polysilicon layer 10 in fig. 1, so as to inhibit the NBTI effect in the MOS device and improve the reliability of the MOS device.
Referring to fig. 4, the method of the present invention for fabricating the field effect transistor shown in fig. 2 gives the following three examples:
example 1, a titanium nitride barrier layer having a thickness of 2nm, a gate oxide layer having a thickness of 2nm, and a lightly doped source/drain region having a doping concentration of 1 × 10 was fabricated18cm-3The stacked layer grid MOS field effect transistor.
Step 1, an SOI substrate is prepared.
1a) Selecting two silicon wafers with the same size, growing a buried oxide layer with the thickness of 145nm on the first silicon wafer at 1250 ℃ by using a dry oxygen oxidation method, activating the silicon wafers, and then carrying out H treatment on the second silicon wafer+Ion implantation, and bonding the two silicon wafers after ion implantation is completed;
1b) and after bonding is finished, carrying out heat treatment on the bonded piece to form an SOI substrate, further carrying out high-temperature annealing treatment at 1100 ℃ to increase bonding strength, and then carrying out flatness treatment on the silicon film surface by adopting chemical mechanical polishing to finish the preparation of the SOI substrate.
Step 2, removing the silicon layer on the SOI substrate by a wet etching process, and carrying out concentration of 1 × 10 on the substrate15cm-3And doping the N-type ions to obtain the N-type substrate layer.
Step 3, growing a silicon layer on the SOI substrate by an epitaxial method, and subjecting the silicon layer to a concentration of 5 × 1017cm-3And doping the arsenic ions to form a body region.
And 4, preparing the shallow trench isolation structure.
4a) Growing a layer of SiO by dry oxygen oxidation over the bulk region at a temperature of 1250 DEG C2A buffer layer, and growing Si on the buffer layer3N4A protective layer, and a layer of photoresist is spin-coated on the protective layer;
4b) removing silicon layer and SiO on two sides of body region by exposure and etching2Buffer layer, Si3N4The protective layer and the photoresist form a shallow trench isolation region groove;
4c) growing SiO in shallow trench isolation groove at 550 ℃ by using chemical vapor deposition method2And performing chemical mechanical polishing, cleaning the photoresist, and removing SiO in hot phosphoric acid solution at 185 deg.C2Buffer layer and Si3N4And a protective layer.
And 5, preparing a gate oxide layer.
5a) Growing a sacrificial oxide layer above the body region at 1200 ℃ by a dry oxygen oxidation method, and removing the sacrificial oxide layer by using an HF solution to enable the surface of the body region to be cleaner;
5b) and growing a silicon dioxide layer with the thickness of 2nm above the body region at the temperature of 1200 ℃ by a dry oxygen oxidation method, wherein the silicon dioxide layer is the gate oxide layer.
And 6, preparing the stacked gate.
6a) Generating a titanium nitride barrier layer with the thickness of 2nm above the gate oxide layer by using a radio frequency sputtering method;
6b) growing a polysilicon layer on the titanium nitride barrier layer at 600 deg.C by chemical vapor deposition, and growing a SiO layer on the polysilicon layer by dry oxidation2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
6c) etching an implantation window on the photoresist by exposure, and performing a concentration of 1 × 10 on the window19cm-3The boron ion is injected to form a heavily doped polysilicon layer, the preparation of the stacked grid is completed, and then the residual photoresist and SiO are cleaned2A buffer layer.
And 7, preparing the lightly doped source drain region.
7a) Growing SiO over the polysilicon layer and the bulk region by dry oxygen oxidation at a temperature of 1250 deg.C2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
7b) etching an injection window of the lightly doped source/drain region on the photoresist on two sides of the gate and above part of the body region by exposure, and injecting a peak concentration of 1 × 10 into the window18cm-3The impurity injection distribution of the boron ions is analyzed by adopting a Gaussian function to form a lightly doped source drain region, and then the residual photoresist and SiO are cleaned2A buffer layer.
Step 8, preparation of Si3N4And a side wall.
8a) Growing SiO on two sides of grid and over body region by dry oxygen oxidation method2A buffer layer, and growing Si on the buffer layer3N4A protective layer, and a layer of photoresist is spin-coated on the protective layer;
8b) etching an injection window on the photoresist on two sides of the grid electrode and above part of the body region by exposure, and etching Si in the window3N4The protective layer is subjected to reactive ion etching to form Si3N4Side wall, then removing residual SiO2Buffer layer, Si3N4A protective layer and a photoresist.
And 9, preparing a drain electrode active region and a source electrode active region.
9a) By dry oxygen oxidation on Si3N4Growing a layer of SiO on two sides of the side wall and above the body region2A buffer layer, on which a layer of photoresist is spin-coated;
9b) by exposure to Si3N4Etching an injection window of the source and drain region on the photoresist on the two sides of the side wall, and performing peak concentration 1 multiplied by 10 inside the window20cm-3The impurity implantation distribution is analyzed by adopting a Gaussian function to form a drain active region and a source active region, and finally, the residual SiO is cleaned2A buffer layer and photoresist.
And step 10, after the source and drain regions are doped, removing surface oxides by using hydrofluoric acid (HF) solution, and finishing the manufacture of the stacked layer grid MOS field effect transistor based on the SOI process.
Example 2, a titanium nitride barrier layer having a thickness of 3nm, a gate oxide layer having a thickness of 3nm, and a lightly doped source/drain region having a doping concentration of 5 × 10 was fabricated18cm-3The stacked layer grid MOS field effect transistor.
Step one, preparing an SOI substrate.
The specific implementation of this step is the same as step 1 in example 1.
And step two, preparing an N-type substrate layer.
The specific implementation of this step is the same as step 2 in example 1.
And step three, preparing a body region.
The specific implementation of this step is the same as step 3 in example 1.
And step four, preparing the shallow trench isolation structure.
The specific implementation of this step is the same as step 4 in example 1.
And step five, preparing the gate oxide layer.
5.1) growing a sacrificial oxide layer above the body region at 1200 ℃ by a dry oxygen oxidation method, and removing the sacrificial oxide layer by using an HF solution to ensure that the surface of the body region is cleaner;
5.2) growing a silicon dioxide layer with the thickness of 3nm above the body region at 1200 ℃ by a dry oxygen oxidation method, wherein the silicon dioxide layer is the gate oxide layer.
And step six, preparing the stacked grid.
6.1) generating a titanium nitride barrier layer with the thickness of 3nm above the gate oxide layer by using a radio frequency sputtering method;
6.2) growing a layer of polycrystalline silicon on the barrier layer of titanium nitride by chemical vapour deposition at a temperature of 600 ℃ and growing a layer of SiO on the layer of polycrystalline silicon by dry oxygen oxidation2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
6.3) etching an implantation window in the photoresist by exposure and performing a concentration of 5X 10 in the window19cm-3The boron ion is injected to form a heavily doped polysilicon layer, the preparation of the stacked grid is completed, and then the residual photoresist and SiO are cleaned2A buffer layer.
And step seven, preparing the lightly doped source drain region.
7.1) by dry oxygen oxidation at a temperature of 1250 deg.CGrowing SiO on polysilicon layer and body region2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
7.2) etching an injection window of the lightly doped source and drain region on the photoresist on two sides of the grid electrode and above part of the body region through exposure, and injecting 5 multiplied by 10 peak concentration into the window18cm-3The impurity injection distribution of the boron ions is analyzed by adopting a Gaussian function to form a lightly doped source drain region, and then the residual photoresist and SiO are cleaned2A buffer layer.
Step eight, respectively preparing Si on two sides of the grid3N4And a side wall.
The specific implementation of this step is the same as step 8 in example 1.
And step nine, preparing a drain electrode active region and a source electrode active region.
The specific implementation of this step is the same as step 9 in example 1.
And step ten, after the source and drain region is doped, removing surface oxide by using hydrofluoric acid (HF) solution, and finishing the manufacture of the stacked layer grid MOS field effect transistor based on the SOI process.
Example 3, a titanium nitride barrier layer was fabricated to have a thickness of 5nm, a gate oxide layer thickness of 4nm, and a lightly doped source/drain doping concentration of 1 × 1019cm-3The stacked layer grid MOS field effect transistor.
And step A, preparing an SOI substrate.
The specific implementation of this step is the same as step 1 in example 1.
And step B, preparing an N-type substrate layer.
The specific implementation of this step is the same as step 2 in example 1.
And step C, preparing a body region.
The specific implementation of this step is the same as step 3 in example 1.
And D, preparing the shallow slot isolation structure.
The specific implementation of this step is the same as step 4 in example 1.
And E, preparing a gate oxide layer.
E1) Growing a sacrificial oxide layer above the body region at 1200 ℃ by a dry oxygen oxidation method, and removing the sacrificial oxide layer by using an HF solution to ensure that the surface of the body region is cleaner;
E2) and growing a silicon dioxide layer with the thickness of 4nm above the body region at 1200 ℃ by a dry oxygen oxidation method, wherein the silicon dioxide layer is the gate oxide layer.
And F, preparing a stacked layer grid.
F1) Generating a titanium nitride barrier layer with the thickness of 5nm above the gate oxide layer by using a radio frequency sputtering method;
F2) growing a layer of polysilicon on the titanium nitride barrier layer by chemical vapor deposition at a temperature of 600 deg.C, and growing a layer of SiO on the polysilicon layer by dry oxygen oxidation2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
F3) etching an implantation window on the photoresist by exposure, and performing a concentration of 1 × 10 on the window20cm-3The boron ion is injected to form a heavily doped polysilicon layer, the preparation of the stacked grid is completed, and then the residual photoresist and SiO are cleaned2A buffer layer.
And G, preparing the lightly doped source drain region.
G1) Growing SiO over the polysilicon layer and the bulk region by dry oxygen oxidation at a temperature of 1250 deg.C2A buffer layer, and a layer of photoresist is spin-coated on the buffer layer;
G2) etching an injection window of the lightly doped source/drain region on the photoresist on two sides of the gate and above part of the body region by exposure, and injecting a peak concentration of 1 × 10 into the window19cm-3The impurity injection distribution of the boron ions is analyzed by adopting a Gaussian function to form a lightly doped source drain region, and then the residual photoresist and SiO are cleaned2A buffer layer.
Step H, respectively preparing Si on two sides of the grid3N4And a side wall.
The specific implementation of this step is the same as step 8 in example 1.
And step I, preparing a drain electrode active region and a source electrode active region.
The specific implementation of this step is the same as step 9 in example 1.
And step J, after the source and drain region is doped, removing surface oxide by using hydrofluoric acid HF solution, and finishing the manufacture of the stacked layer grid MOS field effect transistor based on the SOI process.
The effect of the invention can be further illustrated by the following simulation experiment:
firstly, setting simulation conditions:
stress temperature setting: 400K;
setting stress grid voltage: -2V;
stress time setting: 1s, 10s, 30s, 50s, 100s, 300s, 500s, 1000 s;
during the stress application period, the source electrode, the drain electrode and the substrate are grounded;
transfer characteristic curve test conditions: the drain voltage Vd is set to-0.1V, the gate voltage Vg is set to sweep from 0V to-1.2V, and the others are grounded.
Secondly, simulation content:
simulation 1, which is to respectively perform simulation on the interface trap concentration before and after stress and the time-dependent change relationship of the interface trap concentration before and after stress on the device of embodiment 1 of the present invention by using the simulation parameters, and the result is shown in fig. 5. It can be seen from fig. 5 that the interface trap concentration of the conventional device and the inventive device rapidly increases with the increase of the stress time under the same stress condition, but the interface trap concentration of the inventive device is significantly smaller than that of the conventional device.
Simulation 2, performing electrical characteristic simulation before and after stress on the device of embodiment 1 of the present invention and the conventional device respectively by using the simulation parameters, wherein the result is shown in fig. 6, where fig. 6(a) is a transfer characteristic curve before and after stress of the conventional device, and fig. 6(b) is a transfer characteristic curve before and after stress of the device of embodiment 1; fig. 6(c) is a graph comparing the amount of threshold voltage degradation with time after stress of the conventional device and the device of the present invention, and fig. 6(d) is a graph comparing the amount of saturated leakage current degradation with time after stress of the conventional device and the device of the present invention.
It can be seen from fig. 6(a) and 6(b) that the conventional device and the device of the present invention have degradation such as negative threshold voltage shift, reduced leakage current, reduced transconductance after stress, and the parameter degradation of the device of the present invention is significantly smaller than that of the conventional device.
It can be seen from fig. 6(c) and 6(d) that the threshold voltage degradation amount and the saturation current degradation amount of the conventional device and the device of the present invention increase with the stress time after the stress, but the threshold voltage degradation amount and the saturation current degradation amount of the device of the present invention are significantly smaller than those of the conventional device.
Simulation 3, performing electrical characteristic simulation before and after stress on the device of embodiment 2 of the present invention and the conventional device respectively by using the simulation parameters, and obtaining a result shown in fig. 7, wherein fig. 7(a) is a transfer characteristic curve before and after stress of the conventional device, and fig. 7(b) is a transfer characteristic curve before and after stress of the device of embodiment 2; fig. 7(c) is a graph comparing the amount of threshold voltage degradation with time after stress of the conventional device and the device of the present invention, and fig. 7(d) is a graph comparing the amount of saturated leakage current degradation with time after stress of the conventional device and the device of the present invention.
As can be seen from fig. 7(a) and 7(b), the degradation of negative shift of threshold voltage, reduction of leakage current, and reduction of transconductance occurs in both the conventional device and the device of the present invention, but the degradation of the sensitive parameter of the device of the present invention is significantly smaller than that of the conventional device.
It can be seen from fig. 7(c) and 7(d) that the threshold voltage degradation amount and the saturation leakage current degradation amount of the conventional device and the device of the present invention both increase with the increase of the stress time, but the threshold voltage degradation amount and the saturation leakage current degradation amount of the device of the present invention are significantly smaller than those of the conventional device.
Simulation results show that the device of the invention has the capability of inhibiting the NBTI effect obviously, and under the same stress condition, the threshold voltage degradation amount and the saturation leakage current degradation amount of the device of the invention are both obviously smaller than those of the conventional device, so that the device of the invention has longer service life compared with the conventional device, and the device of the invention has higher reliability compared with the conventional device.
The above three specific examples of the present invention do not constitute any limitation to the present invention, and it is obvious to those skilled in the art that several simple deductions or substitutions can be made without departing from the concept of the present invention, but these should be considered as falling within the protection scope of the present invention.

Claims (8)

1. A stacked layer grid MOS field effect transistor based on SOI technology comprises an N-type substrate layer (1), a buried oxide layer (2), a body region (3), a gate oxide layer (8) and a polysilicon layer (10) from bottom to top; the two sides of the body region (3) are provided with shallow groove isolation structures (4); the polysilicon layer (10) is flanked by Si3N4A sidewall (11); the Si is3N4A lightly doped source drain region (5) is arranged below the side wall (11); source electrode active region (7) is between this light doping source drain region (5) left side and shallow slot isolation structure (4) right side, is drain electrode active region (6) between this light doping source drain region (5) right side and shallow slot isolation structure (4) left side, its characterized in that:
a titanium nitride barrier layer (9) with the thickness of 2-5nm is added between the gate oxide layer (8) and the polycrystalline silicon layer (10) to inhibit the NBTI effect in the MOS device and improve the reliability of the MOS device.
2. The FET of claim 1,
the N-type substrate layer (1) is doped with a concentration of 1 × 1015cm-3An N-type ion of (1);
the body region (3) is doped with a concentration of 5 × 1017cm-3Arsenic ion of (4);
the polysilicon layer (10) is doped with a concentration of 1 × 1019-1×1020cm-3Boron ions of (2).
3. The FET of claim 1,
the lightly doped source/drain region (5) is doped with a concentration of 1 × 1018-1×1019cm-3Boron ions of (2);
the drain active region (6) and the source active region (7) are doped with a concentration of 1 × 1019-1×1020cm-3Boron ions of (2).
4. The FET of claim 1,
the thickness of the buried oxide layer (2) is 100-200 nm;
the thickness of the gate oxide layer (8) is 2-4 nm.
5. A preparation method of a stacked grid MOS field effect transistor based on an SOI process is characterized by comprising the following steps:
1) preparing an SOI substrate:
1a) selecting two silicon wafers with the same size, forming a buried oxide layer (2) on the first silicon wafer by using a dry oxygen oxidation method, and then carrying out activation treatment on the silicon wafers;
1b) h is to be+Implanting ions into a second silicon wafer, and performing low-temperature bonding treatment and heat treatment on the activated first silicon wafer and the silicon wafer to form an SOI (silicon on insulator) substrate;
2) removing the silicon layer on the SOI substrate by a wet etching process, and then carrying out ion doping on the SOI substrate to obtain an N-type substrate layer (1);
3) epitaxially growing a silicon layer on the buried oxide layer (2), and doping the silicon layer to form a body region (3);
4) preparing a shallow trench isolation structure (4):
4a) growing a first SiO layer over the body region (3) by dry oxygen oxidation2A buffer layer of SiO2Growing first Si on the buffer layer3N4A protective layer on the Si3N4Coating photoresist on the protective layer;
4b) removing the single crystal silicon layer and the first SiO on both sides of the body region (3) by exposure and etching2Buffer layer, first Si3N4Forming an isolation region groove by the protective layer and the photoresist;
4c) filling SiO in the isolation region groove2Forming a shallow trench isolation structure (4);
5) preparing a gate oxide layer (8) above the body region (3) by using a dry oxygen oxidation method;
6) preparing a stacked gate:
6a) generating a titanium nitride barrier layer (9) on the gate oxide layer (8) by using a radio frequency sputtering method;
6b) depositing a layer of polycrystalline silicon on the barrier layer (9) of titanium nitride by chemical vapour depositionGrowing a second SiO on the polysilicon by over-dry oxidation2A buffer layer, and spin-coating photoresist on the buffer layer;
6c) etching an injection window of the grid on the photoresist by exposure, then carrying out ion injection on the window to form a heavily doped polysilicon layer (10), completing the preparation of the stacked grid, and removing the residual photoresist and the second SiO2A buffer layer;
7) preparing a lightly doped source drain region (5):
7a) growing a third SiO layer over the polysilicon layer (10) and the body region (3) by dry oxygen oxidation2A buffer layer on the SiO2Photoresist is coated on the buffer layer in a spinning mode;
7b) etching an injection window of the lightly doped source/drain region on the photoresist on the two sides of the polysilicon layer (10) and above part of the body region (3) by exposure, then carrying out ion injection on the window to obtain the lightly doped source/drain region (5), and removing the residual photoresist and the third SiO2A buffer layer;
8) preparation of Si3N4A sidewall (11);
8a) growing fourth SiO on two sides of the grid and above the body region (3) by a dry oxygen oxidation method2A buffer layer, and growing a second Si on the buffer layer3N4A protective layer, and coating photoresist on the protective layer;
8b) etching an injection window on the photoresist above the lightly doped source drain region (5) by exposure, and aligning Si in the window3N4The protective layer is subjected to reactive ion etching to form Si3N4Side wall (11) and removing residual fourth SiO2Buffer layer, second Si3N4A protective layer and a photoresist;
9) preparing a drain active region (6) and a source active region (7):
9a) by dry oxygen oxidation on Si3N4Fifth SiO grows on two sides of the side wall (11) and above the body region (3)2A buffer layer, wherein photoresist is spin-coated on the buffer layer;
9b) by exposure to Si3N4Etching an injection window on the photoresist on the two sides of the side wall (11), and then separating the injection windowSub-implanting to form a drain active region (6) and a source active region (7), and removing the remaining fifth SiO2And (5) buffer layers and photoresist are used for completing the manufacture of the device.
6. The method as claimed in claim 5, wherein the dry oxygen oxidation method used in 1a), 4a), 5), 6b), 7a), 8a) and 9a) is carried out at a temperature of 1100-1250 ℃.
7. The method according to claim 5, wherein the RF sputtering method used in 6a) uses an AC power source with a frequency of 5-30 MHz, the sputtering target is a titanium target, and the reaction gas is nitrogen.
8. The method as claimed in claim 5, wherein the chemical vapor deposition method used in 6b) has a reaction temperature of 550 ℃ and 650 ℃, a reaction pressure of several hundred Pa, and the reactant is silane.
CN202110893933.8A 2021-08-05 2021-08-05 Stacked grid MOS field effect transistor based on SOI process and preparation method Pending CN113611735A (en)

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