CN113611238B - Display control circuit and display system based on 8080 bus interface - Google Patents
Display control circuit and display system based on 8080 bus interface Download PDFInfo
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- CN113611238B CN113611238B CN202110846378.3A CN202110846378A CN113611238B CN 113611238 B CN113611238 B CN 113611238B CN 202110846378 A CN202110846378 A CN 202110846378A CN 113611238 B CN113611238 B CN 113611238B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of display, and provides a display control circuit and a display system based on an 8080 bus interface, wherein the circuit comprises: the main control module comprises: the device comprises a first IO port, a second IO port, a third IO port, an analog chip selection interface, a first data bus interface and a first RGB interface; the main control module simulates a chip selection signal and a write enable signal under a command mode through a first IO port and a second IO port, the chip selection signal under the data mode is simulated after the signal of a data enable end of a first RGB interface is inverted, the write enable signal under the data mode is simulated through a clock signal of the first RGB interface, a command indication signal is simulated through a third IO port, and the first data bus interface is used for transmitting data. The invention adopts the self-contained RGB interface to simulate the 8080 bus interface time sequence, does not need to completely adopt GPIO simulation, and has high speed and high efficiency.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display control circuit and a display system based on an 8080 bus interface.
Background
Common data interfaces in the field of image display include HDMI (High Definition Multimedia Interface), LVDS (Low Voltage Differential Signaling), RGB and 8080 interfaces. 8080 bus and interface are widely used in display field by virtue of simple interface, convenient control, no need of synchronous clock and signal, etc. The 8080 bus interface display device needs to be driven by a main control chip with the 8080 interface.
In the prior art, for a main control chip without an 8080 interface to drive a display device with the 8080 bus interface, the driving of the display device with the 8080 bus interface needs to be realized through GPIO simulation, and the speed is low and the efficiency is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display control circuit and a display system based on an 8080 bus interface, so as to solve the problems in the prior art that a main control chip without an 8080 interface is used for driving a display device with the 8080 bus interface, which needs to be simulated through a GPIO port, and is slow in speed and low in efficiency.
A first aspect of an embodiment of the present invention provides a display control circuit based on an 8080 bus interface, including: a main control module;
the main control module comprises: the device comprises a first IO port, a second IO port, a third IO port, an analog chip selection interface, a first data bus interface and a first RGB interface;
the third IO port of the main control module is used for connecting with a command data selection end of an 8080 interface of an external display device and sending a command indication signal to the display device; the command indication signal is used for indicating the display equipment to work in a command mode or a data mode;
the first IO port of the main control module is used for being connected with a chip selection end of an 8080 interface of the display equipment and sending a chip selection signal in a command mode to the display equipment;
the second IO port of the main control module is used for being connected with a write enable end of an 8080 interface of the display device and sending a write enable signal in a command mode to the display device;
the analog chip selection interface of the main control module is used for being connected with a chip selection end of an 8080 interface of the display equipment and sending a chip selection signal in a data mode to the display equipment; the chip selection signal in the data mode is in phase reversal with a signal output by a data enable end in a first RGB interface of the main control module;
a clock signal end in a first RGB interface of the main control module is used for being connected with a write enable end of an 8080 interface of the display equipment and sending a write enable signal in a data mode to the display equipment;
the first data bus interface of the main control module is used for being connected with a data bus end of an 8080 interface of the display device and sending a parallel data signal to the display device.
Optionally, the main control module includes: the device comprises a first main control chip and a phase inverter;
the first main control chip comprises: a fourth IO port, a fifth IO port, a sixth IO port, a second data bus interface and a second RGB interface;
the fourth IO port of the first main control chip, the fifth IO port of the first main control chip, the sixth IO port of the first main control chip, the second data bus interface of the first main control chip and the second RGB interface of the first main control chip are respectively connected with the first IO port of the main control module, the second IO port of the main control module, the third IO port of the main control module, the first data bus interface of the main control module and the first RGB interface of the main control module in a one-to-one correspondence manner;
a data enabling end in a second RGB interface of the first main control chip is connected with an input end of the phase inverter;
the output end of the phase inverter is connected with the analog chip selection interface of the main control module.
Optionally, the fourth IO port of the first main control chip is multiplexed with the data enable terminal in the second RGB interface of the first main control chip;
and the fifth IO port of the first main control chip is multiplexed with the clock signal end in the second RGB interface of the first main control chip.
Optionally, the inverter is integrated in the first main control chip.
Optionally, the main control module includes: the second main control chip and the auxiliary unit;
the second main control chip comprises: a seventh IO port, an eighth IO port, a ninth IO port, a third data bus interface and a third RGB interface;
a seventh IO port of the second main control chip is connected with the first input end of the auxiliary unit, an eighth IO port of the second main control chip is connected with the second input end of the auxiliary unit, a data enable end in a third RGB interface of the second main control chip is connected with the third input end of the auxiliary unit, a clock signal end in the third RGB interface of the second main control chip is connected with the fourth input end of the auxiliary unit, a ninth IO port of the second main control chip is connected with the third IO port of the main control module, and a third data bus interface of the second main control chip is connected with the first data bus interface of the main control module;
the first output end of the auxiliary unit is used for being connected with a chip selection end of an 8080 interface of the display device and sending a chip selection signal in a command mode and a chip selection signal in a data mode to the display device;
the second output end of the auxiliary unit is used for being connected with a write enable end of an 8080 interface of the display device and sending a write enable signal in a command mode and a write enable signal in a data mode to the display device.
Optionally, the auxiliary unit includes: the device comprises a first single-pole double-throw analog switch, a second single-pole double-throw analog switch, a switching tube, a first resistor and a second resistor;
the first input end of the first single-pole double-throw analog switch is connected with the first end of the switch tube and the second end of the first resistor, the second input end of the first single-pole double-throw analog switch is connected with the first input end of the auxiliary unit, the output end of the first single-pole double-throw analog switch is connected with the first output end of the auxiliary unit, and the enabling end of the first single-pole double-throw analog switch is connected with the third input end of the auxiliary unit;
the first input end of the second single-pole double-throw analog switch is connected with the fourth input end of the auxiliary unit, the second input end of the second single-pole double-throw analog switch is connected with the second input end of the auxiliary unit, the output end of the second single-pole double-throw analog switch is connected with the second output end of the auxiliary unit, and the enabling end of the second single-pole double-throw analog switch is connected with the third input end of the auxiliary unit;
the second end of the switch tube is grounded, and the control end of the switch tube is connected with the third input end of the auxiliary unit through a second resistor;
the second end of the first resistor is connected with an internal power supply.
Optionally, when the enable terminal of the first single-pole double-throw analog switch is at a low level, the first input terminal and the output terminal of the first single-pole double-throw analog switch are gated;
when the enable terminal of the first single-pole double-throw analog switch is at high level, the second input terminal and the output terminal of the first single-pole double-throw analog switch are gated.
Optionally, the main control module further includes: a tenth IO port;
and a frame synchronization signal end in the first RGB interface of the main control module is connected with the tenth IO port of the main control module and used for sending an interrupt signal to the main control module.
Optionally, the display device is an LCD.
A second aspect of an embodiment of the present invention provides a display system, including: a display device having an 8080 interface and a display control circuit based on an 8080 bus interface according to any one of the first aspect of the embodiments of the present invention;
the display control circuit based on the 8080 bus interface is connected with the display device.
The embodiment of the invention provides a display control circuit and a display system based on an 8080 bus interface, wherein the circuit comprises: a main control module; the main control module comprises: the device comprises a first IO port, a second IO port, a third IO port, an analog chip selection interface, a first data bus interface and a first RGB interface; the main control module simulates a chip selection signal and a write enable signal under a command mode through a first IO port and a second IO port, the chip selection signal under the data mode is simulated after the signal of a data enable end of a first RGB interface is inverted, the write enable signal under the data mode is simulated through a clock signal of the first RGB interface, a command indication signal is simulated through a third IO port, and the first data bus interface is used for transmitting data. The embodiment of the invention adopts the self-contained RGB interface to simulate the 8080 bus interface time sequence, does not need to completely adopt GPIO simulation, and has high speed and high efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a timing diagram of an RGB interface;
FIG. 2 is a timing diagram of the 8080 interface;
fig. 3 is a schematic diagram of a display control circuit based on an 8080 bus interface according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a second display control circuit based on an 8080 bus interface according to the embodiment of the present invention;
FIG. 5 is a diagram of a third 8080 bus interface-based display control circuit according to an embodiment of the present invention;
FIG. 6 is a diagram of a fourth display control circuit based on an 8080 bus interface according to the present invention;
FIG. 7 is a timing diagram corresponding to the 8080 bus interface-based display control circuit shown in FIG. 6;
fig. 8 is a schematic diagram of a fifth display control circuit based on an 8080 bus interface according to the present invention;
FIG. 9 is a schematic circuit diagram of an auxiliary unit provided by an embodiment of the present invention;
fig. 10 is a timing diagram corresponding to the 8080 bus interface-based display control circuit shown in fig. 8.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
The screen using the 8080 bus interface generally has a driver chip (such as the ILI9488, the ILI9341, the SSD1963, and the like), the driver chip has a video memory, the upper computer only needs to send display data to the driver chip, and the driver chip first stores the data in the video memory and then displays the data in the video memory on the screen. The screen using the 8080 bus interface has the advantages of simple and convenient control, no need of a clock and a synchronous signal, no need of an upper computer to provide a video Memory, capability of saving an SDRAM (synchronous dynamic Random Access Memory) or an SRAM (Static Random-Access Memory), and suitability for the application of a small-size screen. For example, 240x320 size, with RGB565 mode (16 bit/pixel), plus partial blank area, the required clock speed is around 3 Mbps. The realization is not difficult for the upper computer with the hardware 8080 bus interface, but for the upper computer without the hardware 8080 bus interface, if the realization is realized by a GPIO simulation mode, the speed is very slow, a large amount of CPU resources are consumed, and the efficiency is low.
For a multimedia host computer, an RGB interface is usually provided. Fig. 1 shows a timing diagram of an RGB interface, and fig. 2 shows a timing diagram of an 8080 bus interface. Comparing fig. 1 and fig. 2, it can be seen that the time sequences of the two interfaces have a certain similarity, where the high level of the data enable signal in the RGB interface time sequence is valid, and the low level of the chip select signal in the 8080 interface time sequence is valid, and has a certain similarity; and the clock signal in the RGB interface timing is similar to the write enable signal in the 8080 interface timing.
Based on the above, referring to fig. 3, an embodiment of the present invention provides a display control circuit based on an 8080 bus interface, including: a main control module 1;
the main control module 1 includes: a first IO port GPIO1, a second IO port GPIO2, a third IO port GPIO3, an analog chip selection interface CSX0, a first DATA bus interface DATA1[15 ] and a first RGB interface;
the third IO port GPIO3 of the main control module 1 is configured to be connected to a command data selection port DCX of an 8080 interface of the external display device 2, and send a command indication signal to the display device 2; wherein, the command indication signal is used for indicating the display device 2 to work in a command mode or a data mode;
a first IO port GPIO1 of the main control module 1 is used to connect with a chip selection terminal CSX of an 8080 interface of the display device 2 and send a chip selection signal in a command mode to the display device 2;
the second IO port GPIO2 of the main control module 1 is used for connecting with a write enable WRX of an 8080 interface of the display device 2 and sending a write enable signal in a command mode to the display device 2;
the analog chip selection interface CSX0 of the main control module 1 is used for connecting with the chip selection terminal CSX of the 8080 interface of the display device 2 and sending a chip selection signal in a data mode to the display device 2; the chip selection signal in the data mode is in phase opposition to a signal output by a data enable terminal in a first RGB interface of the main control module 1;
a clock signal terminal CLK1 in the first RGB interface of the main control module 1 is used to connect with a write enable terminal WRX of the 8080 interface of the display device 2 and send a write enable signal in a data mode to the display device 2;
the first DATA bus interface DATA1[15 ] of the main control module 1 is configured to connect with the DATA bus terminal DATA0[15 ] of the 8080 interface of the display device 2.
According to the similarity between the time sequence of the RGB interface and the time sequence of the 8080 interface, a data enable signal output by a data enable end in the RGB interface of the main control module 1 is adopted to invert a chip selection signal in a data mode in the time sequence of the 8080 interface; a clock signal output by a clock signal end in an RGB interface of the main control module 1 is adopted to simulate a write enable signal in a data mode in the 8080 interface time sequence; the first DATA bus interface DATA1[15 ] is directly connected with the DATA bus end DATA0[15 ] of the 8080 interface of the display device 2, and sends a parallel DATA signal; meanwhile, a chip selection signal in a command mode, a write enable signal in the command mode and a command indication signal in the 8080 interface time sequence are simulated by 3 IO modules respectively. The master control module 1 simulates 8080 interface time sequence by using the RGB interface and the IO interface, and IO simulation is not required to be completely adopted, so that CPU resources are saved, and the data transmission speed and efficiency are improved.
The chip selection signal in the data mode output by the analog chip selection interface CSX0 of the main control module 1 is inverted with respect to the signal output by the data enable terminal in the first RGB interface of the main control module 1, and this feature may be implemented by hardware or software, which is not limited in the embodiment of the present invention.
In some embodiments, based on the above, signal inversion may be implemented in hardware. Referring to fig. 4, the main control module 1 may include: a first main control chip 11 and an inverter 12;
the first main control chip 11 includes: a fourth IO port GPIO4, a fifth IO port GPIO5, a sixth IO port GPIO6, a second DATA bus interface DATA2[15 ] and a second RGB interface;
a fourth IO port GPIO4 of the first main control chip 11, a fifth IO port GPIO5 of the first main control chip 11, a sixth IO port GPIO6 of the first main control chip 11, a second DATA bus interface DATA2[15 0] of the first main control chip 11, and a second RGB interface of the first main control chip 11 are connected to the first IO port GPIO1 of the main control module 1, the second IO port GPIO2 of the main control module 1, the third IO port GPIO3 of the main control module 1, the first DATA bus interface DATA1[15 0] of the main control module 1, and the first RGB interface of the main control module 1 in a one-to-one correspondence manner;
a data enable terminal DE2 in the second RGB interface of the first main control chip 11 is connected to an input terminal of the inverter 12;
the output end of the inverter 12 is connected to the analog chip select interface CSX0 of the main control module 1.
In the embodiment of the present invention, an inverter 12 is provided, and inversion of the signal is realized by the inverter 12.
In some embodiments, referring to fig. 5, the fourth IO port GPIO4 of the first main control chip 11 is multiplexed with the data enable terminal DE2 in the second RGB interface of the first main control chip 11;
the fifth IO port GPIO5 of the first main control chip 11 is multiplexed with the clock signal terminal CLK2 in the second RGB interface of the first main control chip 11.
In the embodiment of the present invention, the fourth IO port GPIO4 of the first main control chip 11 is multiplexed with the data enable terminal DE2 in the second RGB interface of the first main control chip 11, and the fifth IO port GPIO5 of the first main control chip 11 is multiplexed with the clock signal terminal CLK2 in the second RGB interface of the first main control chip 11, so that the number of ports is saved, and the connection with the external display device 2 is facilitated.
In some embodiments, referring to fig. 6, the inverter 12 is integrated in the first main control chip 11.
The internal part of the main control chips is provided with an inversion function, and the data enable end DE2 in the second RGB interface of the first main control chip 11 can directly output the inverted signal without independently arranging the inverter 12. Referring to fig. 6, the data enable terminal DE2 in the second RGB interface of the first main control chip 11 is directly connected to the chip select terminal CSX in the 8080 interface of the display device 2.
For example, fig. 7 shows a signal timing diagram of the display control circuit based on the 8080 bus interface shown in fig. 6, which can meet the application requirements of the 8080 bus interface.
In some embodiments, referring to fig. 8, the master control module 1 includes: a second main control chip 13 and an auxiliary unit 14;
the second main control chip 13 includes: a seventh IO port GPIO7, an eighth IO port GPIO8, a ninth IO port GPIO9, a third DATA bus interface DATA3[15 ] and a third RGB interface;
a seventh IO port GPIO7 of the second main control chip 13 is connected to the first input terminal CSX _ GPIO of the auxiliary unit 14, an eighth IO port GPIO8 of the second main control chip 13 is connected to the second input terminal WRX _ GPIO of the auxiliary unit 14, a DATA enable terminal DE3 in the third RGB interface of the second main control chip 13 is connected to the third input terminal CSX _ DE of the auxiliary unit 14, a clock signal terminal CLK3 in the third RGB interface of the second main control chip 13 is connected to the fourth input terminal WRX _ DE of the auxiliary unit 14, a ninth IO port GPIO9 of the second main control chip 13 is connected to the third IO port GPIO3 of the main control module 1, and a third DATA bus interface DATA [15 [ 0] of the second main control chip 13 is connected to the first DATA bus interface DATA1[15 0] of the main control module 1;
a first output terminal CSX _ OUT of the auxiliary unit 14 is configured to be connected to a chip select terminal CSX of an 8080 interface of the display device 2, and send a chip select signal in a command mode and a chip select signal in a data mode to the display device 2;
the second output WRX _ OUT of the auxiliary unit 14 is used for being connected to the write enable WRX of the 8080 interface of the display device 2, and sending a write enable signal in the command mode and a write enable signal in the data mode to the display device 2.
In some embodiments, referring to fig. 9, the auxiliary unit 14 comprises: the circuit comprises a first single-pole double-throw analog switch U1, a second single-pole double-throw analog switch U2, a switch tube Q1, a first resistor R1 and a second resistor R2;
a first input end of the first single-pole double-throw analog switch U1 is connected with a first end of the switch tube Q1 and a second end of the first resistor R1, a second input end of the first single-pole double-throw analog switch U1 is connected with a first input end CSX _ GPIO of the auxiliary unit 14, an output end of the first single-pole double-throw analog switch U1 is connected with a first output end CSX _ OUT of the auxiliary unit 14, and an enable end of the first single-pole double-throw analog switch U1 is connected with a third input end CSX _ DE of the auxiliary unit 14;
a first input end of the second single-pole double-throw analog switch U2 is connected with a fourth input end WRX _ DE of the auxiliary unit 14, a second input end of the second single-pole double-throw analog switch U2 is connected with a second input end WRX _ GPIO of the auxiliary unit 14, an output end of the second single-pole double-throw analog switch U2 is connected with a second output end WRX _ OUT of the auxiliary unit 14, and an enable end of the second single-pole double-throw analog switch U2 is connected with a third input end CSX _ DE of the auxiliary unit 14;
the second end of the switching tube Q1 is grounded, and the control end of the switching tube Q1 is connected with the third input end CSX _ DE of the auxiliary unit 14 through the second resistor R2;
the second terminal of the first resistor R1 is connected to the internal power source VCC.
In the embodiment of the invention, the data enable signal is negated through the switching tube Q1, the chip selection signal in the command mode and the chip selection signal in the data mode are combined to one end to be output by combining the two single-pole double-throw analog switches, and the write enable signal in the command mode and the write enable signal in the data mode are combined to one end to be output. The main control module 1 only reserves four output terminals and is directly connected with the external display device 2, so that the production and the application are convenient.
Referring to fig. 9, the power terminals of the first single-pole double-throw analog switch U1 and the second single-pole double-throw analog switch U2 are both connected to an internal power source VCC; the grounding ends of the first single-pole double-throw analog switch U1 and the second single-pole double-throw analog switch U2 are grounded.
In some embodiments, when the enable terminal of the first single-pole double-throw analog switch U1 is at a low level, the first input terminal and the output terminal of the first single-pole double-throw analog switch U1 are gated;
when the enable terminal of the first single-pole double-throw analog switch U1 is at a high level, the second input terminal and the output terminal of the first single-pole double-throw analog switch U1 are gated.
In some embodiments, the first and second spdt analog switches U1 and U2 may each be of the type BL1551.
In some embodiments, the switching transistor Q1 may be an NPN transistor.
In some embodiments, referring to fig. 6 and 8, the main control module 1 further includes: a tenth IO port GPIO10;
a frame synchronization signal terminal VSYNC _ OUT in the first RGB interface of the main control module 1 is connected to the tenth IO port GPIO10 of the main control module 1, and is configured to send an interrupt signal to the main control module 1.
In the embodiment of the invention, the frame synchronization signal of the RGB interface can be used as self interruption to trigger data transmission. Further, an IO port and a frame synchronization signal terminal in the first main control chip 11 or the second main control chip 13 are respectively connected to the tenth IO port GPIO10 and the frame synchronization signal terminal in the main control module 1 in a one-to-one correspondence manner, which is not described herein again.
Fig. 10 shows a signal timing diagram of the 8080 bus interface-based display control circuit shown in fig. 8, which can also meet the application requirement of the 8080 interface.
In some embodiments, the display device 2 may be an LCD.
With reference to fig. 8, 9 and 10, the operation of the display control circuit based on the 8080 bus interface is described with reference to the specific embodiment.
1. The second main control chip 13 is switched to a GPIO mode, drives the GPIO9 to simulate a command indication signal (high level), drives the third DATA bus interface DATA3[15 ] of the second main control chip to simulate a command of a set/RASET, and is used to set the start position and display area of a screen display (generally set to the range of the whole screen area);
2. waiting for the rising edge of the frame synchronization signal, when detecting the interruption of the rising edge of the frame synchronization signal, the second main control chip 13 switches to the GPIO mode, pulls down the command indication signal (GPIO 9), and enters the command mode; a chip selection signal in a GPIO7 analog command mode, a write enable signal in a GPIO8 analog command mode, a command of a third DATA bus interface DATA3[15 ] analog RAMFR for driving the first main control chip 11
3. After the write command is completed, the second main control chip 13 configures an internal RGB hardware circuit, prepares RGB data which needs to be output by the internal RGB hardware circuit, pulls up a command indication signal (GPIO 9), and enters a data mode;
4. the second main control chip 13 is switched to a DE mode, hardware is started to drive a DATA enable terminal DE3 in the third RGB interface to output a DATA enable signal, a clock signal terminal CLK3 to output a clock signal, and a third DATA bus interface DATA3[15 ] to output a parallel DATA signal, and the second main control chip 13 outputs RGB DATA for one frame;
5. and after the transmission of one frame of data is finished, repeatedly executing the step 2.
Corresponding to any one of the aforementioned display control circuits based on the 8080 bus interface, an embodiment of the present invention further provides a display system, where the display system includes: the display device 2 with the 8080 interface and any one of the display control circuits based on the 8080 bus interface;
the display control circuit based on the 8080 bus interface is connected with the display device 2.
The display system has the advantages of the display control circuit based on the 8080 bus interface, and the details are not repeated herein.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A8080 bus interface-based display control circuit, comprising: a main control module;
the master control module comprises: the device comprises a first IO port, a second IO port, a third IO port, an analog chip selection interface, a first data bus interface and a first RGB interface;
the third IO port of the main control module is used for connecting with a command data selection end of an 8080 interface of an external display device and sending a command indication signal to the display device; wherein the command indication signal is used for indicating the display device to work in a command mode or a data mode;
the first IO port of the main control module is used for being connected with a chip selection end of an 8080 interface of the display equipment and sending a chip selection signal in a command mode to the display equipment;
the second IO port of the main control module is used for being connected with a write enable end of an 8080 interface of the display device and sending a write enable signal in a command mode to the display device;
the analog chip selection interface of the main control module is used for being connected with a chip selection end of an 8080 interface of the display equipment and sending a chip selection signal in a data mode to the display equipment; the chip selection signal in the data mode is opposite to a signal output by a data enable end in a first RGB interface of the main control module;
a clock signal end in the first RGB interface of the main control module is used for connecting with a write enable end of the 8080 interface of the display device and sending a write enable signal in a data mode to the display device;
the first data bus interface of the main control module is used for being connected with a data bus end of an 8080 interface of the display device and sending parallel data signals to the display device.
2. The 8080 bus interface based display control circuit of claim 1, wherein said master control module comprises: the device comprises a first main control chip and a phase inverter;
the first main control chip comprises: a fourth IO port, a fifth IO port, a sixth IO port, a second data bus interface and a second RGB interface;
a fourth IO port of the first main control chip, a fifth IO port of the first main control chip, a sixth IO port of the first main control chip, a second data bus interface of the first main control chip, and a second RGB interface of the first main control chip are respectively connected with the first IO port of the main control module, the second IO port of the main control module, the third IO port of the main control module, the first data bus interface of the main control module, and the first RGB interface of the main control module in a one-to-one correspondence manner;
a data enabling end in a second RGB interface of the first main control chip is connected with an input end of the phase inverter;
and the output end of the phase inverter is connected with the analog chip selection interface of the main control module.
3. The 8080 bus interface based display control circuit of claim 2, wherein a fourth IO port of said first main control chip is multiplexed with a data enable port in a second RGB interface of said first main control chip;
and a fifth IO port of the first main control chip is multiplexed with a clock signal end in the second RGB interface of the first main control chip.
4. The 8080 bus interface based display control circuit of claim 2, wherein said inverter is integrated in said first master control chip.
5. The 8080 bus interface based display control circuit of claim 1, wherein said master control module comprises: the second main control chip and the auxiliary unit;
the second main control chip comprises: a seventh IO port, an eighth IO port, a ninth IO port, a third data bus interface and a third RGB interface;
a seventh IO port of the second main control chip is connected to the first input end of the auxiliary unit, an eighth IO port of the second main control chip is connected to the second input end of the auxiliary unit, a data enable end in a third RGB interface of the second main control chip is connected to the third input end of the auxiliary unit, a clock signal end in the third RGB interface of the second main control chip is connected to the fourth input end of the auxiliary unit, a ninth IO port of the second main control chip is connected to the third IO port of the main control module, and a third data bus interface of the second main control chip is connected to the first data bus interface of the main control module;
the first output end of the auxiliary unit is used for being connected with a chip selection end of an 8080 interface of the display equipment and sending a chip selection signal in the command mode and a chip selection signal in the data mode to the display equipment;
the second output end of the auxiliary unit is configured to be connected to a write enable end of an 8080 interface of the display device, and send a write enable signal in the command mode and a write enable signal in the data mode to the display device.
6. The 8080 bus interface based display control circuit of claim 5, wherein said auxiliary unit comprises: the device comprises a first single-pole double-throw analog switch, a second single-pole double-throw analog switch, a switching tube, a first resistor and a second resistor;
a first input end of the first single-pole double-throw analog switch is connected with a first end of the switch tube and a second end of the first resistor, a second input end of the first single-pole double-throw analog switch is connected with a first input end of the auxiliary unit, an output end of the first single-pole double-throw analog switch is connected with a first output end of the auxiliary unit, and an enabling end of the first single-pole double-throw analog switch is connected with a third input end of the auxiliary unit;
a first input end of the second single-pole double-throw analog switch is connected with a fourth input end of the auxiliary unit, a second input end of the second single-pole double-throw analog switch is connected with a second input end of the auxiliary unit, an output end of the second single-pole double-throw analog switch is connected with a second output end of the auxiliary unit, and an enabling end of the second single-pole double-throw analog switch is connected with a third input end of the auxiliary unit;
the second end of the switch tube is grounded, and the control end of the switch tube is connected with the third input end of the auxiliary unit through the second resistor;
and the second end of the first resistor is connected with an internal power supply.
7. The 8080 bus interface based display control circuit of claim 6, wherein when an enable terminal of said first SPDT analog switch is at a low level, a gate is enabled between a first input terminal and an output terminal of said first SPDT analog switch;
when the enable terminal of the first single-pole double-throw analog switch is at a high level, the second input terminal and the output terminal of the first single-pole double-throw analog switch are gated.
8. The 8080 bus interface based display control circuit of any one of claims 1 to 7, wherein said master control module further comprises: a tenth IO port;
and a frame synchronization signal end in the first RGB interface of the main control module is connected with the tenth IO port of the main control module and is used for sending an interrupt signal to the main control module.
9. The 8080 bus interface based display control circuit of any one of claims 1 to 7, wherein said display device is an LCD.
10. A display system, comprising: a display device having an 8080 interface and the 8080 bus interface-based display control circuit of any one of claims 1 to 9;
the 8080 bus interface based display control circuit is connected with the display device.
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