CN113608784B

CN113608784B - NVMe control device and method

Info

Publication number: CN113608784B
Application number: CN202110952939.8A
Authority: CN
Inventors: 刘海亮; 刘洋; 黄泰然
Original assignee: Hunan Goke Microelectronics Co Ltd
Current assignee: Hunan Goke Microelectronics Co Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2024-05-03
Anticipated expiration: 2041-08-19
Also published as: CN113608784A

Abstract

The embodiment of the invention discloses an NVMe control device and method, wherein the device comprises an arbitration component, a storage component, a plurality of control components and a main control component; the main control component is in communication connection with the plurality of control components; the arbitration component is in communication connection with the plurality of control components; the main control component is used for sending instructions to the plurality of control components, so that the plurality of control components can sequentially execute backup operation or recovery operation on data in one or more units in the storage component under the action of the arbitration component; the main control component sends instructions to the plurality of control components; the plurality of control components sequentially perform backup operations or restore operations on data in one or more units in the storage component under the influence of the arbitration component. The method realizes the automatic backup and recovery of the related data of the NVMe, reduces the complexity of an interface and an internal connecting wire of the NVMe controller, and reduces the low-power-consumption entering and exiting time delay.

Description

NVMe control device and method

Technical Field

The invention relates to the field of data storage, in particular to an NVMe control device and method.

Background

With the high-speed development of cloud computing, artificial intelligence, the Internet of things and the like, the storage requirements of terminal products and servers are increasing, and in the process, NVMe (Non-Volatile Memory express) Solid state disk (Solid STATE DISK, SSD) obtains more and more attention on storage by virtue of low delay, low power consumption, high bandwidth and the like, and also becomes a new wind direction for the development of storage equipment.

NVMe is a host control interface using a register interface as an interaction interface, and stores operation commands of a host to an SSD through a commit queue SQ (Submission Queue), and SQ is divided into two types according to functions: the commit queue ASQ (Admin Submission Queue) and the input-output commit queue IO SQ are managed (Input Output Submission Queue). The management submission queue is used for realizing management of the SSD, such as creating IO SQ, deleting IO SQ, creating IO CQ, deleting IO CQ, setting characteristics, formatting disks and the like; the IO SQ is mainly used for transmitting read-write commands, data comparison commands, end-to-end data protection commands and the like of data.

In the deep sleep scenario, the power of NVMe needs to be disconnected, so the NVMe protocol registers, ASQ/ACQ, IO SQ/CQ related registers, MSIX table and PBA table need to be stored in the non-powered-down memory before power-down and restored after the next power-up.

There are two types of prior art treatments: firstly, a protocol register MSIX of NVMe is put in a non-drop area such as PCIe, ASQ/ACQ and IO SQ/CQ registers are put in an NVMe controller, and before power failure, a CPU performs read-write backup on the related registers of the ASQ/ACQ and the IO SQ/CQ and recovers through CPU read-write after power is again applied; and secondly, the NVMe protocol register, MSIX table, PBA table, ASQ/ACQ and IO SQ/CQ related registers of the physical function and the virtual function are all placed in an NVMe controller, and are backed up in a CPU read-write mode before power failure, and are restored in a CPU read-write mode after power is on again.

The disadvantage of the above scheme is that more wires are added to the interface of the NVMe controller, especially in the NVMe controller supporting multiple virtual physical machines, which is very unfavorable for the design migration and maintenance; meanwhile, the CPU performs backup and recovery through reading and writing, and causes large delay of low-power-consumption entry and exit, and the CPU has complicated operation.

Disclosure of Invention

The embodiment of the disclosure aims to solve the problem that when the number of IO SQs is large or virtual functions are supported in the design of an NVMe controller, the CPU backs up or restores the NVMe related registers or MSIX tables for a long time in an NVMe low-power consumption scene.

In order to solve the above technical problems, embodiments of the present disclosure provide an NVMe control device and method, and the specific scheme is as follows:

In a first aspect, embodiments of the present disclosure provide an NVMe control apparatus, the apparatus including an arbitration component, a storage component, a plurality of control components, and a main control component;

The main control component is in communication connection with the plurality of control components;

the arbitration component is in communication connection with the plurality of control components;

the main control component is used for sending instructions to the plurality of control components, so that the plurality of control components can sequentially execute backup operation or recovery operation on data in one or more units in the storage component under the action of the arbitration component.

According to one embodiment of the present disclosure, the main control assembly includes a detection unit therein;

the detection unit is used for detecting a command mode of the NVMe control device.

According to a specific embodiment of the present disclosure, the plurality of control components includes an NVMe protocol register control component, MSIX control component, commit queue, or completion queue control component;

The storage component comprises an NVMe protocol register unit, a MSIX unit, a commit queue or completion queue register unit and a static random access memory unit;

The NVMe protocol register control component is used for executing backup operation or recovery operation of data in the NVMe protocol register unit;

The MSIX control component is used for executing a backup operation or a recovery operation of the data in the MSIX unit;

The commit queue or completion queue control component is used for executing backup operation or recovery operation of data in a commit queue or completion queue register unit;

The static random access memory unit is used for storing data in the NVMe protocol register unit, the MSIX unit and the commit queue or completion queue register unit.

According to one embodiment of the present disclosure, the apparatus further comprises a decoder component;

the decoder component is in communication with the arbitration component;

the decoder component is used for decoding according to the read-write address and mapping the decoded read-write address to a corresponding unit in the storage component.

According to one embodiment of the present disclosure, the apparatus further comprises a state control component;

The state control component is in communication connection with the main control component;

the state control component is used for configuring and sending a signal to the main control component so that when the main control component detects that the signal is at a high level, corresponding backup operation or recovery operation is executed.

According to one embodiment of the present disclosure, the master control component includes a master control state machine;

the main control state machine is used for sending a backup instruction or a recovery instruction to the NVMe protocol register control component, the MSIX control component, the submit queue or the finish queue control component and receiving a backup completion signal or a recovery completion signal returned by the NVMe protocol register control component, the MSIX control component, the submit queue or the finish queue control component.

In a second aspect, an embodiment of the present disclosure further provides an NVMe control method applied to the NVMe control device according to any one of the first aspect, where the method includes:

the main control component sends instructions to the plurality of control components;

the plurality of control components sequentially perform backup operations or restore operations on data in one or more units in the storage component under the influence of the arbitration component.

The method further comprises the steps of:

The NVMe protocol register control component executes backup operation or recovery operation of data in an NVMe protocol register unit;

the MSIX control component performs a backup operation or a restore operation of the data in the MSIX unit;

The commit queue or completion queue control component executes backup operation or recovery operation of data in a commit queue or completion queue register unit;

The static random access memory unit stores data in an NVMe protocol register unit, MSIX unit, and a commit queue or completion queue register unit.

According to one embodiment of the present disclosure, the method further comprises:

the state control component configures and sends a signal to the main control component so that when the main control component detects that the signal is at a high level, a corresponding backup operation or a restore operation is performed.

The method further comprises the steps of:

the main control state machine sends a backup instruction or a recovery instruction to the NVMe protocol register control component, the MSIX control component, the submit queue or the finish queue control component, and receives a backup finish signal or a recovery finish signal returned by the NVMe protocol register control component, the MSIX control component, the submit queue or the finish queue control component.

According to the NVMe control device and method, the main control component sends the instruction to the control component, and the control component sequentially executes backup operation or recovery operation on data in the storage component under the action of the arbitration component. The existing scheme is that when low power consumption is in, the CPU sequentially reads the NVMe related registers, the values of the registers are written into the SRAM through the CPU, and when the low power consumption is out, the low power consumption is opposite. The scheme omits the operations of the CPU, and the hardware circuit automatically reads out the registers to be written into the SRAM instead, and the opposite is performed when the operation is exited. Compared with the CPU, the hardware circuit has a much faster execution speed of reading the register and writing the SRAM, so the scheme can reduce the entry and exit delay of low power consumption, realize automatic backup and recovery of related data in an NVMe low power consumption mode, reduce the complexity of an NVMe controller interface and an internal connecting line, and is convenient for transplanting and expansion.

Drawings

In order to more clearly illustrate the technical solutions of the present invention, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope of the present invention. Like elements are numbered alike in the various figures.

Fig. 1 shows a schematic structural diagram of an NVMe control device provided by an embodiment of the disclosure;

FIG. 2 shows a schematic diagram of a master control state machine of an NVMe control apparatus provided by an embodiment of the present disclosure;

FIG. 3 shows a MSIX control state machine schematic diagram of an NVMe control apparatus provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a control state machine for a commit queue or a completion queue of an NVMe control device according to an embodiment of the present disclosure;

fig. 5 shows a flow chart of an NVMe control method provided in an embodiment of the disclosure.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.

The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.

The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present invention, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the invention belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the invention.

Example 1

Fig. 1 is a schematic diagram of a connection relationship of an NVMe control device 100 according to an embodiment of the disclosure. As shown in FIG. 1, the NVMe control apparatus 100 comprises an arbitration component 105, a storage component 106, a plurality of control components and a main control component 101;

Specifically, the embodiment of the disclosure realizes automatic backup and recovery of the NVMe protocol register, MSIX table, PBA table, ASQ/ACQ and IO SQ/CQ of physical functions and virtual functions in a deep sleep scene through a hardware circuit.

The main control component 101 is in communication connection with the plurality of control components;

The arbitration component 105 is communicatively coupled to each of the plurality of control components;

In specific implementation, the main control component 101 is in communication connection with the CPU, and the main control component 101 directly receives instructions of the CPU and transmits the instructions to other components.

The main control component 101 is configured to send an instruction to the plurality of control components, so that the plurality of control components sequentially perform a backup operation or a restore operation on data in one or more units in the storage component 106 under the action of the arbitration component 105.

In specific implementation, the arbitration component 105 includes an interface of a PMU register configuration bus and a CPU register configuration bus, where the interfaces are the same, and arbitration of access rights of the register interfaces is implemented by the arbitration component 105. The arbitration component 105 is used to implement access arbitration for the PMU register configuration bus and the CPU register configuration bus. In a specific embodiment, round robin arbitration is used, however, other arbitration modes may be selected according to actual needs, which is not limited herein.

The main control component 101 is configured to control the sequence of backup and restoration of NVMe protocol registers, MSIX tables, ASQ/SQ/ACQ/CQ registers, and send backup or restore instructions to the plurality of control components.

According to one embodiment of the present disclosure, the main control assembly 101 includes a detection unit therein;

In particular implementations, the detection unit includes a save_en register and a restore_en register. Writing 1 to a save_en register or a restore_en register in the main control component 101 by the CPU, and starting the main control component 101 to enter a backup mode or a restore mode; the values written by the save_en register and the restore_en register cannot be 1 at the same time. Reading a CC.EN register of a certain physical function or virtual function, and if the bit value of the read CC.EN register is 1, indicating that the CC.EN register is enabled, starting the backup operation or the recovery operation of the related register of the physical function or virtual function; if the value of the bit of the read cc.en register is 0, this indicates that this cc.en register is not enabled, without backing up or restoring the relevant registers of the function.

According to one embodiment of the present disclosure, as shown in FIG. 1, the plurality of control components includes an NVMe protocol register control component 102, MSIX control component 103, a commit queue, or completion queue control component 104;

Specifically, the NVMe protocol register control component 102, MSIX control component 103 and the commit queue or completion queue control component 104 are communicatively coupled to the master control component 101, respectively. After receiving the backup instruction or the restore instruction of the CPU, the main control component 101 sequentially sends the instructions to the NVMe protocol register control component 102, MSIX control component 103 and the commit queue or completion queue control component 104.

The NVMe protocol register control component 102, MSIX control component 103 and the commit queue or completion queue control component 104 transmit specific instructions during backup or restore to other components through the arbitration component 105. The NVMe protocol register control component 102 is configured to control a specific backup and restore process of the NVMe protocol register; MSIX the control component 103 is used for controlling the specific backup and recovery processes of MSIX table, PBA table and MSIX aggregation register; the commit queue or completion queue control component 104 is used to control specific backup and restore processes of Admin/IO SQ/CQ for physical and virtual functions.

The storage component 106 includes an NVMe protocol register unit, MSIX units, a commit queue or completion queue register unit, and a static random access memory unit;

Specifically, the NVMe protocol register unit provides a PCIe read-write interface and a CPU register read-write interface, where the PCIe read-write interface is used for reading and writing the NVMe protocol register by the host in an active power consumption state (Active Power State); the CPU register read-write interface is used for reading and writing the NVMe protocol register by the CPU in the active power consumption state and is also used for backing up and recovering data in the NVMe protocol register in the low power consumption mode. Each physical or virtual function has an NVMe protocol register unit.

The NVMe protocol register control component 102 is configured to perform a backup operation or a restore operation of data in the NVMe protocol register unit;

specifically, the NVMe protocol register control component 102 starts the backup operation or the restore operation of the NVMe protocol register after receiving the backup signal or the restore signal transmitted by the main control component 101.

The MSIX control component 103 is configured to perform a backup operation or a restore operation of data in the MSIX unit;

In particular, the backup operation or the restore operation of the MSIX table, the PBA table, and the MSIX aggregation register have no sequence requirement. In a specific embodiment, the backup operation or the restore operation is sequentially performed according to the sequence of MSIX tables, PBA tables and MSIX aggregation registers; of course, the backup or restore sequence may be flexibly set according to actual needs, which is not limited herein. MSIX unit is used to receive and store host configuration MSIX vector values. When MSIX is enabled by the host, after the NVMe controller replies a CQ entry (CQ entry) to the host, the NVMe controller sends MSIX an interrupt message to the host side to inform the host that the SQ command has been executed. The MSIX unit also provides a PCIe read-write interface for host read-write configuration MSIX vector, while providing a CPU register read-write interface for backing up and recovering MSIX and PBA (Pending Bit Array) tables through the CPU register configuration interface in low power mode. There is one MSIX units per physical or virtual function.

The commit queue or completion queue control component 104 is configured to perform a backup operation or a restore operation of data in a commit queue or completion queue register unit;

Specifically, the commit queue or completion queue register unit includes an Admin/IO SQ related register and an Admin/IO CQ related register; providing a PCIe read-write interface for updating an ASQ/SQ tail doorbell register and an ACQ/CQ head doorbell register; the CPU register read-write interface is used for realizing the configuration of the CPU to the SQ/CQ, and realizing the backup and recovery of the data in the ASQ/SQ/ACQ/CQ registers through the CPU read-write register in a low power consumption mode. Each physical or virtual function has a pair of Admin SQ/CQ and each has a number of IO SQ/CQ. The SQ_CQ register specifically comprises an ASQ register, an ACQ register, an IO SQ register and an IO CQ register, wherein backup operation or recovery operation of the ASQ register, the ACQ register, the IO SQ register and the IO CQ register has no sequence requirement.

SQ (commit Queue) is used to store operation commands of a host to an SSD (Solid STATE DISK), and is divided into two types according to functions: ASQ (Admin Submission Queue, manage commit queues) and IO SQ. The ASQ is used to manage the SSD, such as creating an IO SQ, deleting an IO SQ, creating an IO CQ, deleting an IO CQ, setting characteristics, formatting a disk, and so on; IO SQ, which is primarily related to IO, includes read-write commands for transferring data, data compare commands, end-to-end data protection commands, and so forth.

In particular, the sram is mainly used for storing NVMe commands in an active power consumption state or for flexible use by firmware, and in a low power consumption sleep state, since the sram is not powered down, the sram is used for storing NVMe protocol registers, MSIX tables, ASQ/SQ/ACQ/CQ registers and other registers required to be backed up by modules or data required to be backed up by firmware.

the decoder component is communicatively coupled to the arbitration component 105;

in particular implementations, the decoder component is communicatively coupled to the arbitration component 105. The decoder component decodes the CPU read-write address transmitted by the arbitration component 105.

Specifically, the NVMe protocol register unit, MSIX unit, commit queue or completion queue register unit, and sram unit are configured to receive the address decoded by the decoder element. The decoder component is used for decoding according to the CPU read-write address and correctly mapping the decoded CPU read-write bus to each component needing CPU read-write access.

The main control state machine is configured to send a backup instruction or a restore instruction to the NVMe protocol register control component 102, MSIX control component 103, the commit queue or the completion queue control component 104, and receive a backup completion signal or a restore completion signal returned by the NVMe protocol register control component 102, MSIX control component 103, the commit queue or the completion queue control component 104.

In particular, as shown in FIG. 2, the master control state machine includes a save_en register and a restore_en register. The save_en register and the restore_en register are written by the CPU to 1, with save_en being 1 indicating that the current is the backup mode and restore_en being 1 indicating that the current is the restore mode. Wherein, sram_base_addr is the base address of the SRAM, which is written in by the CPU through the configuration register. When save_en is 1 or restore_en is 1, the state machine jumps to the cc_en state where the cc.en register of PF0 is read, if the value of the read cc_en bit is 1, jumps to PROTC to start backing up the NVMe protocol register of the PF, if the value of the read cc_en bit is 0, indicating that this function is not enabled, and no backup operation or restoration operation of the NVMe protocol register, MSIX table, ASQ/SQ/ACQ/CQ register, etc. of this function is required to be performed. fc_count is incremented by 1 and the cc_en register of the next physical function is continuously read. It should be noted that both save_en and restore_en cannot be 1 at the same time.

In a specific embodiment, the backup operation or the recovery operation of the NVMe protocol register, MSIX table, ASQ/SQ/ACQ/CQ related register, etc. of all physical functions is sequentially performed, and then the backup operation or the recovery operation of the NVMe protocol register, MSIX table, ASQ/SQ/ACQ/CQ related register, etc. of all virtual functions is sequentially performed; the virtual function may be a physical function or a virtual function corresponding to the physical function, and the design is flexible, and the present invention is not limited thereto.

If the reading is that the CC.EN is always 0, the operation continues until all the functions are traversed once and then return to the IDLE state, which indicates that the backup or the restoration is completed. At PROTC the state outputs protc _sr_strt signal to the NVMe protocol register control component 102, starts backup or restores NVMe protocol registers, after the NVMe protocol register backup is completed, the protc _sr_done signal from the NVMe protocol register control component 102 is set to 1, the protc _sr_strt signal is set to 0, and the state machine jumps to MSIX state. The protc _sr_done signal is set to 0 in MSIX state, the msix _sr_strt signal input by the MSIX control component 103 is set to 1, and backup or restoration of MSIX table, PBA table, MSIX aggregation related registers is started.

Wherein, the backup or restore of MSIX table, PBA table, MSIX aggregation related registers has no sequence requirement, and in a specific embodiment, the backup or restore is sequentially performed according to the sequence of MSIX table, PBA table, MSIX aggregation related registers.

After the backup or restore is completed, the msix _sr_done signal from MSIX control component 103 is set to 1, the msix _sr_strt signal is set to 0, and the state machine jumps to the sq_cq state; in this state, the msix _sr_done signal is set to 0, the sqcq _sr_strt signal is input to the commit queue or completion queue control component 104, and the backup or restore process of the data in the ASQ/SQ/ACQ/CQ-related registers is started.

Wherein the backup or restoration of data in the ASQ/SQ/ACQ/CQ registers is out of order, and in one specific embodiment, the backup or restoration is performed in the order ASQ/ACQ/SQ/CQ. When the backup or restore of these registers is completed, the sqcq _sr_done signal from the commit queue or completion queue control component 104 is set to 1 and it is determined whether the current function is the last function, and if so, the process jumps to the IDLE state and the backup or restore process is completed. If not the last function, jump to CC_EN state, read the CC_EN register of the next function.

Specifically, as shown in fig. 3, when msix _sr_strt is 1, MSIX controls the state machine to jump from the IDLE state to the MSIX _t state, and starts backup or restoration of MSIX tables. It should be noted that the number of MSIX vectors supported by each physical function and virtual function may be different, and the end address of the register to be read in this state needs to be determined according to the number of MSIX vectors supported by the actual function, so as to ensure that each MSIX vector can be backed up or restored.

When MSIX tables are backed up or restored, msixt _sr_done signal is set to 1, and MSIX control state machine detects msixt _sr_done is 1 to jump to PBA_T state. And setting msixt _sr_done signal to 0, starting backup or recovery of the PBA table, setting PBA _sr_done signal to 1 after the backup or recovery of the PBA table is finished, and detecting PBA _sr_done to be 1 by the MSIX control state machine to jump to MSIX _ COAL. And setting pba _sr_done signal to 0, starting MSIX to aggregate the backup or recovery of the data in the related registers, setting msix _sr_done signal to 1 after the backup or recovery of the data in the registers is completed, transmitting the data to the main control component 101, and controlling the state machine to jump to the IDLE state MSIX after the backup or recovery of the data in the MSIX aggregation registers is completed.

In particular, as shown in fig. 4, when sqcq _sr_strt is 1, the sq_cq control state machine jumps from the IDLE state to the ASQ state, and starts to perform backup or restoration of data in the relevant registers that need backup or restoration of ASQ. After ASQ backup or recovery is completed, ASQ _sr_done signal is set to 1, SQ_CQ control state machine detects ASQ _sr_done is 1 to jump to ACQ state, acq_sr_done signal is set to 0, and backup operation or recovery operation of ACQ related register is started. After the backup or recovery of the ACQ related register is finished, the acq_sr_done signal is set to 1, the sq_cq control state machine detects that the acq_sr_done is 1 to jump to the SQ state, the acq_sr_done signal is set to 0, and the backup or recovery operation of the SQ related register is started, wherein in the state, the backup or recovery of all the supported IO SQ related registers is required to be finished. When the backup or recovery of the registers is completed, the sq_sr_done signal is set to 1, the sq_cq control state machine detects that the sq_sr_done signal is 1, the sq_cq control state machine jumps to the CQ state, the sq_sr_done signal is set to 0, the backup or recovery of the IO CQ related registers is started, the data of all the IO CQ related registers needs to be backed up or recovered in the state, the sqcq _sr_done signal is set to 1 after the backup or recovery is completed, and the data is transmitted to the main control component 101, and the sq_cq control state machine jumps to the IDLE state.

According to the NVMe control device provided by the embodiment of the disclosure, the main control component sends the instruction to the control component, and the control component sequentially executes backup operation or recovery operation on the data in the storage component under the action of the arbitration component. The existing scheme is that when low power consumption is in, the CPU sequentially reads the NVMe related registers, the values of the registers are written into the SRAM through the CPU, and when the low power consumption is out, the low power consumption is opposite. The scheme omits the operations of the CPU, and the hardware circuit automatically reads out the registers to be written into the SRAM instead, and the opposite is performed when the operation is exited. Compared with the CPU, the hardware circuit has a much faster execution speed of reading the register and writing the SRAM, so the scheme can reduce the entry and exit delay of low power consumption, realize automatic backup and recovery of related data in an NVMe low power consumption mode, reduce the complexity of an NVMe controller interface and an internal connecting line, and is convenient for transplanting and expansion.

Example 2

Fig. 5 is a schematic flow chart of an NVMe control method according to an embodiment of the disclosure. As shown in fig. 5, the NVMe control method is applied to the NVMe control apparatus described in embodiment 1, and the method includes:

s501, a main control component sends instructions to the plurality of control components;

s502, the plurality of control components sequentially execute backup operation or recovery operation on data in one or more units in the storage component under the action of the arbitration component.

The method further comprises the steps of:

In summary, according to the NVMe control method provided by the embodiment of the present disclosure, the main control component sends the instruction to the control component, and the control component sequentially performs the backup operation or the recovery operation on the data in the storage component under the effect of the arbitration component. The existing scheme is that when low power consumption is in, the CPU sequentially reads the NVMe related registers, the values of the registers are written into the SRAM through the CPU, and when the low power consumption is out, the low power consumption is opposite. The scheme omits the operations of the CPU, and the hardware circuit automatically reads out the registers to be written into the SRAM instead, and the opposite is performed when the operation is exited. Compared with the CPU, the hardware circuit has a much faster execution speed of reading the register and writing the SRAM, so the scheme can reduce the entry and exit delay of low power consumption, realize automatic backup and recovery of related data in an NVMe low power consumption mode, reduce the complexity of an NVMe controller interface and an internal connecting line, and is convenient for transplanting and expansion. The specific implementation process of the provided NVMe control method may refer to the specific implementation process of the NVMe control device provided in the embodiments shown in fig. 1 to fig. 4, and will not be described herein.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules or units in various embodiments of the invention may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.

Claims

1. An NVMe control device is characterized by comprising an arbitration component, a storage component, a plurality of control components and a main control component;

The main control component is used for sending instructions to the plurality of control components, so that the plurality of control components can sequentially execute backup operation or recovery operation on data in one or more units in the storage component under the action of the arbitration component;

The plurality of control components comprise an NVMe protocol register control component, a MSIX control component, a commit queue or a completion queue control component;

2. The NVMe control device of claim 1, wherein the main control assembly includes a detection unit therein;

3. The NVMe control device of claim 1, further comprising a decoder component;

the decoder component is in communication with the arbitration component;

4. The NVMe control device of claim 1, further comprising a status control component;

5. The NVMe control device of claim 1, wherein the master control component comprises a master control state machine;

6. An NVMe control method, characterized by being applied to the NVMe control device according to any one of claims 1 to 5, comprising:

7. The NVMe control method of claim 6, wherein the plurality of control components comprises an NVMe protocol register control component, MSIX control component, commit queue, or completion queue control component;

The method further comprises the steps of:

8. The NVMe control method of claim 6, further comprising:

9. The NVMe control method of claim 7, wherein the master control component comprises a master control state machine;

The method further comprises the steps of: