CN113608784A

CN113608784A - NVMe control device and method

Info

Publication number: CN113608784A
Application number: CN202110952939.8A
Authority: CN
Inventors: 刘海亮; 刘洋; 黄泰然
Original assignee: Hunan Goke Microelectronics Co Ltd
Current assignee: Hunan Goke Microelectronics Co Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2021-11-05
Anticipated expiration: 2041-08-19
Also published as: CN113608784B

Abstract

The embodiment of the invention discloses an NVMe control device and a method, wherein the device comprises an arbitration component, a storage component, a plurality of control components and a main control component; the main control assembly is in communication connection with the plurality of control assemblies; the arbitration component is in communication connection with each of the plurality of control components; the main control assembly is used for sending instructions to the plurality of control assemblies so that the plurality of control assemblies sequentially execute backup operation or recovery operation on data in one or more units in the storage assembly under the action of the arbitration assembly; the main control component sends instructions to the plurality of control components; the plurality of control components sequentially execute backup operation or recovery operation on the data in one or more units in the storage component under the action of the arbitration component. The NVMe automatic backup and recovery related data are realized, the complexity of an NVMe controller interface and an internal connection line is reduced, and the low-power-consumption entry and exit delay is reduced.

Description

NVMe control device and method

Technical Field

The invention relates to the field of data storage, in particular to an NVMe control device and method.

Background

With the rapid development of cloud computing, artificial intelligence, internet of things and the like, the storage requirements of terminal products and servers are getting larger and larger, in the process, NVMe (Non-Volatile Memory express) Solid State disks (Solid State disks, SSDs) get more and more attention to storage with the advantages of low delay, low power consumption, high bandwidth and the like, and the NVMe Solid State disks also become a new wind direction for the development of storage devices.

NVMe is a host-side control interface using a register interface as an interactive interface, and stores an operating command of a host to an SSD (solid state drive) by submitting a queue SQ (submission queue), wherein SQ is divided into two types according to functions: an administration Submission Queue asq (admin Submission Queue) and an Input Output Submission Queue IO SQ (Input Output Submission Queue). The management submission queue is used for realizing management of the SSD solid state disk, such as creating IO SQ, deleting IO SQ, creating IO CQ, deleting IO CQ, setting characteristics, formatting a disk and the like; the IO SQ is mainly used for transmitting a read-write command of data, a data comparison command, an end-to-end data protection command and the like.

In a deep sleep scene, the power supply of the NVMe needs to be disconnected, so that the NVMe protocol register, the ASQ/ACQ and IO SQ/CQ related registers, the MSIX table and the PBA table need to be stored in a non-power-down memory before power failure, and are recovered after next power-up.

The prior art processes are of two kinds: firstly, an NVMe protocol register and an MSIX table are placed in a PCIe non-drop area, ASQ/ACQ and IO SQ/CQ registers are placed in an NVMe controller, a CPU reads and writes related registers of the ASQ/ACQ and the IO SQ/CQ before power failure and reads and backs up the registers and recovers the registers after the power failure is powered on again; and secondly, the NVMe protocol register, the MSIX table and the PBA table, the ASQ/ACQ and the IO SQ/CQ related registers with physical functions and virtual functions are all placed in an NVMe controller, backup is carried out in a CPU read-write mode before power failure, and recovery is carried out in the CPU read-write mode after power is on again.

The disadvantage of the above scheme is that more connecting lines are added to the interface of the NVMe controller, and particularly, the NVMe controller supporting multiple virtual physical machines is very disadvantageous to the migration and maintenance of the design; meanwhile, the backup and recovery are carried out through the reading and writing of the CPU, so that the low-power-consumption entry and exit delay is large, and the operation of the CPU is complicated.

Disclosure of Invention

The embodiment of the disclosure aims to solve the problem that a CPU backups or restores NVMe related registers or MSIX tables for a long time in an NVMe low power consumption scene when IO SQ quantity is large or virtual functions are supported in NVMe controller design.

In order to solve the technical problem, the embodiment of the present disclosure provides an NVMe control apparatus and method, and the specific scheme is as follows:

in a first aspect, an embodiment of the present disclosure provides an NVMe control apparatus, where the apparatus includes an arbitration component, a storage component, a plurality of control components, and a main control component;

the main control assembly is in communication connection with the plurality of control assemblies;

the arbitration component is in communication connection with each of the plurality of control components;

the main control assembly is used for sending instructions to the plurality of control assemblies, so that the plurality of control assemblies sequentially execute backup operation or recovery operation on data in one or more units in the storage assembly under the action of the arbitration assembly.

According to a specific embodiment of the present disclosure, the main control assembly includes a detection unit therein;

the detection unit is used for detecting a command mode of the NVMe control device.

According to a specific embodiment of the present disclosure, the plurality of control components includes an NVMe protocol register control component, an MSIX control component, a commit queue or a complete queue control component;

the storage component comprises an NVMe protocol register unit, an MSIX unit, a submission queue or completion queue register unit and a static random access memory unit;

the NVMe protocol register control component is used for executing backup operation or recovery operation of data in the NVMe protocol register unit;

the MSIX control component is used for executing backup operation or recovery operation of data in the MSIX unit;

the commit queue or completion queue control component is used for executing backup operation or recovery operation of data in the register unit of the commit queue or completion queue;

the static random access memory unit is used for storing data in the NVMe protocol register unit, the MSIX unit and the register unit of the submission queue or the completion queue.

According to a specific embodiment of the present disclosure, the apparatus further comprises a decoder component;

the decoder component is in communication connection with the arbitration component;

the decoder component is used for decoding according to the read-write address and mapping the decoded read-write address to a corresponding unit in the storage component.

According to a specific embodiment of the present disclosure, the apparatus further comprises a state control component;

the state control assembly is in communication connection with the main control assembly;

the state control assembly is used for configuring and sending a signal to the main control assembly so that when the main control assembly detects that the signal is at a high level, corresponding backup operation or recovery operation is executed.

According to a specific embodiment of the present disclosure, the master control assembly includes a master control state machine;

the main control state machine is used for sending a backup instruction or a recovery instruction to the NVMe protocol register control component, the MSIX control component, the commit queue or the completion queue control component and receiving a backup completion signal or a recovery completion signal returned by the NVMe protocol register control component, the MSIX control component, the commit queue or the completion queue control component.

In a second aspect, an embodiment of the present disclosure further provides an NVMe control method applied to the NVMe control apparatus according to any one of the first aspects, where the method includes:

the main control component sends instructions to the plurality of control components;

the plurality of control components sequentially execute backup operation or recovery operation on the data in one or more units in the storage component under the action of the arbitration component.

the method further comprises the following steps:

the NVMe protocol register control component executes backup operation or recovery operation of data in the NVMe protocol register unit;

the MSIX control component executes a backup operation or a recovery operation of data in the MSIX unit;

the commit queue or completion queue control component executes the backup operation or the recovery operation of the data in the register unit of the commit queue or completion queue;

the static random access memory unit stores data in the NVMe protocol register unit, the MSIX unit, and the commit queue or completion queue register unit.

According to a specific embodiment of the present disclosure, the method further comprises:

and the state control assembly configures and sends a signal to the main control assembly so that the main control assembly executes corresponding backup operation or recovery operation when detecting that the signal is at a high level.

the method further comprises the following steps:

and the main control state machine sends a backup instruction or a recovery instruction to the NVMe protocol register control component, the MSIX control component, the submission queue or the completion queue control component and receives a backup completion signal or a recovery completion signal returned by the NVMe protocol register control component, the MSIX control component and the submission queue or completion queue control component.

According to the NVMe control device and the NVMe control method provided by the embodiment of the disclosure, the main control component sends the instruction to the control component, and the control component sequentially executes backup operation or recovery operation on data in the storage component under the action of the arbitration component. In the existing scheme, when low power consumption enters, NVMe related registers are read in sequence by a CPU, and the values of the registers are written into an SRAM by the CPU, and when the registers exit, the opposite is realized. This scheme saves these operations of the CPU and instead the hardware circuit automatically reads these registers to write to SRAM and exits the other way around. Compared with a CPU (central processing unit) for reading a register and writing an SRAM (static random access memory), the hardware circuit has a high execution speed, so that the entering and exiting time delay of low power consumption can be reduced, the automatic backup and recovery of related data in an NVMe (network video Me) low-power-consumption mode are realized, the complexity of an interface and an internal connection line of an NVMe (network video Me) controller is reduced, and the transplantation and the expansion are facilitated.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.

Fig. 1 shows a schematic structural diagram of an NVMe control apparatus provided by an embodiment of the present disclosure;

fig. 2 shows a schematic diagram of a main control state machine of an NVMe control apparatus provided by an embodiment of the present disclosure;

fig. 3 illustrates an MSIX control state machine diagram of an NVMe control apparatus according to an embodiment of the present disclosure;

fig. 4 illustrates a schematic diagram of a commit queue or completion queue control state machine of an NVMe control apparatus according to an embodiment of the present disclosure;

fig. 5 shows a schematic flow chart of an NVMe control method provided by an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

Example 1

Fig. 1 is a schematic connection relationship diagram of an NVMe control apparatus 100 according to an embodiment of the present disclosure. As shown in fig. 1, the NVMe control apparatus 100 includes an arbitration component 105, a storage component 106, a plurality of control components, and a main control component 101;

specifically, the embodiment of the disclosure realizes automatic backup and recovery of NVMe protocol registers, MSIX tables, PBA tables, ASQ/ACQ, IO SQ/CQ of physical functions and virtual functions in a deep sleep scene through a hardware circuit.

The main control assembly 101 is in communication connection with the plurality of control assemblies;

the arbitration component 105 is communicatively coupled to each of the plurality of control components;

in specific implementation, the main control component 101 is in communication connection with the CPU, and the main control component 101 directly receives the instruction of the CPU and transmits the instruction to other components.

The main control component 101 is configured to send instructions to the plurality of control components, so that the plurality of control components sequentially execute a backup operation or a recovery operation on data in one or more units in the storage component 106 under the action of the arbitration component 105.

In specific implementation, the arbitration component 105 includes an interface of the PMU register configuration bus and a CPU register configuration bus, the interfaces of the PMU register configuration bus and the CPU register configuration bus are the same, and the arbitration of the access right of the register interface is realized by the arbitration component 105. Arbitration component 105 is used to implement access arbitration for the PMU register configuration bus and the CPU register configuration bus. Round-robin arbitration is used in one specific embodiment, but of course, other arbitration schemes may be selected according to actual needs, and are not limited herein.

The main control component 101 is used for controlling the backup and recovery sequence of the NVMe protocol register, the MSIX table and the ASQ/SQ/ACQ/CQ register, and sending a backup or recovery instruction to the plurality of control components.

According to a specific embodiment of the present disclosure, the main control assembly 101 includes a detection unit therein;

In specific implementation, the detection unit comprises a save _ en register and a restore _ en register. Writing 1 into a save _ en register or a restore _ en register in the main control component 101 by the CPU, and starting the main control component 101 to enter a backup mode or a restore mode; wherein, the values written by the save _ en register and the restore _ en register cannot be 1 at the same time. Reading a CC.EN register of a certain physical function or virtual function, and if the value of a read bit of the CC.EN register is 1, which indicates that the CC.EN register is enabled, starting to execute backup operation or recovery operation of a relevant register of the physical function or virtual function; if the value of the bit of the read cc.en register is 0, it indicates that the cc.en register is not enabled, and the relevant register of the function does not need to be backed up or restored.

According to one embodiment of the present disclosure, as shown in fig. 1, the plurality of control components includes an NVMe protocol register control component 102, an MSIX control component 103, a commit queue or completion queue control component 104;

specifically, the NVMe protocol register control component 102, the MSIX control component 103, and the commit queue or completion queue control component 104 are communicatively connected to the main control component 101, respectively. After receiving a backup instruction or a recovery instruction of the CPU, the main control component 101 sequentially sends instructions to the NVMe protocol register control component 102, the MSIX control component 103, and the commit queue or completion queue control component 104.

The NVMe protocol register control component 102, the MSIX control component 103, and the commit queue or completion queue control component 104 transmit specific instructions in the backup or restore process to other components through the arbitration component 105. The NVMe protocol register control component 102 is used for controlling the specific backup and recovery processes of the NVMe protocol register; the MSIX control component 103 is used for controlling the concrete backup and recovery processes of the MSIX table, the PBA table and the MSIX aggregation register; the commit queue or completion queue control component 104 is used to control the specific backup, recovery process of Admin/IO SQ/CQ for physical and virtual functions.

The storage component 106 comprises an NVMe protocol register unit, an MSIX unit, a submit queue or complete queue register unit and a static random access memory unit;

specifically, the NVMe protocol register unit provides a PCIe read-write interface and a CPU register read-write interface, and the PCIe read-write interface is used for an Active Power State (Active Power State) host to read and write the NVMe protocol register; the CPU register read-write interface is used for reading and writing the NVMe protocol register by the CPU in the active power consumption state and is also used for backing up and recovering data in the NVMe protocol register in the low power consumption mode. There is one NVMe protocol register unit per physical function or virtual function.

The NVMe protocol register control component 102 is configured to execute a backup operation or a recovery operation of data in an NVMe protocol register unit;

specifically, the NVMe protocol register control component 102 starts the backup operation or the recovery operation of the NVMe protocol registers after receiving the backup signal or the recovery signal transmitted by the main control component 101.

The MSIX control component 103 is used for executing backup operation or recovery operation of data in the MSIX unit;

in specific implementation, the backup operation or the recovery operation of the MSIX table, the PBA table and the MSIX aggregation register has no sequential requirement. In a specific implementation mode, backup operation or recovery operation is performed in sequence according to an MSIX table, a PBA table and an MSIX aggregation register; of course, the backup or recovery sequence may also be flexibly set according to actual needs, and is not limited herein. The MSIX unit is used for receiving and storing host configuration MSIX vector values. When the MSIX is enabled by the host, after the NVMe controller replies a CQ entry (CQ entry) to the host, the NVMe controller sends an MSIX interrupt message to the host to notify the host that the SQ command has been executed. The MSIX unit also provides a PCIe read-write interface for the host to read and write the configured MSIX vector, and simultaneously provides a CPU register read-write interface for the MSIX table and the PBA (pending Bit array) table to be backed up and restored through the CPU register configuration interface in a low power consumption mode. There is one MSIX unit per physical function or virtual function.

The commit queue or completion queue control component 104 is configured to perform a backup operation or a restore operation on data in a register unit of the commit queue or completion queue;

specifically, the register unit of the submission queue or the completion queue comprises an Admin/IO SQ correlation register and an Admin/IO CQ correlation register; providing a PCIe read-write interface for updating an ASQ/SQ tail doorbell register and an ACQ/CQ head doorbell register; the CPU register read-write interface is used for realizing the configuration of the CPU on the SQ/CQ and realizing the backup and the recovery of the data in the ASQ/SQ/ACQ/CQ register through the CPU read-write register under the low power consumption mode. Each physical function or virtual function has a pair of Admin SQ/CQ, and each has a certain number of IO SQ/CQ. The SQ _ CQ register specifically comprises an ASQ register, an ACQ register, an IO SQ register and an IO CQ register, wherein the backup operation or recovery operation of the ASQ register, the ACQ register, the IO SQ register and the IO CQ register has no sequential requirement.

SQ (Submission Queue) is used to store operation commands of a host to an SSD (Solid State Disk), and is divided into two types according to functions: ASQ (Admin Submission Queue) and IO SQ. The ASQ is used for realizing management of the SSD, such as creating IO SQ, deleting IO SQ, creating IO CQ, deleting IO CQ, setting characteristics, formatting a disk and the like; IO SQ, which is mainly related to IO, includes read and write commands for transferring data, data comparison commands, end-to-end data protection commands, and the like.

In a low-power sleep state, because the static random access memory unit does not power down, the static random access memory unit is used for storing NVMe protocol registers, MSIX tables, ASQ/SQ/ACQ/CQ registers and other registers which need to be backed up by modules or data which needs to be backed up by firmware.

the decoder component is communicatively coupled to the arbitration component 105;

in one implementation, the decoder component is communicatively coupled to the arbitration component 105. The decoder component decodes the CPU read and write addresses transmitted by the arbitration component 105.

Specifically, the NVMe protocol register unit, the MSIX unit, the commit queue or completion queue register unit, and the sram unit are configured to receive an address decoded by the decoder component. The decoder component is used for decoding according to the CPU read-write address and correctly mapping the decoded CPU read-write bus to each component needing the CPU read-write access.

the main control state machine is used for sending a backup instruction or a recovery instruction to the NVMe protocol register control component 102, the MSIX control component 103, and the commit queue or completion queue control component 104, and receiving a backup completion signal or a recovery completion signal returned by the NVMe protocol register control component 102, the MSIX control component 103, and the commit queue or completion queue control component 104.

In particular, as shown in fig. 2, the main control state machine includes a save _ en register and a restore _ en register. The save _ en register and restore _ en register are written by the CPU with 1 for save _ en indicating current backup mode and 1 for restore _ en indicating current restore mode. Wherein, SRAM _ base _ addr is the base address of SRAM, and is written by the CPU through the configuration register. When save _ EN is 1 or restore _ EN is 1, the state machine jumps to the CC _ EN state, reads the CC _ EN register of PF0 in this state, jumps to the PROTC state to start backing up the NVMe protocol register of the PF if the value of the read CC _ EN bit is 1, and if the value of the read CC _ EN bit is 0, it indicates that this function is not enabled and it is not necessary to perform the backup operation or the restore operation of the NVMe protocol register, the MSIX table, the ASQ/SQ/ACQ/CQ register, and the like of this function. And adding 1 to the fc _ count, and continuously reading the CC _ EN register of the next physical function. It should be noted that both save _ en and restore _ en cannot be 1 at the same time.

In a specific embodiment, the backup operation or the recovery operation of all the NVMe protocol registers of the physical functions, the MSIX table, the ASQ/SQ/ACQ/CQ related registers and the like is sequentially executed, and then the backup operation or the recovery operation of all the NVMe protocol registers of the virtual functions, the MSIX table, the ASQ/SQ/ACQ/CQ related registers and the like is sequentially executed; the physical function and the virtual function corresponding to the physical function may be in sequence, and the design is flexible, and is not limited here.

And if the read CC.EN is always 0, continuing to return to an IDLE state after all functions are traversed once, and indicating that the backup or the recovery is finished. And outputting a PROTC _ sr _ strt signal to the NVMe protocol register control component 102 in the PROTC state, starting to backup or restore the NVMe protocol register, setting a PROTC _ sr _ done signal from the NVMe protocol register control component 102 to be 1 after the NVMe protocol register is completely backed up, setting the PROTC _ sr _ strt signal to be 0, and jumping the state machine to the MSIX state. In the MSIX state, a protc _ sr _ done signal is set to 0, an MSIX _ sr _ strt signal input by the MSIX control component 103 is set to 1, and backup or recovery of the MSIX table, the PBA table and the MSIX aggregation related register is started.

The backup or recovery of the MSIX table, the PBA table and the MSIX aggregation related register has no sequence requirement, and in a specific implementation mode, the backup or recovery is performed in sequence according to the sequence of the MSIX table, the PBA table and the MSIX aggregation related register.

After the backup or recovery is completed, setting the MSIX _ sr _ done signal from the MSIX control component 103 to 1, setting the MSIX _ sr _ strt signal to 0, and jumping to the SQ _ CQ state by the state machine; in this state, the msix _ sr _ done signal is set to 0, and the sqcq _ sr _ strt signal is input to the commit queue or completion queue control component 104, starting the backup or recovery process of the data in the ASQ/SQ/ACQ/CQ correlation registers.

The backup or recovery of the data in the ASQ/SQ/ACQ/CQ register has no sequential requirement, and in a specific embodiment, the backup or recovery is performed according to the sequence of the ASQ/ACQ/SQ/CQ. After the backup or recovery of these registers is completed, the sqcq _ sr _ done signal from the commit queue or completion queue control component 104 is set to 1, and it is determined whether the current function is the last function, if the current function is the last function, the IDLE state is skipped, and the backup or recovery process is completed. If not, jump to the CC _ EN state and read the CC _ EN register of the next function.

Specifically, as shown in fig. 3, when MSIX _ sr _ strt is 1, the MSIX control state machine jumps from the IDLE state to the MSIX _ T state, and starts to backup or restore the MSIX table. It should be noted that the number of the MSIX vectors supported by each physical function and the virtual function may be different, and the end address of the register to be read in this state needs to be determined according to the number of the MSIX vectors supported by the actual function, so as to ensure that each MSIX vector can be backed up or restored.

After the MSIX table is backed up or restored, the msixt _ sr _ done signal is set to 1, and the MSIX control state machine detects that the msixt _ sr _ done is 1 and jumps to the PBA _ T state. Setting the msixt _ sr _ done signal to 0, starting the backup or recovery of the PBA table, setting the PBA _ sr _ done signal to 1 after the backup or recovery of the PBA table is finished, and jumping to the MSIX _ COAL state when the MSIX control state machine detects that PBA _ sr _ done is 1. Setting pba _ sr _ done signal to 0, starting backup or recovery of data in MSIX aggregation related registers, setting MSIX _ sr _ done signal to 1 and transmitting to the main control component 101 after the data in the registers are completely backed up or recovered, and jumping to an IDLE state by the MSIX control state machine after the data in the MSIX aggregation register are completely backed up or recovered.

In specific implementation, as shown in fig. 4, when sqcq _ sr _ strt is 1, the SQ _ CQ control state machine jumps from the IDLE state to the ASQ state, and starts to backup or restore data in the relevant register that needs to be backed up or restored by the ASQ. After the ASQ backup or recovery is completed, ASQ _ sr _ done signal is set to 1, the SQ _ CQ control state machine detects that ASQ _ sr _ done jumps to the ACQ state for 1, sets the ACQ _ sr _ done signal to 0, and starts the backup operation or recovery operation of the ACQ-related registers. After the ACQ related registers are backed up or restored, setting the ACQ _ sr _ done signal to be 1, jumping to an SQ state when the ACq _ sr _ done is detected to be 1 by an SQ _ CQ control state machine, setting the ACQ _ sr _ done signal to be 0, starting the backup operation or the restoration operation of the SQ related registers, and in the state, backing up or restoring all the supported IO SQ related registers. After the backup or recovery of the registers is finished, setting the SQ _ sr _ done signal to be 1, detecting that the SQ _ sr _ done signal is 1 by the SQ _ CQ control state machine, jumping to a CQ state by the SQ _ CQ control state machine, setting the SQ _ sr _ done signal to be 0, starting the backup or recovery of the CQ IO related registers, needing to backup or recover all the data of the IO CQ related registers in the state, setting the sqcq _ sr _ done signal to be 1 after the backup or recovery is finished, transmitting the sqcq _ sr _ done signal to the main control component 101, and jumping to an IDLE state by the SQ _ CQ control state machine.

According to the NVMe control device provided by the embodiment of the disclosure, the main control component sends the instruction to the control component, and the control component sequentially executes backup operation or recovery operation on data in the storage component under the action of the arbitration component. In the existing scheme, when low power consumption enters, NVMe related registers are read in sequence by a CPU, and the values of the registers are written into an SRAM by the CPU, and when the registers exit, the opposite is realized. This scheme saves these operations of the CPU and instead the hardware circuit automatically reads these registers to write to SRAM and exits the other way around. Compared with a CPU (central processing unit) for reading a register and writing an SRAM (static random access memory), the hardware circuit has a high execution speed, so that the entering and exiting time delay of low power consumption can be reduced, the automatic backup and recovery of related data in an NVMe (network video Me) low-power-consumption mode are realized, the complexity of an interface and an internal connection line of an NVMe (network video Me) controller is reduced, and the transplantation and the expansion are facilitated.

Example 2

Fig. 5 is a schematic flow chart of an NVMe control method provided by an embodiment of the present disclosure. As shown in fig. 5, the NVMe control method is applied to the NVMe control apparatus according to embodiment 1, and the method includes:

s501, the main control component sends instructions to the plurality of control components;

s502, the control components sequentially execute backup operation or recovery operation on the data in one or more units in the storage component under the action of the arbitration component.

the method further comprises the following steps:

To sum up, in the NVMe control method provided by the embodiment of the present disclosure, the main control component sends an instruction to the control component, and the control component sequentially executes backup operation or recovery operation on data in the storage component under the action of the arbitration component. In the existing scheme, when low power consumption enters, NVMe related registers are read in sequence by a CPU, and the values of the registers are written into an SRAM by the CPU, and when the registers exit, the opposite is realized. This scheme saves these operations of the CPU and instead the hardware circuit automatically reads these registers to write to SRAM and exits the other way around. Compared with a CPU (central processing unit) for reading a register and writing an SRAM (static random access memory), the hardware circuit has a high execution speed, so that the entering and exiting time delay of low power consumption can be reduced, the automatic backup and recovery of related data in an NVMe (network video Me) low-power-consumption mode are realized, the complexity of an interface and an internal connection line of an NVMe (network video Me) controller is reduced, and the transplantation and the expansion are facilitated. For a specific implementation process of the NVMe control method, reference may be made to the specific implementation process of the NVMe control device provided in the embodiments shown in fig. 1 to fig. 4, and details are not repeated here.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims

1. The NVMe control device is characterized by comprising an arbitration component, a storage component, a plurality of control components and a main control component;

2. The NVMe control apparatus according to claim 1, wherein a detection unit is included in the main control assembly;

3. The NVMe control apparatus of claim 1, wherein the plurality of control components comprises an NVMe protocol register control component, an MSIX control component, a commit queue, or a complete queue control component;

4. The NVMe control apparatus of claim 1, further comprising an encoder component;

5. The NVMe control apparatus of claim 1, further comprising a state control component;

6. The NVMe control apparatus of claim 3, wherein the main control component comprises a main control state machine;

7. An NVMe control method applied to the NVMe control apparatus according to any one of claims 1 to 6, the method comprising:

8. The NVMe control method of claim 7, wherein the plurality of control components includes an NVMe protocol register control component, an MSIX control component, a commit queue, or a completion queue control component;

the method further comprises the following steps:

9. The NVMe control method of claim 7, further comprising:

10. The NVMe control method of claim 8, wherein the master control component comprises a master control state machine;

the method further comprises the following steps: