CN113608771A - Method, device and equipment for quickly programming FPGA firmware and readable medium - Google Patents
Method, device and equipment for quickly programming FPGA firmware and readable medium Download PDFInfo
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Abstract
The invention provides a method, a device, equipment and a readable medium for rapidly programming FPGA firmware, wherein the method comprises the following steps: judging whether the received data is a firmware upgrading instruction; in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data; in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware; and responding to the completion of writing all the cached data into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data. By using the scheme of the invention, the rapid programming of the FPGA firmware can be realized, the firmware programming speed is greatly improved, the programming flexibility of the FPGA firmware is improved, and the method can be effectively applied to application scenes with special requirements on space and time.
Description
Technical Field
The field relates to the field of computers, and more particularly to a method, a device, equipment and a readable medium for quickly programming FPGA firmware.
Background
The FPGA is called as a field programmable gate array, the chip internally comprises abundant programmable logic units and wiring resources, and the internal logic units and the interconnection structure can be configured and changed by means of software to complete the established design function. The FPGA has high reliability, high parallel processing capability and flexible programmability, and is widely applied to the aspects of communication, medical treatment, industrial Internet and the like.
According to different FPGA implementation processes, the FPGA can be divided into an FPGA based on an SRAM structure, an FPGA based on an antifuse structure and an FPGA based on a Flash structure. The FPGA based on the SRAM structure is widely applied due to its advantages of low implementation cost, large-scale integration, high performance, etc., and at present, the FPGA products of the Altera company and the Xilinx company, which are the largest two FPGA manufacturers, are implemented based on the SRAM process. But the disadvantage is that the SRAM loses all configuration after power is lost, and the FPGA needs to be reconfigured every time it is powered up. The configuration file in which the circuit is to be implemented is generally referred to as the firmware of the FPGA.
Taking the FPGA of Xilinx as an example, the loading modes of the upper electrical firmware file are divided into a main string, a main parallel, a slave string, a slave parallel and a SelectMap. A common loading method is loading a main string, a main parallel and a SelectMAP, where the main string or the main parallel mode is loaded by an FPGA providing a clock, reading a firmware file from a board program memory to complete loading, and the SelectMAP loading is loading by an external controller reading the firmware file from the board program memory or receiving the firmware file from an external interface, and transferring the firmware file to the FPGA to complete loading. It can be seen that the FPGA basically requires an external program memory for storing configuration files when applied, and for larger-scale FPGAs, the configuration files are generally larger, and basically all adopt Flash of SPI or BPI interface as the program memory.
For the programming of the firmware, a JTAG interface programming mode is generally adopted. An FPGA manufacturer can provide a set of complete programming tool kit and a guide file, and a user stores programs and designs circuits related to an external interconnection interface according to the guide file. When the firmware is programmed, the upper computer programming tool and the hardware onboard FPGA are connected through the USB-JTAG download line, and the firmware is programmed to the program memory. At present, with the increasing of the FPGA scale, the data volume of FPGA firmware is increased, in the process of programming by adopting a JTAG interface, the firmware can be read back to an upper computer for verification after being written, and the data transmission volume in the process of programming the firmware is doubled. The programming time of the firmware of the large-scale FPGA is generally over 20 minutes due to the lower data transmission rate of the JTAG, and the USB-JTAG download line is easily interfered by the outside world, so that the programming failure of the firmware is caused, and the programming efficiency of the FPGA firmware is seriously influenced. In some special applications, the conventional firmware programming method cannot meet the requirement under the condition that the whole machine has a strict requirement on firmware programming time or cannot be connected with a JTAG (joint test action group) download line.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for fast programming an FPGA firmware, which can implement fast programming of an FPGA firmware by using the technical solution of the present invention, thereby greatly improving a firmware programming speed, improving flexibility of programming an FPGA firmware, and being effectively applied to an application scenario with special requirements on space and time.
Based on the above purpose, an aspect of the embodiments of the present invention provides a method for fast programming FPGA firmware, including the following steps:
judging whether the received data is a firmware upgrading instruction;
in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data;
in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware;
and responding to the completion of writing all the cached data into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data.
According to an embodiment of the present invention, determining whether the received data is a firmware upgrade instruction includes:
analyzing the received data, and judging whether the analyzed content contains a firmware upgrading instruction;
and determining the received data as a firmware upgrading instruction in response to the analyzed content including the firmware upgrading instruction.
According to an embodiment of the present invention, in response to that the received data is a firmware upgrade instruction, erasing the data to be written into the firmware this time and caching the subsequently received data includes:
in response to the received data being a firmware upgrading instruction, erasing the address data to be written into the firmware;
and buffering the received data again.
According to one embodiment of the invention, the threshold size is 256B.
According to an embodiment of the present invention, in response to that all the cached data is written into the firmware, reading the data written into the firmware and determining whether the firmware programming is successful according to the read data includes:
reading data written into the firmware and calculating a Cyclic Redundancy Check (CRC) of the read data;
calculating the CRC of all data in the cache, and comparing the CRC of all data in the cache with the CRC of the read data;
and judging that the firmware programming is successful in response to the fact that the CRC of all the data in the cache is the same as the CRC of the read data.
According to an embodiment of the present invention, further comprising:
and judging that the firmware programming fails in response to the fact that the CRC of all the data in the cache is different from the CRC of the read data.
According to an embodiment of the present invention, further comprising:
and in response to the failure of the firmware programming, erasing the address data written into the firmware.
In another aspect of the embodiments of the present invention, there is also provided an apparatus for fast programming FPGA firmware, where the apparatus includes:
the judging module is configured to judge whether the received data is a firmware upgrading instruction;
the cache module is configured to respond to that the received data is a firmware upgrading instruction, erase the data to be written into the firmware at this time and cache the subsequently received data;
a write-in module configured to begin writing all of the cached data into the firmware in response to the cached data reaching a threshold size;
and the reading module is configured to respond to the completion of the writing of all the cached data into the firmware, read the data written into the firmware and judge whether the firmware programming is successful according to the read data.
In another aspect of an embodiment of the present invention, there is also provided a computer apparatus including:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods described above.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program, which when executed by a processor implements the steps of any one of the above-mentioned methods.
The invention has the following beneficial technical effects: the method for rapidly programming the FPGA firmware provided by the embodiment of the invention judges whether the received data is a firmware upgrading instruction; in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data; in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware; the technical scheme of responding to the fact that all cached data are written into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data can achieve rapid programming of the FPGA firmware, greatly improve the firmware programming speed, improve the flexibility of the programming of the FPGA firmware, and can be effectively applied to application scenes with special requirements on space and time.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method for fast programming of FPGA firmware, according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a system for fast programming of FPGA firmware according to an embodiment of the present invention
FIG. 3 is a schematic diagram of an apparatus for fast programming of FPGA firmware according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer device according to one embodiment of the present invention;
fig. 5 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of a method for fast programming FPGA firmware. Fig. 1 shows a schematic flow diagram of the method.
As shown in fig. 1, the method may include the steps of:
s1 judges whether the received data is a firmware upgrade instruction.
Receiving external input data in real time, performing instruction analysis on the data, judging whether the analyzed data is a firmware upgrading instruction or not, and returning to continue receiving and analyzing the data if the firmware upgrading instruction is not analyzed.
S2, in response to the received data being a firmware upgrade instruction, erases the data to be written into the firmware this time and caches subsequently received data.
If the firmware upgrading instruction is successfully analyzed, starting firmware upgrading, sending a Flash erasing instruction, erasing address data to be written into the firmware, and sending the subsequently received data to a data cache module for caching as firmware data.
S3 begins writing all of the buffered data to firmware in response to the buffered data reaching a threshold size.
The data is continuously cached in the cache module, when the cache exceeds the threshold size, the threshold size is 256B, that is, when the data cache is larger than 256B, the data in the data cache module is read and written into the firmware, the instruction that the firmware data is sent is received after the firmware data is sent, and all the data before the instruction needs to be written into the firmware.
S4, responding to the fact that all the cached data are written into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data.
After all data are written into the firmware, the firmware data which are just written are read back and sent to the data checking module to complete CRC calculation of the read-back data, the calculation result is compared with the received firmware data CRC to determine whether the written firmware data are completely correct, if the comparison is completely consistent, the firmware programming is successful, a firmware programming success state indication is generated, if the comparison is not consistent, the firmware programming is failed, a firmware programming failure state indication is generated, and meanwhile, the address field which is just written into the firmware is erased.
According to the technical scheme, the FPGA firmware can be quickly programmed, the firmware programming speed is greatly improved, the programming flexibility of the FPGA firmware is improved, and the method can be effectively applied to application scenes with special requirements on space and time.
In a preferred embodiment of the present invention, determining whether the received data is a firmware upgrade instruction includes:
analyzing the received data, and judging whether the analyzed content contains a firmware upgrading instruction;
and determining the received data as a firmware upgrading instruction in response to the analyzed content including the firmware upgrading instruction.
In a preferred embodiment of the present invention, in response to that the received data is a firmware upgrade instruction, erasing the data to be written into the firmware this time and caching the subsequently received data includes:
in response to the received data being a firmware upgrading instruction, erasing the address data to be written into the firmware;
and buffering the received data again.
In a preferred embodiment of the present invention, the threshold size is 256B.
In a preferred embodiment of the present invention, in response to that all the cached data are written into the firmware, reading the data written into the firmware and determining whether the firmware programming is successful according to the read data includes:
reading data written in the firmware and calculating CRC of the read data;
calculating the CRC of all data in the cache, and comparing the CRC of all data in the cache with the CRC of the read data;
and judging that the firmware programming is successful in response to the fact that the CRC of all the data in the cache is the same as the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and judging that the firmware programming fails in response to the fact that the CRC of all the data in the cache is different from the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and in response to the failure of the firmware programming, erasing the address data written into the firmware. After all data are written into the firmware, the firmware data which are just written are read back and sent to the data checking module to complete CRC calculation of the read-back data, the calculation result is compared with the received firmware data CRC to determine whether the written firmware data are completely correct, if the comparison is completely consistent, the firmware programming is successful, a firmware programming success state indication is generated, if the comparison is not consistent, the firmware programming is failed, a firmware programming failure state indication is generated, and meanwhile, the address field which is just written into the firmware is erased.
The above method can be implemented by using a system shown in fig. 2, as shown in fig. 2, the system includes an external data receiving module, a data caching module, a read-write control logic module, a data checking module, and a QSPI driving module, and the implementation and functions of each module are as follows:
the external data receiving module can be connected with an external processor, completes input data receiving, completes data content analysis, judges whether a firmware upgrading instruction is received or not, and sends subsequent firmware data to the lower module. The external input interface can adopt PCIE, SRIO, Ethernet or UART and the like according to specific conditions, the module and an external exchange interface are designed into a standard AXI bus interface, so that the module can be conveniently butted with various bus IPs, and when the interfaces are not matched and can not be butted, the external input interface part of the module needs to be customized;
the data cache module can finish caching of firmware data, when the writing of the SPI Flash is considered, the data to be written in needs to be sent after an instruction is sent firstly, in order to improve the writing efficiency of the SPI interface, the FLASH writing adopts a Page writing mode, taking MT25QU type Flash of Meixin corporation as an example, the size of a Page is 256B, and therefore the writing is started when the firmware data cache is larger than 256B;
the read-write control logic module can complete the jump of a Flash read-write erasing control state machine, when a firmware programming instruction is received or a state indication of firmware programming failure is detected, a Flash erasing instruction is sent to a lower-level module, and when data of the data cache module is larger than 256B, a Flash page writing instruction and firmware data to be written are sent to the lower-level module; after firmware data is completely written in, after a firmware data sending finishing instruction is received, Flash quick reading is sent to a lower-level module, written data is read out, and the written data is sent to a data verification module for verification;
the data check module compares the data read back from the Flash with the received firmware data CRC after CRC calculation, and generates firmware upgrading state indication information according to the check result;
and the QSPI driving module finishes the read-write operation of the SPI Flash according to the operation instruction sent by the upper level. To increase the firmware programming rate, the SPI operation is in four-wire two-edge mode, with a clock frequency of 50 MHz.
According to the technical scheme, the FPGA firmware can be quickly programmed, the firmware programming speed is greatly improved, the programming flexibility of the FPGA firmware is improved, and the method can be effectively applied to application scenes with special requirements on space and time.
It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the above programs may be stored in a computer-readable storage medium, and when executed, the programs may include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided an apparatus for fast programming FPGA firmware, as shown in fig. 3, the apparatus 200 includes:
and the judging module is configured to judge whether the received data is a firmware upgrading instruction.
Receiving external input data in real time, performing instruction analysis on the data, judging whether the analyzed data is a firmware upgrading instruction or not, and returning to continue receiving and analyzing the data if the firmware upgrading instruction is not analyzed.
And the cache module is configured to erase the data to be written into the firmware and cache the subsequently received data in response to the received data being a firmware upgrading instruction.
If the firmware upgrading instruction is successfully analyzed, starting firmware upgrading, sending a Flash erasing instruction, erasing address data to be written into the firmware, and sending the subsequently received data to a data cache module for caching as firmware data.
A write module configured to begin writing all of the cached data to the firmware in response to the cached data reaching a threshold size.
The data is continuously cached in the cache module, when the cache exceeds the threshold size, the threshold size is 256B, that is, when the data cache is larger than 256B, the data in the data cache module is read and written into the firmware, the instruction that the firmware data is sent is received after the firmware data is sent, and all the data before the instruction needs to be written into the firmware.
And the reading module is configured to respond to the completion of the writing of all the cached data into the firmware, read the data written into the firmware and judge whether the firmware programming is successful according to the read data.
After all data are written into the firmware, the firmware data which are just written are read back and sent to the data checking module to complete CRC calculation of the read-back data, the calculation result is compared with the received firmware data CRC to determine whether the written firmware data are completely correct, if the comparison is completely consistent, the firmware programming is successful, a firmware programming success state indication is generated, if the comparison is not consistent, the firmware programming is failed, a firmware programming failure state indication is generated, and meanwhile, the address field which is just written into the firmware is erased.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device. Fig. 4 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 4, an embodiment of the present invention includes the following means: at least one processor S21; and a memory S22, the memory S22 storing computer instructions S23 executable on the processor, the instructions when executed by the processor implementing the method steps of:
judging whether the received data is a firmware upgrading instruction;
in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data;
in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware;
and responding to the completion of writing all the cached data into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data.
In a preferred embodiment of the present invention, determining whether the received data is a firmware upgrade instruction includes:
analyzing the received data, and judging whether the analyzed content contains a firmware upgrading instruction;
and determining the received data as a firmware upgrading instruction in response to the analyzed content including the firmware upgrading instruction.
In a preferred embodiment of the present invention, in response to that the received data is a firmware upgrade instruction, erasing the data to be written into the firmware this time and caching the subsequently received data includes:
in response to the received data being a firmware upgrading instruction, erasing the address data to be written into the firmware;
and buffering the received data again.
In a preferred embodiment of the present invention, the threshold size is 256B.
In a preferred embodiment of the present invention, in response to that all the cached data are written into the firmware, reading the data written into the firmware and determining whether the firmware programming is successful according to the read data includes:
reading data written in the firmware and calculating CRC of the read data;
calculating the CRC of all data in the cache, and comparing the CRC of all data in the cache with the CRC of the read data;
and judging that the firmware programming is successful in response to the fact that the CRC of all the data in the cache is the same as the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and judging that the firmware programming fails in response to the fact that the CRC of all the data in the cache is different from the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and in response to the failure of the firmware programming, erasing the address data written into the firmware.
In view of the above object, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. FIG. 5 is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 5, the computer readable storage medium stores S31 a computer program that, when executed by a processor, performs the method of S32:
judging whether the received data is a firmware upgrading instruction;
in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data;
in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware;
and responding to the completion of writing all the cached data into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data.
In a preferred embodiment of the present invention, determining whether the received data is a firmware upgrade instruction includes:
analyzing the received data, and judging whether the analyzed content contains a firmware upgrading instruction;
and determining the received data as a firmware upgrading instruction in response to the analyzed content including the firmware upgrading instruction.
In a preferred embodiment of the present invention, in response to that the received data is a firmware upgrade instruction, erasing the data to be written into the firmware this time and caching the subsequently received data includes:
in response to the received data being a firmware upgrading instruction, erasing the address data to be written into the firmware;
and buffering the received data again.
In a preferred embodiment of the present invention, the threshold size is 256B.
In a preferred embodiment of the present invention, in response to that all the cached data are written into the firmware, reading the data written into the firmware and determining whether the firmware programming is successful according to the read data includes:
reading data written in the firmware and calculating CRC of the read data;
calculating the CRC of all data in the cache, and comparing the CRC of all data in the cache with the CRC of the read data;
and judging that the firmware programming is successful in response to the fact that the CRC of all the data in the cache is the same as the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and judging that the firmware programming fails in response to the fact that the CRC of all the data in the cache is different from the CRC of the read data.
In a preferred embodiment of the present invention, the method further comprises:
and in response to the failure of the firmware programming, erasing the address data written into the firmware.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for quickly programming FPGA firmware is characterized by comprising the following steps:
judging whether the received data is a firmware upgrading instruction;
in response to the received data being a firmware upgrading instruction, erasing the data to be written into the firmware at this time and caching the subsequently received data;
in response to the cached data reaching a threshold size, beginning to write all of the cached data into the firmware;
and responding to the completion of writing all the cached data into the firmware, reading the data written into the firmware and judging whether the firmware programming is successful according to the read data.
2. The method of claim 1, wherein determining whether the received data is a firmware upgrade instruction comprises:
analyzing the received data, and judging whether the analyzed content contains a firmware upgrading instruction;
and determining the received data as a firmware upgrading instruction in response to the analyzed content including the firmware upgrading instruction.
3. The method of claim 1, wherein in response to the received data being a firmware upgrade instruction, erasing data to be written into the firmware this time and caching subsequently received data comprises:
in response to the received data being a firmware upgrading instruction, erasing the address data to be written into the firmware;
and buffering the received data again.
4. The method of claim 1, wherein the threshold size is 256B.
5. The method of claim 1, wherein in response to the buffered data being written to the firmware, reading the data written to the firmware and determining whether the firmware programming was successful based on the read data comprises:
reading data written in the firmware and calculating CRC of the read data;
calculating the CRC of all data in the cache, and comparing the CRC of all data in the cache with the CRC of the read data;
and judging that the firmware programming is successful in response to the fact that the CRC of all the data in the cache is the same as the CRC of the read data.
6. The method of claim 5, further comprising:
and judging that the firmware programming fails in response to the fact that the CRC of all the data in the cache is different from the CRC of the read data.
7. The method of claim 6, further comprising:
and in response to the failure of the firmware programming, erasing the address data written into the firmware.
8. An apparatus for rapidly programming FPGA firmware, the apparatus comprising:
the judging module is configured to judge whether the received data is a firmware upgrading instruction;
the cache module is configured to respond to that the received data is a firmware upgrading instruction, erase the data to be written into the firmware at this time and cache the subsequently received data;
a write module configured to begin writing all of the cached data to firmware in response to the cached data reaching a threshold size;
and the reading module is configured to respond to the completion of the writing of all the cached data into the firmware, read the data written into the firmware and judge whether the firmware programming is successful according to the read data.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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