CN113604184A - Chip packaging material, chip packaging structure and packaging method - Google Patents

Chip packaging material, chip packaging structure and packaging method Download PDF

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CN113604184A
CN113604184A CN202111176315.8A CN202111176315A CN113604184A CN 113604184 A CN113604184 A CN 113604184A CN 202111176315 A CN202111176315 A CN 202111176315A CN 113604184 A CN113604184 A CN 113604184A
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packaging material
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parts
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CN113604184B (en
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伍得
胡宗潇
廖述杭
苏峻兴
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Wuhan Sanxuan Technology Co ltd
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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/08—Macromolecular additives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
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    • C08L2203/00—Applications
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    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2205/00—Polymer mixtures characterised by other features
    • C08L2205/02—Polymer mixtures characterised by other features containing two or more polymers of the same C08L -group
    • C08L2205/025—Polymer mixtures characterised by other features containing two or more polymers of the same C08L -group containing two or more polymers of the same hierarchy C08L, and differing only in parameters such as density, comonomer content, molecular weight, structure
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2205/00—Polymer mixtures characterised by other features
    • C08L2205/03—Polymer mixtures characterised by other features containing three or more polymers in a blend

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  • General Physics & Mathematics (AREA)
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Abstract

The application discloses a chip packaging material, which comprises epoxy resin containing naphthalene rings, and a curing agent with a specific proportion, so that the warpage of the packaging material is effectively reduced, and the defect that a chip containing a copper shielding layer is easy to reversely warp due to the fact that the copper shielding layer is soft is obviously improved. In addition, the silicon rubber powder with the core-shell structure is added as the toughening agent, the warping of the packaging material is further adjusted, the packaging material is suitable for packaging chips with different sizes and different electromagnetic shielding layer thicknesses, and the usability of the packaging material is improved. Furthermore, the application provides a packaging structure and a packaging method of a chip containing the electromagnetic shielding layer, the packaging structure is simple in process, can be widely applied to packaging of the chip, and has a wide application prospect.

Description

Chip packaging material, chip packaging structure and packaging method
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a chip packaging material, a chip packaging structure, and a packaging method.
Background
In the field of electronic devices, the integration level of integrated circuit chips inside electronic products is higher and higher, electronic products are also miniaturized, but the functions of the electronic products are stronger and stronger, so that the intensity of generated electromagnetic waves is correspondingly improved, and some chips are very sensitive to electromagnetic interference, such as radio frequency chips, especially high frequency radio frequency chips, which can affect the normal performance of the chips, and even can directly or indirectly cause misoperation or system failure of electronic components and electrical equipment. Therefore, it must be protected by electromagnetic shielding.
At present, a common electromagnetic shielding manner for a chip includes disposing a metal shell in a package structure or forming a metal shielding layer on a surface of the chip. However, with the rapid development of semiconductor and electronic technologies, the demand for miniaturization of chip packages in the field of semiconductor circuits and the like is becoming more and more significant. This puts higher demands on the chip packaging technology, and the metal shell as an electromagnetic shielding structure has excessively increased the volume of the chip packaging structure, and is not suitable for small-size chip packaging. Therefore, it has become a common electromagnetic shielding structure for chips to dispose an electromagnetic shielding layer on the chip. Copper is widely applied to a metal electromagnetic shielding layer of a chip, but because the copper is made of a soft material, when the copper is arranged on the back of the chip, upward warping is easy to occur, and the stability of a chip packaging structure is affected.
At present, a novel resin-based encapsulating material with low cost, good moldability and good durability has become a gradual substitute for conventional encapsulating materials such as ceramics and metals. Common resin packaging materials are mainly thermosetting resins, such as epoxy resin, phenolic resin, silicon rubber and the like, wherein the epoxy resin packaging materials are widely applied to the fields of semiconductor devices, integrated circuits and the like due to the characteristics of high reliability, low cost, simple production and packaging processes and the like. However, the type of epoxy resin and the material composition directly affect the performance of the encapsulating material. The existing epoxy packaging material is difficult to meet the application requirement of the chip with the copper electromagnetic shielding layer. Therefore, there is still a need to develop a packaging material suitable for a chip having an electromagnetic shielding layer.
Disclosure of Invention
The application provides a chip packaging material, a chip packaging structure and a packaging method, which can correct the upward warping of an electromagnetic shielding layer on the back of a chip, and have excellent interface adhesion performance and good high-temperature fluidity.
The application provides the following technical scheme:
in one aspect, the present application provides a chip packaging material, comprising the following components in parts by weight: 5-15 parts of epoxy resin, 5-15 parts of curing agent, 0.1-1 part of curing accelerator, 60-85 parts of silicon dioxide, 0.5-2.5 parts of coupling agent and 0.1-15 parts of diluent;
wherein the epoxy resin comprises a structural unit shown as a formula (I):
Figure 365612DEST_PATH_IMAGE001
（I），
in the formula (I), R1And R2Independently selected from C1-C10 alkyl, C6-C20 aryl or C5-C10 heteroaryl.
Optionally, in some embodiments herein, the epoxy resin has an epoxy equivalent weight of 135-165 g/eq.
Optionally, in some embodiments of the present application, the epoxy resin comprises a structural unit represented by formula (II),
Figure 938545DEST_PATH_IMAGE002
(II)。
optionally, in some embodiments of the present application, the chip packaging material further includes 0.1 to 10 parts by weight of a toughening agent, where the toughening agent is a silicon rubber powder having a core-shell structure, where the core of the core-shell structure is silicon rubber, and the shell is silicon resin.
Optionally, in some embodiments herein, the particle size of the toughening agent is 2 to 60 μm.
Optionally, in some embodiments herein, the toughening agent is at least one of the cortexation chemistry KMP600, KMP601, KMP602, or KMP 605.
Optionally, in some embodiments of the present application, the silica has a particle size in the range of 0.1 to 75 μm.
Optionally, in some embodiments herein, the curing agent is selected from at least one of tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, phthalic anhydride, tetrahydrophthalic anhydride, methylnadic anhydride, and phenol-aralkyl phenolic resins.
Optionally, in some embodiments of the present application, the chip packaging material further comprises 0.02 to 0.1 parts by weight of a colorant.
On the other hand, the application also provides a chip packaging structure, which comprises a substrate, a chip reversely arranged on the substrate, and a packaging layer covering the back surface of the chip, wherein an electromagnetic shielding layer is arranged on the back surface of the chip along the direction from the substrate to the back surface of the chip, and the packaging layer comprises the packaging material.
Optionally, in some embodiments of the present application, the electromagnetic shielding layer includes a titanium metal layer, a copper metal layer, and a tin metal layer, which are sequentially stacked along one side of the substrate in a direction toward the back of the chip.
Optionally, in some embodiments of the present application, the encapsulation layer is in contact with the tin metal layer.
Optionally, in some embodiments of the present application, the thickness of the encapsulation layer is 50-210 μm.
Correspondingly, the application also provides a chip packaging method, which comprises the following steps:
providing a chip to be packaged, wherein the chip is inversely arranged on a substrate;
providing an encapsulating material; and
applying the packaging material on the back surface of the chip, and curing to form a packaging layer;
the back surface of the chip is provided with an electromagnetic shielding layer along the direction from the substrate to the back surface of the chip, and the packaging layer comprises the packaging material.
Has the advantages that:
the packaging material comprises epoxy resin shown in formula (I) and other components in a specific ratio, so that the low-stress and low-warpage packaging material is provided. According to the packaging material, the special epoxy resin with the naphthalene ring structure is compounded with the curing agent in a specific proportion, so that the warpage of the packaging material is effectively reduced, and the defect that a chip containing a copper shielding layer is easy to generate reverse warpage due to soft copper materials is obviously improved. In addition, the silicon rubber powder with the core-shell structure is added as the toughening agent, the warping of the packaging material is further adjusted, the packaging material is suitable for packaging chips with different sizes and different electromagnetic shielding layer thicknesses, and the usability of the packaging material is improved. Furthermore, the application provides a packaging structure and a packaging method of a chip containing an electromagnetic shielding layer, the packaging structure is simple in process, can be widely applied to packaging of special chips, and has a wide application prospect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a chip package structure provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of an electromagnetic shielding layer of a chip with an electromagnetic shielding layer on the back surface in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the description of this application, the term "including" means "including but not limited to". Various embodiments of the invention may exist in a range of forms; it is to be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention; accordingly, the described range descriptions should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range. For example, it is contemplated that a range description from 1 to 5 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, and a single number within the recited range, such as 1, 2,3, 4, or 5, regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any number (fractional or integer) recited within the indicated range.
The embodiment of the application provides a chip packaging material which comprises the following components in parts by weight: 5-15 parts of epoxy resin, 5-15 parts of curing agent, 0.1-1 part of curing accelerator, 60-85 parts of silicon dioxide, 0.5-2.5 parts of coupling agent and 0.1-15 parts of diluent;
wherein the epoxy resin comprises a structural unit shown as a formula (I):
Figure 921544DEST_PATH_IMAGE001
（I），
in the formula (I), R1 and R2 are independently selected from C1-C10 alkyl, C6-C20 aryl or C5-C10 heteroaryl. Alkyl includes straight chain alkyl, branched chain alkyl or cycloalkyl, provided that the carbon chain is saturated, is within the scope of the alkyl groups of the embodiments herein. Aromatic groups include groups containing one or more benzene rings, including but not limited to substituted or unsubstituted benzene rings, fused ring compounds, or biphenyl compounds, such as benzene rings, naphthalene rings, anthracene rings, biphenyl, p-terphenyl, and the like. Heteroaryl includes aromatic groups containing heteroatoms such as O, S, N.
As shown in formula (I), the epoxy resin used in the examples of the present application includes at least one naphthalene ring to improve the heat resistance of the epoxy resin, and the epoxy resin is a bifunctional epoxy resin, i.e., one epoxy molecule includes 2 epoxy groups. In some embodiments, there may also be more epoxy groups, for example 3 or 4 or more. In some embodiments, other types of epoxy resins, such as bisphenol F epoxy resins, may be formulated, and the mass ratio of the epoxy resin of formula (I) to the bisphenol F epoxy resin is in the range of (1-10): 1.
In some embodiments, the epoxy equivalent weight of the epoxy resin is 135-165g/eq, preferably 135-150 g/eq, for the curing rate and the degree of crosslinking in the chip packaging process. The viscosity (ICI, 150 ℃) of the epoxy resin is 250-3000 dPa.s; in some embodiments, the epoxy resin has a viscosity (ICI, 150 ℃) of 250-850 dPa.s. The epoxy resin can keep a proper curing rate with the curing agent and has good fluidity, so that the packaging material can flow on the surface of a chip in a packaging process and does not generate flow marks. If the viscosity is too high, good flowability is difficult to achieve at higher loading levels, if the viscosity is too low, an encapsulation layer of effective thickness is difficult to form, and the formation of a tough, low warpage encapsulation layer in the molding process is difficult to achieve.
The epoxy resin can be epoxy resin shown in formula (II). In some embodiments, HP-4032 or HP-4032D from DIC may be used, with HP-4032D being preferred.
The chip packaging material also comprises 0.1-10 parts by weight of toughening agent, such as 5-8 parts. The toughening agent is silicon rubber powder with a core-shell structure, wherein the core of the core-shell structure is silicon rubber, and the shell of the core-shell structure is silicon resin. The grain size of the toughening agent is 2-60 mu m, preferably 2-25 mu m. Optionally, in some embodiments herein, the toughening agent is at least one of the cortexation chemistry KMP600, KMP601, KMP602, or KMP 605. The toughening agent can be well dispersed in liquid epoxy resin, and the silicon rubber core can be moderately swelled to provide excellent toughness, and the toughening agent is properly added into the packaging material to enable the packaging layer to correct warpage of the electromagnetic shielding layer on the back of the chip to different degrees, so that the packaging layer with better toughness and better impact resistance is obtained.
The particle size of the silicon dioxide is 0.1-75 μm, and the silicon dioxide is used in an amount of 70-85 parts by weight. The above particle size and amount of silica may result in a low coefficient of thermal expansion of the encapsulant. In some embodiments, the silica may be fumed silica or fused silica, having a particle size of 0.1 to 75 μm, or 1 to 50 μm.
The curing agent is at least one selected from tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methyl hexahydrophthalic anhydride, phthalic anhydride, tetrahydrophthalic anhydride, methyl nadic anhydride (methyl-5-norbornene-2, 3-dicarboxylic anhydride) and phenol-aralkyl phenolic resin. The curing agent is used in an amount of 5 to 15 parts by weight, for example 10 to 12 parts. In some embodiments, the curing agent is preferably a combination of methyl nadic anhydride and methyl hexahydrophthalic anhydride in a ratio of (0.5-2): 1, more preferably 1: 1. In some embodiments, the epoxy resin and curing agent are used in amounts of (1-2): 1, preferably 1: 1. In the embodiment of the application, 0.1-1 part by weight of curing accelerator can be further added, and the curing accelerator can be selected from imidazole or N, N-dimethylaniline. The curing agent and the curing accelerator are combined with the epoxy resin in the embodiment of the application to realize the processing performances such as curing rate, fluidity and the like required by the packaging material, and ensure that the packaging material obtains a good-performance packaging layer in the packaging process.
The packaging material contains 0.5-2.5 weight parts of coupling agent. The coupling agent can increase the compatibility among all components, and particularly, under the condition that the silica filler and the toughening agent with larger specific gravity are added, the coupling agent can help the particles to be uniformly dispersed in an epoxy resin system, so that the compatibility of the system is improved. In the embodiment of the present application, the coupling agent is a silane coupling agent having an epoxy group, for example, any one selected from the group consisting of γ -glycidoxypropyltrimethoxysilane, γ -glycidoxypropyltriethoxysilane, γ -glycidoxypropyltripropoxysilane, and γ -glycidoxypropyltributoxysilane, but not limited thereto. The epoxy functional group carried by the silane coupling agent with the epoxy group can better form a curing crosslinking network with the epoxy resin in the curing process, and the compatibility of the system is further improved.
The packaging material contains 0.1-1.5 weight parts of diluent, so that the viscosity of the packaging material can be reduced under the condition of not changing the material performance as much as possible. The diluent may be selected from epoxy diluents known in the art, such as ED-509S of ADEKA. The amount of diluent should not exceed 1.5% to maintain a low total chlorine content.
The chip packaging material also comprises 0.02-0.1 weight part of colorant. In some embodiments, the pigment is carbon black. The colorant imparts a color to the encapsulation layer so that the encapsulation layer presents a differently colored appearance and facilitates printing of text on the chip.
Referring to fig. 1, the chip package structure further includes a substrate 40, a chip 10 flip-chip mounted on the substrate, and a package layer 30 covering a back surface of the chip, wherein an electromagnetic shielding layer 20 is disposed on the back surface of the chip 10 along a direction from the substrate to the back surface of the chip 10, and the package layer 30 includes the package material provided in the embodiment of the present application.
Fig. 2 illustrates a structure of a chip having an electromagnetic shielding layer on the back surface, and the electromagnetic shielding layer 20 is disposed on the back surface of the chip 10, wherein the electromagnetic shielding layer 20 includes a titanium metal layer 201, a copper metal layer 202, and a tin metal layer 203, which are sequentially stacked along one side of the substrate in the direction toward the back surface of the chip 10 (in the direction away from the back surface of the chip 10). In some embodiments, titanium metal layer 201 has a thickness of 800-1000A, copper metal layer 202 has a thickness of 15-18 μm, and tin metal layer 203 has a thickness of 1-5 μm. The copper metal layer 202 may be formed by stacking two copper films, for example, a thinner copper metal layer is formed by a magnetron sputtering process, so as to form a copper metal layer on the surface of the titanium metal layer better. The thickness of the copper metal layer formed by the magnetron sputtering process can be 2000-3000 a, and then a thicker copper metal layer is formed on the surface of the copper metal layer formed by the magnetron sputtering process, for example, the copper metal layer with the thickness of 15-20 μm is formed by an evaporation coating method or an electroplating method. The structure of the electromagnetic shielding layer 20 can achieve a good electromagnetic shielding effect, and the warpage of the electromagnetic shielding layer can achieve an excellent effect under the action of the packaging layer, thereby ensuring the stability of the chip.
The encapsulation layer is in contact with the tin metal layer. It will be understood by those skilled in the art that the electromagnetic shielding layer may be formed by a method known in the art for forming a metal layer, such as evaporation coating, electron beam evaporation coating, magnetron sputtering, multi-arc ion coating, physical vapor deposition, atomic layer deposition, or pulsed laser deposition, etc.
In some embodiments, the thickness of the encapsulation layer 30 is 50-200 μm.
In some embodiments, an encapsulation layer 30 covers the back side of the chip 10; in other embodiments, the encapsulation layer 30 covers and surrounds the chip 10. In some embodiments, a plurality of chips are spaced apart on the substrate, and the encapsulation material covers the back surfaces of the chips 10 and fills gaps between adjacent chips 10.
Accordingly, the present application also provides a chip packaging method to form the above package structure. The chip packaging method comprises the following steps:
s1, providing a chip to be packaged, wherein the chip is inversely arranged on the substrate;
s2, providing a packaging material;
s3, applying the packaging material on the back of the chip, and curing to form a packaging layer;
the back surface of the chip is provided with an electromagnetic shielding layer along the direction from the substrate to the back surface of the chip, and the packaging layer comprises the packaging material.
In some embodiments, the step of providing an encapsulation material comprises: and providing the components of the packaging material according to the proportion, and uniformly mixing to form the packaging material.
In some embodiments, the step of mixing comprises:
s11, firstly, carrying out revolution rotation type centrifugal stirring and mixing uniformly,
s21, mixing the materials by a three-roller,
s31, carrying out centrifugal stirring and defoaming to obtain the packaging material.
In step S11, during the revolving and rotating type centrifugal stirring, the temperature is controlled below 70 ℃, and the power of the rotation is 70-90% of the revolving power. In step S21, during three-roll mixing, the gap between the rolls is determined by the maximum particle size of silica, the gap between the rolls at the feeding end is 2-3 times of the maximum particle size of silica, and the gap between the rolls at the discharging end is 1.5-2 times of the maximum particle size of silica, so that the materials can be uniformly pressed by the rotation of the rolls in the gap between the rolls during mixing, and are fully mixed. The temperature is controlled to be less than or equal to 50 ℃ during the three-roller mixing, so that the advanced solidification of the materials caused by overhigh temperature is avoided. In step S31, the temperature of centrifugal stirring and defoaming is controlled to be less than or equal to 50 ℃, and the rotation power is 30-50% of the revolution power. Since the viscosity of the encapsulating material is high, if the rotation ratio is too high, the material is overheated, and undesirable property changes such as premature curing are caused.
Optionally, in some embodiments of the present application, the curing temperature in the curing step is 120-. The curing process can further improve the hardness of the packaging material, so that the packaging material can better protect the chip.
Optionally, in some embodiments of the present application, applying an encapsulation material to the back surface of the chip, and curing to form an encapsulation layer refers to casting the encapsulation material on the back surface and around the chip, and then filling the encapsulation material into a mold by using a molding process, and curing to form the encapsulation layer.
Optionally, in some embodiments of the present application, the molding process includes: and (4) prepressing and pressing by using a mould press, then decompressing and taking out, and heating and curing in an oven. The parameters of the molding process are not particularly limited, and those skilled in the art can determine the operating parameters of the molding press according to the molding process known in the art and the specific scale of the wafer and the mold.
The present application provides packaging materials suitable for use in any chip back side lamination overlay technology, including wafer level packaging.
The present application will be described in detail with reference to specific examples, which are intended to be part of the present application and are not intended to limit the present application.
Examples
The components of the encapsulating material are weighed according to the table 1, mixed, defoamed and tubulated to prepare the epoxy resin encapsulating material (encapsulating adhesive).
The mixing process comprises the following steps: centrifugally stirring for 30min at 70 ℃, wherein the rotation power is 70% of the revolution power, and the revolution speed is 1200-; mixing for 1h at the three-roller mixing temperature of 50 ℃ and the roller spacing of 30 mu m; the temperature for centrifugal stirring and defoaming is 50 ℃, and the stirring is carried out for 10 min; the rotation power is 30 percent of the revolution power, and the revolution speed is 1200-1500 r/min.
The coefficient of thermal expansion CTE1 was tested on the encapsulant of the examples and comparative examples by: curing the packaging adhesive at 130 ℃/1h to prepare a sample meeting the requirements of the standard ASTM E831-2019, and then testing the thermal expansion coefficient of the sample.
The packaging adhesives of the examples and the comparative examples are subjected to a warpage test, and the test method comprises the following steps:
covering a packaging adhesive with the thickness of 200 mu m on the upper surface of the Cu sheet, curing for 1h at 130 ℃, taking out after cooling, placing on a horizontal desktop, pressing one side of the glass slide by a weight, and measuring the distance from the other side to the desktop by a caliper.
The viscosities of the encapsulating glues of the examples and comparative examples were determined, with reference to the standard ASTM D2196-2018, at a constant temperature of 25 ℃ and with a Brookfield viscometer, with the selection of the SC4-14 spindle, at a speed of 2-10 rpm;
metal interfacial adhesion to the encapsulation pastes of examples and comparative examples, test method
And respectively dropping the glue solution on a 5 x 5mm area on a copper sheet testing interface according to the standard ASTM D1002-2010, curing for 1h at 180 ℃, and testing the shear bonding strength by using a universal tensile machine.
TABLE 1 packaging Material composition Table and Performance test results
Figure 51174DEST_PATH_IMAGE003
As can be seen from the above table, the encapsulating materials prepared in examples 1 to 5 had a lower coefficient of thermal expansion than those of comparative example 1 and comparative example 2, and exhibited warpage in different directions on the surface of the copper sheet (+ representing warpage in both sides, and-representing warpage in both sides). Specifically, it can be seen from examples 1, 3 and 2 that, when no toughening agent is added, the epoxy resin encapsulating material exhibits a large reverse warpage, and during the chip encapsulation process, although the forward warpage easily causes chip cracks, which is highly undesirable, it is desirable that the forward or reverse warpage is in a small range, and the addition of the toughening agent can keep the epoxy resin encapsulating material reverse warpage and adjust the reverse warpage to a better range, so that the encapsulating layer and the electromagnetic shielding layer are obviously in a relatively horizontal state, and the stability of the chip is effectively protected. In addition, as can be seen from comparison between example 2 and comparative example 1, the epoxy resin shown in formula (I) is adopted in the examples of the present application, so that the viscosity of the epoxy encapsulating material is further reduced, the fluidity is better, and the flow mark can be prevented from being generated on the surface of the chip.
The chip packaging material, the chip packaging structure and the packaging method provided by the embodiments of the present application are introduced in detail, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. The chip packaging material is characterized by comprising the following components in parts by weight: 5-15 parts of epoxy resin, 5-15 parts of curing agent, 0.1-1 part of curing accelerator, 60-85 parts of silicon dioxide, 0.5-2.5 parts of coupling agent and 0.1-15 parts of diluent;
wherein the epoxy resin comprises a structural unit shown as a formula (I):
Figure DEST_PATH_IMAGE001
（I），
in the formula (I), R1 and R2 are independently selected from C1-C10 alkyl, C6-C20 aryl or C5-C10 heteroaryl.
2. The chip packaging material as claimed in claim 1, wherein the epoxy resin has an epoxy equivalent of 135-165 g/eq.
3. The chip packaging material of claim 1 or 2, wherein the epoxy resin comprises a structural unit represented by formula (II),
Figure DEST_PATH_IMAGE002
(II)。
4. the chip packaging material of claim 1 or 2, further comprising 0.1-10 parts by weight of a toughening agent.
5. The chip packaging material according to claim 4, wherein the toughening agent is silicone rubber powder having a core-shell structure, wherein the core of the core-shell structure is silicone rubber, and the shell is silicone resin; the grain diameter of the toughening agent is 2-60 mu m.
6. The chip packaging material of claim 1, wherein the silica has a particle size in the range of 0.1-75 μm.
7. The chip packaging material of claim 1, wherein the curing agent is at least one selected from tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, phthalic anhydride, tetrahydrophthalic anhydride, nadic methyl anhydride, and phenol-aralkyl phenolic resin.
8. A chip packaging structure is characterized by comprising a substrate, a chip inversely arranged on the substrate, and a packaging layer covering the back of the chip, wherein the back of the chip is provided with an electromagnetic shielding layer, and the packaging layer comprises the packaging material as claimed in any one of claims 1 to 7.
9. The chip packaging structure according to claim 8, wherein the electromagnetic shielding layer comprises a titanium metal layer, a copper metal layer and a tin metal layer which are sequentially stacked along one side of the substrate in the direction from the substrate to the back surface of the chip, and the packaging layer is in contact with the tin metal layer; and/or the thickness of the packaging layer is 50-200 μm.
10. A chip packaging method comprises the following steps:
providing a chip to be packaged, wherein the chip is inversely arranged on a substrate;
providing an encapsulating material according to any of claims 1 to 7;
applying the packaging material on the back surface of the chip, and curing to form a packaging layer;
and an electromagnetic shielding layer is arranged on the back surface of the chip.
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