CN113595659B - Integrated conduction test and number writing method and device - Google Patents
Integrated conduction test and number writing method and device Download PDFInfo
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- CN113595659B CN113595659B CN202110834862.4A CN202110834862A CN113595659B CN 113595659 B CN113595659 B CN 113595659B CN 202110834862 A CN202110834862 A CN 202110834862A CN 113595659 B CN113595659 B CN 113595659B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/15—Performance testing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/29—Performance testing
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Abstract
The present disclosure provides a method of integrated conduction testing and number writing, comprising passing a conduction testing and number writing device: determining a target interface, and completing connection with a target circuit through the target interface; starting the target circuit through the target interface; waiting for a first preset time period; indicating a radio frequency unit in the target circuit to complete a calibration test through the target interface, generating a calibration value, and determining that the calibration value meets a preset condition; writing a target number into a target chip in the target circuit through the target interface; and indicating, by the target interface, that the target circuit is complete to close. An apparatus for integrated conduction testing and number writing using the method is also provided. The technical scheme of the present disclosure can integrate the common work flow in the conduction test and the writing number operation, and under the condition that interference can not occur between each other, a group of test tools and test instrument equipment are utilized to complete in the same time under one test workstation.
Description
Technical Field
The present disclosure relates to the field of circuits, and in particular, to a method and apparatus for integrated conduction testing and number writing.
Background
Currently, the circuit structure in intelligent electronic devices is widely used as analog ICs and digital ICs. Along with the development of the industrialization level of intelligent electronic equipment, the circuit structure has the characteristics of small volume, low power consumption, multiple functions and the like. Meanwhile, due to the development requirement of the Internet of things, intelligent electronic equipment used by users daily also presents a trend of everything interconnection, for example, intelligent locks, intelligent cameras, intelligent desk lamps and the like can realize wireless interconnection based on radio frequency units in a circuit structure.
In the production link of intelligent electronic equipment, various tests are required to be carried out on the intelligent electronic equipment so as to ensure that the functions of the products are good. In the single board test stage, the radio frequency unit in the circuit structure needs to be conducted with the radio frequency index. Meanwhile, before leaving the factory, address numbers, such as IMEI numbers, MEID numbers, MAC address numbers and the like, are also required to be written into the chips in the circuit structure.
In the actual production link, the conduction test of the radio frequency unit in the circuit structure is required to be completed by using one group of test tools and test instrument equipment on a single test workstation, and the writing of the serial number of the chip in the circuit structure is required to be completed by using another group of test tools and test instrument equipment on another test workstation. The conduction test of the radio frequency unit and the writing numbering operation of the chip in the circuit are carried out on different testing working stations, and all links are not matched with each other, so that the waste of manpower, testing jigs, testing instrument equipment and testing working stations is caused, and the problems of high production cost and reduced benefit are caused.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure proposes a method for integrating conduction test and write numbering operation into a complete method and corresponding execution device.
The application provides an integrated conduction test and number writing method, which comprises the following steps of passing a conduction test and number writing device: determining a target interface, and completing connection with a target circuit through the target interface; starting the target circuit through the target interface; waiting for a first preset time period; indicating a radio frequency unit in the target circuit to complete a calibration test through the target interface, generating a calibration value, and determining that the calibration value meets a preset condition; writing a target number into a target chip in the target circuit through the target interface; and indicating, by the target interface, that the target circuit is complete to close.
In some embodiments of the present application, after the determining that the calibration value meets a preset condition, the method further includes: and writing the calibration value into a radio frequency unit in the target circuit through the target interface.
In some embodiments of the present application, after the writing of the calibration value to the radio frequency unit in the target circuit through the target interface, the method further includes: waiting for a second preset time period; and writing a target number into a target chip in the target circuit through the target interface.
In some embodiments of the present application, after writing, by the target interface, a target number to a target chip in the target circuit, the method further includes: determining that the target number is successfully written; and running a verification process.
In some embodiments of the present application, the calibration test comprises: and calibrating and testing the transmitting power and the receiving power of the radio frequency unit.
In some embodiments of the present application, the calibration test comprises: calibration test of the frequency offset of the radio frequency unit.
In some embodiments of the present application, the writing, by the target interface, the target number to the target chip in the target circuit occurs before the determining that the calibration value meets a preset condition; the method further comprises: and when the target number is written into the target circuit, if the calibration value does not meet the preset condition, recovering the target number to form a recovered target number.
In some embodiments of the present application, the enabling the target circuit through the target interface includes: the target circuit is powered by a target power supply onboard the conduction test and number writing apparatus independent of the target circuit through a target interface.
In some embodiments of the present application, the target power source comprises a programmable power source.
In some embodiments of the present application, the target circuit includes a motherboard of at least one of a smart eye-shield lamp, a smart lock, and a smart camera.
In some embodiments of the present application, the destination number includes at least one of an IMEI number, a MEID number, and a MAC address number.
In some embodiments of the present application, the target interface includes at least one of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, and an HDMI interface.
The application also provides an integrated conduction test and number writing device, comprising: a memory storing at least one set of instructions for performing the method of conducting the test and writing the number; and a processor in communication with the memory, the processor executing the set of conduction test and number writing method instructions in the memory when running, and executing any one of the above integrated conduction test and number writing methods according to the set of conduction test and number writing method instructions.
In some embodiments of the present application, the integrated conduction test and number writing apparatus further comprises: the test fixture is electrically connected with the target circuit through the target interface and is in data communication with the processor through the I/O component; a test instrument establishing a radio frequency communication connection with a radio frequency unit in the target circuit, configured to receive and transmit radio frequency signals, and to provide a reference signal for calibration testing; a shielding device configured to shield a signal whose external frequency is within a target range from the outside of the shielding device, the target circuit and the test jig being disposed inside the shielding device; and a target power supply configured to provide a power source to the integrated conduction test and number writing device.
In some embodiments of the present application, the integrated conduction test and number writing apparatus further comprises: at least one group of target numbers are stored in the memory and used for calling when writing numbers; the memory may store calibration test data and calibration values therein; and the memory can store the recovery target number for being called again after the recovery of the target number.
In some embodiments of the present application, the integrated conduction test and number writing apparatus further comprises: and the MES system is used for managing and maintaining the instruction, the target number, the calibration test data and the calibration value.
The beneficial effects of the present disclosure are: the technical scheme of the present disclosure can integrate the common work flow in the conduction test and the writing number operation, and under the condition that interference can not occur between each other, a group of test tools and test instrument equipment are utilized to complete in the same time under one test workstation. The technical scheme of the disclosure can reduce the repeated operation of the factory inspection link to the circuit structure, reduce the operation time as a whole, and also can reduce the manpower, the use quantity of the test fixture, the test instrument equipment and the test workstation, thereby reducing the labor and material cost of the intelligent electronic equipment production link.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present description, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an integrated conduction testing and number writing apparatus 100 provided in accordance with some embodiments of the present disclosure;
fig. 2 is a schematic structural view of a manipulator 200 provided in accordance with some embodiments of the present disclosure;
FIG. 3 is a flow chart of a method S100-1 for integrated conduction testing and number writing provided in accordance with some embodiments of the present disclosure; and
FIG. 4 is a flow chart of another integrated conduction test and number writing method S100-2 provided in accordance with some embodiments of the present disclosure;
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting.
These and other features of the present application, as well as the operation and function of the related elements of structure, as well as the combination of parts and economies of manufacture, may be significantly improved upon in view of the following description. All of which form a part of the present application, reference is made to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the application.
The following description may significantly improve the operation and function of these and other features of the present application, as well as related elements of structure, as well as the economic efficiency of the assembly and manufacture. All of which form a part of the present application with reference to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the application. It should also be understood that the drawings are not drawn to scale.
The following is a description of technical terms in the art related to the technical scheme of the present disclosure:
MES: manufacturing Execution System, which is a production informatization management system facing the workshop execution layer of a manufacturing enterprise.
IMEI number: an international mobile equipment identity (International Mobile Equipment Identity, IMEI) for identifying each individual mobile terminal device in the mobile network, corresponding to an identity card of the mobile terminal device.
MEID number: the mobile device identifier (Mobile Equipment Identifier) is an identity identifier of a CDMA mobile terminal, and is also an unique identifier of each CDMA mobile terminal, through which the network can track and manage the terminal.
MAC address: a media access control address (Media Access Control Address) for uniquely identifying a network card in the network, and a device if one or more network cards are present, each network card requires and has a unique MAC address.
Fig. 1 is a schematic structural diagram of an integrated conduction testing and number writing apparatus 100 provided in accordance with some embodiments of the present disclosure. The apparatus 100 may include a test fixture 110, a target power supply 120, a test instrument 130, a shielding device 140, and a manipulator 200.
In some embodiments, the manipulator 200 may be a general-purpose computer or a special-purpose computer, and is communicatively connected to the test fixture, and issues test parameters through the test fixture to obtain the target current value, and complete the operation of writing the target number. The console 200 may also be a server, a personal computer, a portable computer (e.g., a notebook computer, a tablet computer, etc.), or an electronic device with other computing capabilities. For example, the manipulator 200 has an MES system running therein, and the command, the target number, the calibration test data, and the calibration value are managed and maintained by the MES system. The manipulator 200 may include one or more forms of processor 220 and various forms of memory 230. At least one set of instructions may be stored in the memory 230 for performing the method of conducting the test and writing the number; at least one set of the target numbers may be stored in the memory 230, and used for calling when writing numbers; the memory 230 may also store the recycling destination number, which is used for being called again after recycling the destination number. The processor 220 is communicatively coupled to a memory 230, and a set of method instructions for executing the conduction test and the write number in the memory 230 at run-time.
The manipulator 200 is connected to the target circuit 002 through the test tool 110, and performs conduction test and number writing on the target circuit 002. In some embodiments, the test fixture 110 may include a target interface 111; the target circuit 001 may include a circuit interface 002. The circuit interface 002 of the target circuit 001 can act as an access point for conducting tests and writing numbers. The test fixture 110 may reserve at least one target interface 111 interfacing with the circuit interface 002 according to the design requirement of the target circuit 001. The test fixture 110 may be electrically connected to the target circuit 001 through the target interface 111, and may be in data communication with the handler 200 through an I/O assembly 260 (see fig. 2). The target interface 111 may be one or more of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, an HDMI interface, or other interfaces that may provide corresponding functions.
The target power supply 120 is configured to provide a power source to the integrated conduction test and number writing apparatus and may provide power to the target circuit 001 through the test fixture 110. For example, the target power source 120 may be a programmable power source; the target power supply 120 may also be connected to the external power supply 004 at the same time. Such as shown in fig. 1, the target power source 120 may include a first end or a second end. In operation, the first end of the target power supply 120 is electrically connected to the external power supply 004 of the integrated conduction testing and number writing device 100; the second end includes a power supply interface, where the power supply interface is electrically connected to the power supply interface on the shielding device 140 when in operation, and provides a power source for the test fixture 110 and the target circuit 001. Also, a filter may be provided in the target power supply 120 to filter the interference of the low frequency signal generated from the ground line of the external power supply 004. In some embodiments, the external power supply 004 may be ac mains.
The test instrument 130 establishes a radio frequency communication connection with the radio frequency unit in the target circuit 001, is configured to receive and transmit radio frequency signals, and provides a reference signal for calibration testing. For example, the test instrument 130 may be communicatively connected to the test fixture 110 through a radio frequency interface on the shielding device 140, and the test instrument 130 thereby establishes a radio frequency communication connection with a radio frequency unit in the target circuit 001 connected to the test fixture 110.
The shielding device 140 is configured to shield a signal whose external frequency is within a target range from the outside of the shielding device. The target circuit 001 and the test fixture 110 are disposed inside the shielding device 140. For example, the shielding device 140 may be a shielding case structure. The shielding case structure may be made of an electrically conductive material or a magnetically conductive material. The material of the shielding box structure may be related to the frequency band of the target signal to be shielded and/or the shielding effect to be achieved. The shielding box structure may be opened and closed. When the shielding case structure is in the open state, the target circuit 001 may be placed in the shielding case structure and electrically connected with the test fixture 110 through the target interface 111. When the shielding box structure is in a closed state, the shielding box structure can shield wireless signals transmitted and radiated from the outside so as to provide a non-interference testing environment for an internal tested target circuit 001.
For another example, a power interface is disposed on the shielding device 140, and the power interface is electrically connected to the test fixture 110 at one end inside the shielding device 140, and is electrically connected to the target power source 120 at the other end outside the shielding device. The target power source 120 provides power to the test fixture 110 and the target circuit 001 through the power interface. The shielding device 140 is further provided with a communication serial port, and the communication serial port is in communication connection with the test fixture 110 at one end inside the shielding device 140, and is in communication connection with the manipulator 200 at the other end outside through the I/O assembly 260 (see fig. 2). The manipulator 200 establishes data communication with the test fixture 110 through the communication serial port. The shielding device 140 is further provided with a radio frequency interface, and the radio frequency interface is connected with the test fixture 110 in a communication manner at one end inside the shielding device 140, and is connected with the test instrument 130 in a communication manner at the other end outside the shielding device. The test instrument 130 establishes a radio frequency communication connection with the radio frequency unit in the target circuit 001 through the radio frequency interface to complete a calibration test.
Fig. 2 is a schematic structural view of a manipulator 200 provided in accordance with some embodiments of the present disclosure.
For example, the operator 200 may include a communication port 250, which communication port 250 may be connected to the network 003 or out of the network 003 to which it is connected to facilitate data communication, which may be accessed remotely by an operator to execute the operating instructions therein. Manipulator 200 may also include a processor 220 in the form of one or more processors, only one processor 220 being depicted in data processing device 200 in this application for illustrative purposes only. The handler 200 may also include an internal communication bus 210 that may connect the various device components, as well as various forms of memory 230, such as a magnetic disk 232 (non-transitory memory), and a read-only memory (ROM) 234 or Random Access Memory (RAM) 236, etc., for storing various data files to be processed and/or transferred. The storage medium may be a storage medium local to the operating machine 200, or may be a storage medium shared by the operating machine 200 (for example, a shared storage medium obtained from the network 003 by using the communication port 250, for example, a cloud platform). The handler 200 may also include program instructions stored in the ROM 234, ram 246, and/or other types of non-transitory storage media to be executed by the processor 220.
The handler 200 may also include an I/O component 260 to support data communication with other functional components in the integrated conduction test and number writing device 100. The handler 200 may also receive remote access and obtain data via the network 003.
The processor 220 may be in the form of one or more processors, and in some embodiments, the processor 220 may include one or more hardware processors, such as microcontrollers, microprocessors, reduced Instruction Set Computers (RISC), application Specific Integrated Circuits (ASICs), application specific instruction set processors (ASIPs), central Processing Units (CPUs), graphics Processing Units (GPUs), physical Processing Units (PPUs), microcontroller units, digital Signal Processors (DSPs), field Programmable Gate Arrays (FPGAs), advanced RISC Machines (ARM), programmable Logic Devices (PLDs), any circuit or processor capable of executing one or more functions, or the like, or any combination thereof. For illustrative purposes only, only one processor 220 is depicted in the manipulator 200.
However, one of ordinary skill in the art will appreciate that the manipulator 200 of the present application may also include multiple processors. The methods/steps/operations described herein as being performed by one processor may also be performed by multiple processors, either together or separately. For example, if in the present application, the processor of the manipulator 200 may perform step a and step B simultaneously. It will be appreciated that step a and step B may also be performed jointly by two different processors. For example, the first processor performs step a, the second processor performs step B, or the first processor and the second processor together perform steps a and B.
Fig. 3 is a flow chart of a method S100-1 for integrated conduction testing and number writing provided in accordance with some embodiments of the present disclosure. The method S100-1 may be performed by the integrated conduction test and number writing apparatus 100. For example, some steps may be performed by the manipulator 200. In particular, the processor 220 may be communicatively coupled to the memory 230 when conducting the test and writing the number, and read the one or more sets of instructions stored in the memory 230. The one or more sets of instructions instruct the processor 220 to complete the flow of the method S100-1.
The operation of the method S100-1 presented below is intended to be illustrative and not limiting. In some embodiments, the method S100-1 may be implemented with one or more additional operations not described, and/or with one or more operations described herein omitted. Furthermore, the order of execution shown in the figures and described below is not limited in this regard.
S110, determining a target interface, and completing connection with a target circuit through the target interface.
For example, the operator opens the shielding device 140, connects the target circuit 001 to the target interface 111 of the test fixture 110 disposed inside the shielding device 140, and then closes the shielding device 140, which may be performed by other machines (e.g., an automatic device). The test fixture 110 is electrically connected to the target circuit 001 through the target interface 111. After the connection is completed, the processor 220 may detect that a corresponding load is present on the target interface 111. For example, the target interface 111 may include any one or more of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, and an HDMI interface, or other interfaces that may provide corresponding functions. For example, the target circuit 001 may be a motherboard of an intelligent lockset, an intelligent eye-protecting lamp, and an intelligent camera, and may also be a circuit structure of other intelligent electronic devices.
S120, starting the target circuit through the target interface.
For example, the processor 220 may control the integrated conduction test and number writing device 100 to send instructions to the target circuit 001 via the target interface 111 to activate the target circuit 001. Specifically, step S120 may include steps S121, S122, S123.
S121, starting the target power supply to supply power to the target circuit.
For example, the processor 220 may instruct, via the target interface 111, that the target circuit 001 be powered by the target power supply 120 that is self-contained with the conduction test and number writing apparatus 100 that is independent of the target circuit 001.
S122, indicating that the target circuit completes system startup.
For example, the processor 220 sends a handshake instruction to the target circuit 001 through the target interface 111, activates the target circuit 001, and waits for the target circuit 001 to complete a system start.
S123, acquiring starting self-checking information of the target circuit.
For example, the processor 220 obtains the start-up self-test information of the target circuit 001, including system version information, start-up time information, and radio frequency status information, through the target interface 111.
S130, waiting for a first preset time period.
For example, after the target circuit 001 is started, the processor 220 waits for a preset period of time. After the target circuit 001 is stably operated, the processor 220 performs a subsequent process method again. The first preset duration may be set according to different target circuits.
S140, indicating the radio frequency unit in the target circuit to complete a calibration test through the target interface, generating a calibration value, and determining that the calibration value meets a preset condition;
specifically, step S140 may include steps S141, S142.
S141, indicating the radio frequency unit in the target circuit to complete the calibration test of the frequency offset through the target interface, generating a calibration value of the frequency offset, and determining that the calibration value meets a preset condition.
For example, after the target circuit 001 completes the start-up and steady operation, the processor 220 transmits a calibration test instruction for performing frequency offset to the target circuit 001 through the target interface 111, and then receives feedback frequency offset calibration test data from the target interface 111, and generates a calibration value according to the calibration test data. The processor 220 compares the calibration value with a reference signal provided by the test instrument 130 to determine whether a predetermined condition is satisfied. If the calibration value meets the preset condition, the processor 220 continues to execute the flow step S142, otherwise, the processor 220 closes the target circuit if the calibration value indicates that the radio frequency unit of the target circuit is not operating normally and is an unacceptable product.
S142, indicating the radio frequency unit in the target circuit to complete calibration test of the transmitting power and the receiving power through the target interface, generating calibration values of the transmitting power and the receiving power, and determining that the calibration values meet preset conditions.
For example, the processor 220 transmits a calibration test instruction for performing transmit power and receive power to the target circuit 001 through the target interface 111, then receives calibration test data of the transmit power and the receive power fed back from the target interface 111, and generates a calibration value according to the calibration test data. The processor 220 compares the calibration value with the reference signal to determine whether a preset condition is satisfied. If the calibration value meets the preset condition, the processor 220 continues to execute the flow step S150, otherwise, the processor 220 closes the target circuit if the calibration value indicates that the radio frequency unit of the target circuit is not operating normally and belongs to an unqualified product.
S150, writing the calibration value into the radio frequency unit in the target circuit through the target interface.
For example, the processor 220 determines that the calibration values of the transmit power and the receive power, and the calibration value of the frequency offset satisfy the preset condition. The processor 220 writes the calibration value to the radio frequency unit in the target circuit 110 via the target interface 111.
S160, writing a target number into a target chip in the target circuit through the target interface.
For example, the processor 220 invokes a destination number stored in the memory 230, and then may immediately write the destination number to the destination chip in the destination circuit 001 via the destination interface 111. The processor 220 is thus able to reduce instruction execution time. Or the processor 220 may call the target number stored in the memory 230, then wait for a second preset period of time, and write the target number to the target chip in the target circuit 001 through the target interface 111. The processor 220 is thus able to reduce the likelihood of a write instruction of the calibration value colliding with a write instruction of the target number. The second preset duration may be set according to different target circuits.
S170, after the target serial numbers are written into the target chips in the target circuit through the target interface, the successful writing of the target serial numbers is determined, and then a verification process is operated.
For example, the processor 220 reads the target number that has been written in the target chip through the target interface 111. The processor 220 compares the read target number that has been written to the target number called from the memory 230 and then runs a verification process. In some embodiments, the destination number may be any one or more of an IMEI number, MEID number, MAC address, and other common address numbers.
S190, indicating the target circuit to finish closing through the target interface.
For example, the processor 220 sends a release instruction to the target circuit 001 via the target interface 111, and then waits for the target circuit 001 to complete a system shutdown. The processor 220 indicates to the target circuit 001 through the target interface 111 that power down is complete when the target circuit 001 is system-off.
Fig. 4 is a flow chart of another integrated conduction test and number writing method S100-2 provided in accordance with some embodiments of the present disclosure. The same steps are numbered in fig. 4 as in fig. 3. The method S100-2 may be performed by the integrated conduction test and number writing apparatus 100. For example, some steps may be performed by the manipulator 200. In particular, the processor 220 may be communicatively coupled to the memory 230 when conducting the test and writing the number, and read the one or more sets of instructions stored in the memory 230. The one or more sets of instructions instruct the processor 220 to complete the flow of the method S100-2.
The operation of the method S100-2 presented below is intended to be illustrative and not limiting. In some embodiments, the method S100-2 may be implemented with one or more additional operations not described, and/or with one or more operations described herein omitted. Furthermore, the order of execution shown in the figures and described below is not limited in this regard.
S110, determining a target interface, and completing connection with a target circuit through the target interface.
S120, starting the target circuit through the target interface.
S130, waiting for a first preset time period.
S160, writing a target number into a target chip in the target circuit through the target interface.
S141, indicating the radio frequency unit in the target circuit to complete the calibration test of the frequency offset through the target interface, generating a calibration value of the frequency offset, and determining that the calibration value meets a preset condition.
If the calibration value meets the preset condition, the radio frequency unit of the target circuit 001 is indicated to be operating normally, and the processor 220 executes the process step S142.
If the calibration value does not meet the preset condition, the radio frequency unit of the target circuit 001 is not normally operated, and product quality rechecking is required. Since the above numbers are generally assigned by the relevant management department, it is necessary to occupy public resources and pay a license fee, and thus if the target circuit 001 is a defective product, it is necessary to recycle the target number. Accordingly, if the calibration value does not satisfy the preset condition, the processor 220 performs the process of recovering the target number in step S180, and then the processor 220 instructs the target circuit to complete the shutdown.
S142, indicating the radio frequency unit in the target circuit to complete calibration test of the transmitting power and the receiving power through the target interface, generating calibration values of the transmitting power and the receiving power, and determining that the calibration values meet preset conditions.
If the calibration value meets the preset condition, the rf unit of the target circuit 001 is indicated to be operating normally, and the processor 220 executes the flow step S150.
If the calibration value does not meet the preset condition, the radio frequency unit of the target circuit 001 is not normally operated, and product quality rechecking is required. The processor 220 performs the process of recovering the target number in step S180, and then the processor 220 instructs the target circuit to complete the shutdown.
S150, writing the calibration value into the radio frequency unit in the target circuit through the target interface.
S170, after the target serial numbers are written into the target chips in the target circuit through the target interface, the successful writing of the target serial numbers is determined, and then a verification process is operated.
And S180, when the target number is written into the target circuit, and the calibration value does not meet the preset condition, recovering the target number to form a recovery target number. For example, the processor 220 writes a target number to a target chip in the target circuit 001 through the target interface 111 before the processor 220 determines that the calibration value satisfies a preset condition. After the target number has been written into the target circuit 001, the processor 220 determines that the calibration value meets a preset condition, and then continues to execute the flow step; otherwise, the processor 220 recovers the target number to form a recovered target number, and then closes the target circuit. The recycle destination number is stored in the memory 230 and can be recalled.
S190, indicating the target circuit to finish closing through the target interface.
Another aspect of the present disclosure provides a computer-readable storage medium. The storage medium stores therein the method instructions for integrated conduction testing and number writing. When executed by a processor, the instructions direct the processor to perform the steps of the integrated conductivity test and number writing method described in the present disclosure. In some possible implementations, aspects of the disclosure may also be implemented in the form of a program product including program code. The program product for implementing the method described above may be a portable compact disc read only memory (CD-ROM) comprising program code and may be run on a data processing device. However, the program product of the present disclosure is not limited thereto, and in the present disclosure, the readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system (e.g., processor 220). The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the processor 220, partly on the integrated conduction test and number writing device 100, as a stand-alone software package, partly on a data processing device, partly on a remote computing device, or entirely on a remote computing device.
In view of the foregoing, it will be evident to a person skilled in the art that the foregoing detailed disclosure may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present disclosure is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be proposed by this disclosure, and are intended to be within the spirit and scope of the exemplary embodiments of this disclosure.
Furthermore, certain terms in the present disclosure have been used to describe embodiments of the present disclosure. For example, "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. Thus, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various portions of this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined as suitable in one or more embodiments of the disclosure.
It should be appreciated that in the foregoing description of embodiments of the disclosure, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure. Alternatively, the disclosure is in turn to disperse various features in a plurality of embodiments of the disclosure. However, this is not to say that a combination of these features is necessary, and it is entirely possible for a person skilled in the art to extract some of them as separate embodiments to understand them upon reading this disclosure. That is, embodiments in this disclosure may also be understood as an integration of multiple secondary embodiments. While each secondary embodiment is satisfied by less than all of the features of a single foregoing disclosed embodiment.
In some embodiments, numbers expressing quantities or properties used to describe and claim certain embodiments of the disclosure are to be understood as being modified in some instances by the term "about", "approximately" or "substantially". For example, unless otherwise indicated, "about", "approximately" or "substantially" may mean a 20% change in the value it describes. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by the particular embodiment. In some embodiments, numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible.
Each patent, patent publication, and other material, e.g., articles, books, publications, documents, articles, etc., cited herein is hereby incorporated by reference. The entire contents for all purposes, except for any prosecution file history associated therewith, may be any identical prosecution file history inconsistent or conflicting with this file, or any identical prosecution file history which may have a limiting influence on the broadest scope of the claims. Now or later in association with this document. For example, if there is any inconsistency or conflict between the description, definition, and/or use of terms associated with any of the incorporated materials, the terms in the present document shall prevail.
Finally, it should be understood that the embodiments disclosed herein are illustrative of the principles. Other modified embodiments are also within the scope of this disclosure. Accordingly, the embodiments of the present disclosure are by way of example only and not by way of limitation. Those skilled in the art can adopt alternative arrangements to implement the teachings of the present disclosure in accordance with embodiments thereof. Accordingly, embodiments of the present disclosure are not limited to those precisely described in the disclosure.
Claims (13)
1. A method for integrated conduction testing and number writing, comprising the steps of:
determining a target interface, and completing connection with a target circuit through the target interface;
starting the target circuit through the target interface;
waiting for a first preset time period;
if the target interface indicates that the radio frequency unit in the target circuit completes the calibration test of the frequency offset, generating a calibration value of the frequency offset, determining that the calibration value of the frequency offset meets the preset condition, and
the target interface indicates that the radio frequency unit in the target circuit finishes the calibration test of the transmitting power and the receiving power, generates the calibration value of the transmitting power and the calibration value of the receiving power, and determines that the calibration value of the transmitting power and the calibration value of the receiving power meet the preset condition, and then the target interface writes the calibration value of the frequency offset, the calibration value of the transmitting power and the calibration value of the receiving power into the radio frequency unit in the target circuit;
if any one of the calibration value of the frequency offset, the calibration value of the transmitting power and the calibration value of the receiving power does not meet the preset condition, the target circuit is indicated to be closed through the target interface;
writing a target number into a target chip in the target circuit through the target interface; and
and indicating the target circuit to finish closing through the target interface.
2. The integrated conduction test and number writing method of claim 1, further comprising, after said writing said calibration value to a radio frequency unit in said target circuit via said target interface:
waiting for a second preset time period; and
and writing a target number into a target chip in the target circuit through the target interface.
3. The method for integrated conduction testing and number writing according to claim 1, wherein after writing a target number to a target chip in the target circuit through the target interface, further comprising:
determining that the target number is successfully written; and
and running a verification process.
4. The integrated conduction test and number writing method of claim 1, wherein said writing a target number to a target chip in said target circuit via said target interface occurs before said determining that said calibration value meets a preset condition; and
the method further comprises the steps of: and when the target number is written into the target circuit, if the calibration value does not meet the preset condition, recovering the target number to form a recovered target number.
5. The integrated conduction testing and number writing method of claim 1, wherein said enabling said target circuit through said target interface comprises: the target circuit is powered by a target power supply onboard the conduction test and number writing apparatus independent of the target circuit through a target interface.
6. The integrated conduction testing and number writing method of claim 5 wherein said target power source comprises a programmable power source.
7. The integrated conduction testing and number writing method of claim 1, wherein the target circuit comprises a motherboard of at least one of a smart eye-shield lamp, a smart lock, and a smart camera.
8. The integrated conduction testing and number writing method of claim 1, wherein the target number comprises at least one of an IMEI number, a MEID number, and a MAC address number.
9. The integrated conduction testing and number writing method of claim 1, wherein the target interface comprises at least one of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, and an HDMI interface.
10. An integrated conduction testing and number writing apparatus comprising:
a memory storing at least one set of instructions for performing the method of conducting the test and writing the number; and
a processor in communication with the memory, the processor executing the set of conductive test and write method instructions in memory and performing the method of any of claims 1 to 9 in accordance with the set of conductive test and write method instructions.
11. An integrated conduction testing and number writing apparatus as recited in claim 10, further comprising:
the test fixture is electrically connected with the target circuit through the target interface and is in data communication with the processor through the I/O component;
a test instrument establishing a radio frequency communication connection with a radio frequency unit in the target circuit, configured to receive and transmit radio frequency signals, and to provide a reference signal for calibration testing;
a shielding device configured to shield a signal whose external frequency is within a target range from the outside of the shielding device, the target circuit and the test jig being disposed inside the shielding device; and
a target power supply configured to provide a power source to the integrated conduction test and number writing device.
12. The integrated conductivity test and number writing device according to claim 10, further comprising, said memory storing at least one set of said target numbers for recall in writing numbers; the memory may store calibration test data and calibration values therein; and the memory can store the recovery target number for being called again after the recovery of the target number.
13. An integrated conduction test and number writing apparatus as recited in claim 10 further comprising an MES system through which said instructions, target numbers, calibration test data, and calibration values are managed.
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