CN114117973A - Logic synthesis method, device and storage medium - Google Patents
Logic synthesis method, device and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a logic synthesis method, a logic synthesis device and a logic synthesis storage medium, and belongs to the technical field of communication. The method comprises the following steps: the method comprises the steps of obtaining comprehensive input data of a target module according to module comprehensive configuration information in a target configuration file, sending the comprehensive input data of the target module and a starting command of a logic synthesis tool to a first target server, obtaining a logic synthesis tool operated by the first target server, carrying out logic synthesis on the comprehensive input data of the target module to obtain a netlist file and a first report file, sending the netlist file to a second target server when the first report file is determined to meet comprehensive result tracking information in the target configuration file, and sending the netlist file and the comprehensive input data to a third target server. The logic synthesis method improves the efficiency of logic synthesis.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip design in an integrated circuit, in particular to a logic synthesis method, logic synthesis equipment and a storage medium.
Background
Integrated circuit technology is a key technology of modern information technology. With the rapid development of communication technology, the performance requirements of integrated circuits are higher and higher, the logic scale of the integrated circuits is larger and larger, and the design cycle is shorter and shorter due to market competition. How to shorten the development cycle of the integrated circuit under the condition of ensuring the success rate becomes a great challenge for designers of the integrated circuit. The field of digital integrated circuit design is generally divided into digital front-end design and digital back-end design. Wherein, the digital front end design includes: the method comprises the steps of algorithm, hardware architecture design and analysis, Register-transfer Level (RTL) circuit code implementation, checking and function verification of RTL circuit codes, logic synthesis, static time sequence analysis and form verification.
Currently, logic synthesis, static timing analysis and formal verification are achieved by the following steps: acquiring an RTL circuit code finished by a front end; manually starting a logic synthesis tool, realizing logic synthesis through the synthesis tool, mapping the RTL circuit code into a netlist file related to the process library and obtaining a related output report file; after the logic synthesis tool is determined to be operated completely, manually starting a static time sequence analysis tool, and performing static time sequence analysis by the static time sequence analysis tool through the netlist file, the process library file and the written constraint file to obtain a relevant report of time sequence analysis; after the static time sequence analysis tool is determined to be operated completely, manually starting a formal verification tool, and verifying the correctness of the netlist file through the netlist file and the RTL circuit code by the formal verification tool to obtain a formal verification report; and manually confirming whether related files such as a netlist file generated by the RTL circuit code through logic synthesis, static timing analysis and formal verification, a related report of the timing analysis, a formal verification report and the like meet design conditions, and delivering the related files under the condition of meeting the design conditions.
However, in the above process, the logic synthesis tool needs to be manually started, and a large amount of manpower is consumed to confirm whether the logic synthesis tool is completely operated, so that the efficiency of logic synthesis is low.
Disclosure of Invention
The embodiments of the present invention mainly aim to provide a logic synthesis method, device, and storage medium, which aim to implement a function of improving the efficiency of logic synthesis.
In order to achieve the above object, an embodiment of the present invention provides a logic synthesis method, including the following steps:
acquiring comprehensive input data of a target module according to the module comprehensive configuration information in the target configuration file;
sending the integrated input data of the target module and a starting command of a logic integrated tool to a first target server;
acquiring a netlist file and a first report file after the first target server operates the logic synthesis tool and performs logic synthesis on the synthesis input data of the target module;
and when the first report file is determined to meet the comprehensive result tracking information in the target configuration file, sending the netlist file to a second target server, and sending the netlist file and the comprehensive input data to a third target server.
To achieve the above object, an embodiment of the present invention further provides a logic synthesis apparatus, which includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program implements the steps of the foregoing method when executed by the processor.
To achieve the above object, an embodiment of the present invention provides a storage medium for a computer-readable storage, the storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the steps of the foregoing method.
The logic synthesis method, device and storage medium provided by the embodiment include: the method comprises the steps of obtaining comprehensive input data of a target module according to module comprehensive configuration information in a target configuration file, sending the comprehensive input data of the target module and a starting command of a logic synthesis tool to a first target server, obtaining a logic synthesis tool operated by the first target server, carrying out logic synthesis on the comprehensive input data of the target module to obtain a netlist file and a first report file, sending the netlist file to a second target server when the first report file is determined to meet comprehensive result tracking information in the target configuration file, and sending the netlist file and the comprehensive input data to a third target server. According to the logic synthesis method, on one hand, the logic synthesis tool can be automatically started, a netlist file and a first report file formed after the logic synthesis tool is operated can be obtained, the logic synthesis efficiency is improved, on the other hand, the first report file can be automatically verified according to a target configuration file, whether the next process can be carried out or not is confirmed, and the logic synthesis efficiency is further improved.
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FIG. 1 is a schematic flow chart diagram illustrating a logic synthesis method according to an embodiment;
FIG. 2 is a schematic flow chart diagram illustrating a logic synthesis method according to another embodiment;
FIG. 3 is a schematic flow chart diagram illustrating a logic synthesis method according to yet another embodiment;
FIG. 4 is a diagram illustrating a file structure of a logic synthesis platform according to an embodiment;
FIG. 5 is a schematic diagram of a logic synthesis apparatus according to an embodiment;
fig. 6 is a schematic structural diagram of a logic synthesis apparatus according to an embodiment.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the invention and are not limiting of the embodiments of the invention.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the description of the embodiments of the present invention, and have no peculiar meaning by themselves. Thus, "module", "component" or "unit" may be used mixedly.
Fig. 1 is a flowchart of a logic synthesis method according to an embodiment. The embodiment is suitable for the integrated circuit design and the logic synthesis scene. The basic circuit in this embodiment refers to a kind of micro-electronic device or component. The present embodiment may be performed by a logic synthesis apparatus, which may be implemented by software and/or hardware, and may be integrated in a computer device. As shown in fig. 1, the logic synthesis method provided in this embodiment includes the following steps:
step 101: and acquiring the comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file.
For today's increasingly complex VLSI designs, the traditional top-down logic synthesis approach is not suitable, and the bottom-up logic synthesis approach is currently used. Therefore, not only can all parts of the whole design be synthesized in parallel, the synthesis time is reduced, but also the modules can be conveniently and comprehensively optimized, and the requirement on the memory is reduced. The embodiment is realized on the basis of block-type synthesis, and corresponding logic synthesis operation flow and logic synthesis delivery are realized in parallel for each block-type module.
The target configuration file in this embodiment is a file written in advance and preset in the logic synthesis apparatus. The target configuration file is a configuration file corresponding to the target project. The target item in this embodiment refers to an item to be logically integrated. The target item in this embodiment includes at least one target module. The purpose of logic synthesis in this embodiment is to describe the RTL circuit code of the target module as a netlist file at the gate level.
The target configuration file includes integrated configuration information. The integrated configuration information in this embodiment may include: the name of the target module and the version number of the corresponding RTL circuit code.
Alternatively, the logic synthesis apparatus may execute step 101 under external triggering, or may automatically execute step 101. The logic synthesis device can go to a preset storage area for storing RTL circuit codes according to the module synthesis configuration information to acquire the synthesis input data of the target module. In this embodiment, the acquired comprehensive input data of the target module may at least include: RTL circuit code of the target module. Further, the synthetic input data may also include a constraint file for the target module.
Step 102: and sending the integrated input data of the target module and the starting command of the logic integrated tool to the first target server.
In one embodiment, the first target server is a preset server.
In another embodiment, the first target server is a server determined from a cluster of servers. This implementation will be described in detail in the embodiment shown in fig. 3.
After the logic synthesis device obtains the synthesis input data of the target module, it may automatically perform step 102: and sending the integrated input data of the target module and the starting command of the logic integrated tool to the first target server.
In order to complete the logic synthesis process, other files required for logic synthesis, such as a constraint file of the target module and a running script file of the logic synthesis tool, may also be included in the start command of the logic synthesis tool.
Alternatively, the logic synthesis tool in this embodiment may be a Design Compiler (DC).
The first target server has previously installed therein a logic synthesis tool. After receiving the starting command of the logic synthesis tool, the first target server can start the logic synthesis tool, operate the logic synthesis tool and carry out logic synthesis on the synthesis input data of the target module.
Step 103: and acquiring a netlist file and a first report file after the first target server operates a logic synthesis tool and performs logic synthesis on the synthesis input data of the target module.
In this embodiment, the logic synthesis apparatus may determine whether the first target server is completely operated at a preset frequency. And when the first target server is determined to be operated completely, obtaining a netlist file and a first report file of the first target server after logic synthesis. The netlist file in this embodiment may also be referred to as a gate-level netlist file, which is a file for describing the connection relationship of circuit elements with each other.
For example, the logic synthesis apparatus may read the work log of the first target server at a preset frequency. When it is determined that the netlist file indicating the target module in the working log has been generated, it is determined that the first target server is running completely.
In one implementation, the start command of the logical synthesis tool includes parameter information of the logical synthesis tool. The parameter information of the logic synthesis tool in this embodiment includes a version of the logic synthesis tool and an operation mode of the logic synthesis tool. The parameter information of the logic synthesis tool is set in the starting command of the logic synthesis tool, so that the logic synthesis tool matched with the target module can be started conveniently and operated in a matched mode, and the expandability and the flexibility of the logic synthesis process are improved.
The first report file in this embodiment includes timing information in the logic synthesis process and other information related to logic synthesis.
Step 104: and when the first report file is determined to meet the comprehensive result tracking information in the target configuration file, sending the netlist file to a second target server, and sending the netlist file and the comprehensive input data to a third target server.
The target configuration file in this embodiment further includes integrated result tracking information. The integrated result tracking information is used to indicate the required form of the logically integrated report file. When the first report file is determined to meet the comprehensive result tracking information in the target configuration file, the obtained netlist file of the target module can be subjected to next time sequence analysis and form verification. The specific report analysis process may be: and filtering the ignorable warning and error in the first report file according to the filtering information in the comprehensive result tracking information of the target configuration file, and then judging according to the filtered information and obtaining the conclusion whether the whole logic comprehensive process is successful or not.
In one implementation, the integrated result tracking information includes: general integrated result tracking information and integrated result tracking information specific to the target module. In order to further improve efficiency, when the first report file meets the general comprehensive result tracking information and the target module-specific comprehensive result tracking information, the netlist file can be sent to the second target server, and the netlist file and the comprehensive input data can be sent to the third target server in parallel. Through double information filtering, the first report file can be further ensured to meet the requirement form, and the efficiency of subsequent time sequence analysis and form verification is improved.
The second target server in this embodiment may be a server running the timing analysis tool, and the third target server may be a server running the form verification tool.
The timing analysis in this embodiment may be a static timing analysis. The timing analysis tool in this embodiment may be PrimeTime, and the format verification tool may be Formality.
In an embodiment, the second target server and the third target server are preset servers.
In another embodiment, the second target server and the third target server are servers determined from a server cluster. This implementation will be described in detail in the embodiment shown in fig. 3.
In the field of integrated circuit design, it is often necessary to convert RTL circuit code into the correct netlist file after inspection and functional verification of the RTL circuit code is completed. The RTL code is converted into a netlist file through logic synthesis, timing information of the netlist file is verified through timing analysis, the consistency of the netlist file and the RTL circuit code is verified through formal verification, and after the steps are carried out without errors, the processed netlist file and the report file are delivered to a digital back end to carry out next-step design.
The logic synthesis method provided by the embodiment comprises the following steps: the method comprises the steps of obtaining comprehensive input data of a target module according to module comprehensive configuration information in a target configuration file, sending the comprehensive input data of the target module and a starting command of a logic synthesis tool to a first target server, obtaining a logic synthesis tool operated by the first target server, carrying out logic synthesis on the comprehensive input data of the target module to obtain a netlist file and a first report file, sending the netlist file to a second target server when the first report file is determined to meet comprehensive result tracking information in the target configuration file, and sending the netlist file and the comprehensive input data to a third target server. According to the logic synthesis method, on one hand, the logic synthesis tool can be automatically started, a netlist file and a first report file formed after the logic synthesis tool is operated can be obtained, the logic synthesis efficiency is improved, on the other hand, the first report file can be automatically verified according to a target configuration file, whether the next process can be carried out or not is confirmed, and the logic synthesis efficiency is further improved.
Fig. 2 is a schematic flow chart of a logic synthesis method according to another embodiment. The present embodiment provides a detailed description of the steps after step 104 based on the embodiment shown in fig. 1 and various alternatives. As shown in fig. 2, the logic synthesis method provided in this embodiment further includes the following steps:
step 105: and sending a starting command of the timing analysis tool to the second target server.
Step 106: and sending a starting command of the form verification tool to the third target server.
In one implementation, the netlist file may be sent to a second target server, while the start command of the timing tool may be sent to the second target server. And sending a starting command of the formal verification tool to the third target server while sending the netlist file and the comprehensive input data to the third target server.
The second target server has installed therein a timing analysis tool in advance. After receiving the starting command of the timing analysis tool, the second target server can start the timing analysis tool, run the timing analysis tool, and calculate and predict the timing of the netlist file.
Optionally, to implement the timing analysis, the start command of the timing analysis tool may further include other files required for the timing analysis, such as a process library file, and a constraint file of the target module.
The third target server has installed a formal verification tool in advance. After receiving the start command of the formal verification tool, the third target server can start the formal verification tool, run the formal verification tool and verify the netlist file.
Optionally, to implement formal verification, the launch command of the formal verification tool may also include other files required for formal verification, such as the synthetic input data of the target module.
In one implementation, the start command of the time sequence analysis tool may further include parameter information of the time sequence analysis tool. The start command of the formal verification tool may also include parameter information of the formal verification tool.
It should be noted that the static timing analysis in this embodiment refers to a workflow for calculating and predicting the timing of the digital circuit. Formal verification in this embodiment refers to the process of mathematically proving or verifying whether an implementation of a circuit does implement the functionality described by the circuit design. The process library in this embodiment is a file provided by the chip manufacturer to indicate the various units in the integrated circuit fabrication process. The constraint file in this embodiment can constrain the timing, area, and power consumption of the circuit, which is a design pulse and determines whether the chip meets the specification of the design requirement.
It should be noted that there is no timing relationship between step 105 and step 106.
Step 107: and acquiring a second report file obtained by running a time sequence analysis tool on the second target server and performing time sequence analysis on the netlist file.
In this embodiment, the logic synthesis apparatus may determine whether the second target server is completely operated at a preset frequency. And when the second target server is determined to finish running, obtaining a running time sequence analysis tool of the second target server, and carrying out time sequence analysis on the netlist file to obtain a second report file.
For example, the logic synthesis apparatus may read the work log of the second target server at a preset frequency. When it is determined that a second report file indicating a target module has been generated in the work log, it is determined that the second target server operation is complete.
Optionally, the second report file in this embodiment includes result information of the time sequence analysis.
Step 108: and obtaining a third report file obtained by running a formal verification tool on the third target server and performing formal verification on the netlist file.
In this embodiment, the logic synthesis apparatus may determine whether the third target server is completely operated at a preset frequency. And when the third target server is determined to finish running, obtaining a running form verification tool of the third target server, and performing form verification on the netlist file to obtain a third report file.
For example, the logic synthesis apparatus may read the work log of the third target server at a preset frequency. When it is determined that a third report file indicating a target module in the work log has been generated, it is determined that a third target server operation is completed.
Optionally, the third report file in this embodiment includes result information of formal verification.
Step 109: and when the second report file and the third report file are determined to meet the result judgment information in the target configuration file, delivering the netlist file.
The target configuration file in this embodiment further includes result determination information. The result judgment information is used for indicating the required form of the report file after the time sequence analysis and the form verification, namely, the standard which needs to be met by the project, such as the requirement of time sequence information, the requirement of area information, the result of form verification and other conditions. The specific report analysis process may be: and (4) according to the result of the target configuration file, judging whether the filtering information in the information filters the ignorable warning and error in the second report file and the third report file, and then judging according to the filtered information and obtaining the conclusion of the success or failure of the time sequence analysis and form verification process. And when the second report file and the third report file are determined to meet the result judgment information in the target configuration file, the realization of the netlist file function of the target module is correct, and the netlist file can be delivered to the back end. Optionally, at least one of the first report file, the second report file and the third report file may be delivered to the backend according to actual requirements.
It should be noted that there is no timing relationship between step 107 and step 108.
Further, after step 107 and step 108, the logic synthesis method provided in this embodiment further includes the following steps: displaying at least one of the netlist file, the first report file, the second report file and the third report file; and/or at least one of the netlist file, the first report file, the second report file and the third report file is sent to a mail address in a preset mail list. The method for visually displaying at least one of the netlist file, the first report file, the second report file and the third report file can facilitate the integrated circuit designer to analyze the output files, and improve the efficiency of integrated circuit design.
The logic synthesis method provided by this embodiment further includes: sending a starting command of the time sequence analysis tool to a second target server, sending a starting command of the form verification tool to a third target server, obtaining a second target server running time sequence analysis tool, obtaining a second report file after time sequence analysis is carried out on the netlist file, obtaining a third target server running form verification tool, obtaining a third report file after form verification is carried out on the netlist file, and delivering the netlist file when the second report file and the third report file are determined to meet result judgment information in the target configuration file. The logic synthesis method can automatically start the sequential analysis tool and the form verification tool of the next step after logic synthesis on one hand, save the starting time of each tool, and can automatically acquire a second report file formed after the sequential analysis tool is operated and a third report file formed after the form verification tool is operated, so that the steps of the current logic synthesis environment are seamlessly connected, manual intervention is not needed in the input and output processing process, the efficiency of integrated circuit design is improved, the labor cost is saved, on the other hand, the second report file and the third report file can be automatically verified according to the target configuration file, whether the next step delivery process can be carried out or not is automatically determined, whether the delivery can be carried out or not is not manually determined, and the efficiency of integrated circuit design is further improved, the accuracy, the high efficiency and the standardization of delivery are ensured.
Fig. 3 is a schematic flow chart of a logic synthesis method according to yet another embodiment. This embodiment will explain in detail the steps before step 102, the steps after step 102, and the steps before step 104 on the basis of the embodiment shown in fig. 1 and fig. 2 and various alternatives. As shown in fig. 3, the logic synthesis method provided in this embodiment includes the following steps:
step 301: and acquiring the comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file.
Step 301 is similar to the implementation process and technical principle of step 101, and is not described herein again.
Step 302: and determining a server of which the corresponding load meets a first preset condition in the server cluster as a first target server.
The first preset condition in this embodiment may be a screening condition that the load is smaller than a preset threshold. The load in this embodiment can be measured by the utilization rate of the server and parameters such as unused memory.
Optionally, the specific implementation process of step 302 may be: determining a server with a normal state in a server cluster; sequencing the servers in a normal state according to the sequence of the utilization rates from small to large, and determining the servers with the utilization rates arranged in the first preset number; sequencing the servers with the utilization rates ranked in the first preset number according to the sequence of the unused memories from small to large, and determining the servers with the unused memories ranked in the first preset number; and determining the servers with the second preset number before the unused internal memory as the first target server. The first target server determined in the above mode can ensure that the logic synthesis tool can be operated efficiently, and the logic synthesis efficiency is improved.
Step 303: and sending the integrated input data of the target module and the starting command of the logic integrated tool to the first target server.
Step 303 is similar to the implementation process and technical principle of step 102, and is not described herein again.
In one implementation, the number of target modules is multiple. The implementation process of step 302 specifically includes: determining a plurality of servers with corresponding loads meeting a first preset condition in a server cluster as a plurality of first target servers, and determining a mapping relation between the first target servers and a target module. Based on this implementation, the implementation process of step 302 specifically includes: and sending the integrated input data of the corresponding target module and the starting command of the logic integrated tool to the first target server in batch. The implementation mode can realize the logic synthesis of a plurality of target modules in batch under the condition that the number of the target modules is multiple, and improves the efficiency of the logic synthesis.
Step 304: and inquiring the working state of the first target server at a preset frequency.
Step 305: if the working state of the first target server is determined to be the running state, the step 307 is determined to be executed.
Step 306: and if the working state of the first target server is determined to be the non-running state, returning to execute the step 302.
In steps 304 to 306, the logic synthesis apparatus may query the operating state of the first target server at a preset frequency. When the operating state of the first target server is determined to be the running state, the step of step 307 is determined to be executed. When the working state of the first target server is determined to be the non-running state, it is required to return to the step of executing the step 302 to re-determine the first target server, which indicates that the start command of the logic synthesis tool is failed to be submitted to the first target server.
The implementation manner of step 304 to step 306 realizes monitoring of the working state of the first target server, and improves the success rate of logic synthesis.
Step 307: and acquiring a netlist file and a first report file after the first target server operates a logic synthesis tool and performs logic synthesis on the synthesis input data of the target module.
Step 307 is similar to the implementation process and technical principle of step 103, and is not described herein again.
Step 308: and when the first report file is determined to meet the comprehensive result tracking information in the target configuration file, determining a server of which the corresponding load meets a second preset condition in the server cluster as a second target server, and determining a server of which the corresponding load meets a third preset condition in the server cluster as a third target server.
Similar to step 302, in step 308, when it is determined that the first report file satisfies the integrated result tracking information in the target configuration file, determining the second target server and the third target server may be implemented to ensure that the timing analysis tool and the format verification tool are efficiently operated, thereby improving the efficiency of the timing analysis and the format verification.
The specific determination process is similar to the process of determining the first target server in step 302, and is not described here again.
Step 309: and sending the netlist file and a start command of the timing analysis tool to a second target server, and sending the netlist file, the synthetic input data and a start command of the form verification tool to a third target server.
Step 309 is similar to the implementation process and technical principle of step 104, step 105 and step 106, and is not described here again.
Step 310: and acquiring a second report file obtained by running a time sequence analysis tool on the second target server and performing time sequence analysis on the netlist file.
In one implementation, prior to step 310, the operating status of the second target server may be queried at a preset frequency. If the working state of the second target server is determined to be the running state, the step of step 310 is determined to be executed. And if the working state of the second target server is determined to be the non-running state, returning to execute the step 308.
Step 311: and obtaining a third report file obtained by running a formal verification tool on the third target server and performing formal verification on the netlist file.
In one implementation, before step 311, the working state of the third target server may be queried at a preset frequency. And if the working state of the third target server is determined to be the running state, determining to execute the step 311. And if the working state of the third target server is determined to be the non-running state, returning to execute the step 308.
Step 312: and when the second report file and the third report file are determined to meet the result judgment information in the target configuration file, delivering the netlist file.
Step 312 is similar to the implementation process and technical principle of step 109, and is not described herein again.
The logic synthesis method provided by this embodiment establishes an effective synchronous communication mechanism in each stage by introducing a full-flow target configuration file, so that each step can be seamlessly connected. The operation process is automatically realized through reasonable process control, the tool process is monitored and submitted through a server traversing method, and the output result of each tool is monitored in real time; all tools are automatically connected, reports are analyzed and processed, full-process automatic processing and delivery are achieved, all steps are accurate and efficient, and design efficiency is greatly improved due to standardized operation.
According to the logic synthesis method provided by the embodiment, on one hand, the first target server, the second target server and the third target server which meet the conditions can be determined, and the running efficiency of each tool is improved, so that the logic synthesis efficiency is improved, on the other hand, the working state of each server can be monitored, and the logic synthesis success rate is improved.
Fig. 4 is a schematic diagram of a file structure of the logic synthesis platform according to an embodiment. The logic synthesis platform provided by this embodiment may be used to implement the logic synthesis method provided by the embodiments shown in fig. 1 to fig. 3. As shown in fig. 4, the logic synthesis platform is implemented by a script. It includes the following script: the system comprises an automation logic comprehensive platform main script, an automation logic comprehensive platform initialization script, a platform sub-script folder and a platform log folder.
The main script of the automation logic comprehensive platform analyzes the initialization script of the automation logic comprehensive platform and controls various sub scripts.
The platform log folder stores four types of log files generated in the running process of the platform. The integrated version log contains various files that run the integrated process. The platform result upload log comprises a log generated during the data delivery process. The web billboard upload log comprises files generated during the process of uploading the content of the required project to the web page. The mail transmission log refers to a file generated during the process of transmitting the project mail.
The platform sub-script folder contains the following eight scripts.
(1) And analyzing the version information script, and analyzing the version information file provided by the front end to obtain version information of the RTL circuit code and information of the module needing to be integrated, such as the name of the module.
(2) And moving the constraint file script, updating the latest constraint file, and moving the constraint file to the platform.
(3) And the code acquisition script updates the code file and generates a code file required by the platform according to the version information of the RTL circuit code.
(4) The one-key parallel execution integrated flow script is a core script of the platform, and has the following functions:
1. multiple modules are launched in parallel to implement one-key operation of the logic synthesis tool, the timing analysis tool, and the formal verification tool.
2. Before running the tool, sorting the servers, namely firstly selecting the servers with normal server states, then sorting the selected servers according to the utilization rate of the servers, and finally re-sorting the servers with the same utilization rate according to an unused memory; when the tool is operated, tool processes are submitted according to the sequence of the server, whether the submitted processes are successful or not is monitored, if the submission is failed, the failed processes are closed, and the server is traversed to continuously submit the corresponding processes until the submission processes are successful.
3. The parallel operation of each tool is realized in a thread mode, a new terminal cannot be started, and terminal resources are not occupied. The terminal in this embodiment refers to a terminal of a linux system.
4. And controlling the versions of all tools, and selecting a mode for the logic synthesis tool.
5. The tool enabling signal is used for selecting the tool to be used, so that the occupation of server resources is reduced.
(5) And the comprehensive result analysis script reduces the manual analysis of the comprehensive result. The log or report is analyzed by double information filtering, general filtering information and special module filtering information. If all the information is filtered, the result is correct; if there is remaining information, manual confirmation is required.
(6) And the comprehensive data delivery script delivers various comprehensively generated data files.
(7) The web billboard data generates scripts, generates data files required by the web page, and uploads the data files.
(6) And generating a sending script for the mail data, generating a data file required by the mail, and uploading.
The logic comprehensive platform automatically realizes the operation process through reasonable process control, monitors and submits the tool process through a server traversing method, and monitors the output result of each tool in real time; all tools are automatically connected, reports are analyzed and processed, full-process automatic processing and delivery are achieved, all steps are accurate and efficient, and design efficiency is greatly improved due to standardized operation.
Fig. 5 is a schematic structural diagram of a logic synthesis apparatus according to an embodiment. As shown in fig. 5, the logic synthesis apparatus provided in this embodiment includes the following modules: a first obtaining module 51, a sending module 52 and a second obtaining module 53.
A first obtaining module 51 configured to obtain the comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file.
A sending module 52 configured to send the synthetic input data of the target module and the start command of the logical synthesis tool to the first target server.
Optionally, the start command of the logical synthesis tool includes parameter information of the logical synthesis tool.
The second obtaining module 53 is configured to obtain a netlist file and a first report file obtained by the first target server running a logic synthesis tool and performing logic synthesis on the synthesis input data of the target module.
The sending module 52 is further configured to send the netlist file to the second target server, and send the netlist file and the synthesis input data to the third target server when it is determined that the first report file satisfies the synthesis result trace information in the target configuration file.
Optionally, the integrated result tracking information includes: general integrated result tracking information and integrated result tracking information specific to the target module.
Optionally, the sending module 52 may be further configured to send a start command of the timing analysis tool to the second target server.
Optionally, the sending module 52 may be further configured to send a start command of the formal verification tool to a third target server.
Optionally, the apparatus further comprises: the device comprises a third acquisition module, a fourth acquisition module and a delivery module.
And the third acquisition module is configured to acquire a second report file obtained by running a timing analysis tool on the second target server and performing timing analysis on the netlist file.
And the fourth acquisition module is configured to acquire a third report file obtained by running a formal verification tool on the third target server and performing formal verification on the netlist file.
And the delivery module is configured to deliver the netlist file when the second report file and the third report file are determined to meet the result judgment information in the target configuration file.
Optionally, the apparatus further comprises a first determining module.
In an embodiment, the first determining module is configured to determine, as the first target server, a server in the server cluster whose corresponding load meets a first preset condition.
Optionally, the first determining module is specifically configured to: determining a server with a normal state in a server cluster; sequencing the servers in a normal state according to the sequence of the utilization rates from small to large, and determining the servers with the utilization rates arranged in the first preset number; sequencing the servers with the utilization rates ranked in the first preset number according to the sequence of the unused memories from small to large, and determining the servers with the unused memories ranked in the first preset number; and determining the servers with the second preset number before the unused internal memory as the first target server.
In an embodiment, the first determining module is further configured to determine, as the second target server, a server in the server cluster whose corresponding load meets a second preset condition. The first determining module is further configured to determine, as a third target server, a server in the server cluster whose corresponding load meets a third preset condition.
In one embodiment, the apparatus further comprises: the device comprises a query module and a second determination module.
And the query module is configured to query the working state of the first target server at a preset frequency.
The second determination module is configured to determine to execute the steps of acquiring a first target server operation logic synthesis tool and performing logic synthesis on the synthesis input data of the target module to obtain a netlist file and a first report file when the first target server is determined to be operated and completed if the working state of the first target server is determined to be the operating state; and if the working state of the first target server is determined to be the non-running state, returning to execute the step of determining the server with the corresponding load meeting the first preset condition in the server cluster as the first target server.
Optionally, the number of target modules is plural. The first determining module is specifically configured to: determining a plurality of servers with corresponding loads meeting a first preset condition in a server cluster as a plurality of first target servers, and determining a mapping relation between the first target servers and a target module. Based on the implementation, the sending module is specifically configured to: and sending the integrated input data of the corresponding target module and the starting command of the logic integrated tool to the first target server in batch.
In one embodiment, the apparatus further comprises: a display module and/or a mail sending module.
A display module configured to display at least one of the netlist file, the first report file, the second report file, and the third report file.
And the mail sending module is configured to send at least one of the netlist file, the first report file, the second report file and the third report file to a mail address in a preset mail list.
The logic synthesis apparatus provided in this embodiment is used to execute the logic synthesis method in any of the above embodiments, and the implementation principle and technical effect of the logic synthesis apparatus provided in this embodiment are similar, and are not described herein again.
Fig. 6 is a schematic structural diagram of a logic synthesis apparatus according to an embodiment. As shown in fig. 6, the logic synthesis apparatus includes a processor 61 and a memory 62; the number of the processors 61 in the logic synthesis device may be one or more, and one processor 61 is taken as an example in fig. 6; a processor 61 and a memory 62 in the logic synthesis apparatus; the connection may be via a bus or other means, such as via a bus as illustrated in FIG. 6.
The memory 62 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the logic synthesis method in the embodiment of the present application (for example, the first obtaining module 51, the sending module 52, and the second obtaining module 53 in the logic synthesis apparatus). The processor 61 logically synthesizes various functional applications of the apparatus and logic by running software programs, instructions, and modules stored in the memory 62, that is, implements the above-described logic synthesizing method.
The memory 62 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the logic synthesis apparatus, and the like. Further, the memory 62 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device.
Embodiments of the present application also provide a storage medium containing computer-executable instructions that, when executed by a computer processor, perform a method of logic synthesis, the method comprising:
acquiring comprehensive input data of a target module according to the module comprehensive configuration information in the target configuration file;
sending the integrated input data of the target module and a starting command of a logic integrated tool to a first target server;
acquiring a netlist file and a first report file after the first target server operates the logic synthesis tool and performs logic synthesis on the synthesis input data of the target module;
and when the first report file is determined to meet the comprehensive result tracking information in the target configuration file, sending the netlist file to a second target server, and sending the netlist file and the comprehensive input data to a third target server.
Of course, the present application provides a storage medium containing computer-executable instructions, which are not limited to the method operations described above, but can also perform related operations in the logic synthesis method provided in any embodiment of the present application.
The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
One of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not intended to limit the scope of the embodiments of the invention. Any modifications, equivalents and improvements that may occur to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention are intended to be within the scope of the claims of the embodiments of the present invention.
Claims (12)
1. A method of logic synthesis, the method comprising:
acquiring comprehensive input data of a target module according to the module comprehensive configuration information in the target configuration file;
sending the integrated input data of the target module and a starting command of a logic integrated tool to a first target server;
acquiring a netlist file and a first report file after the first target server operates the logic synthesis tool and performs logic synthesis on the synthesis input data of the target module;
and when the first report file is determined to meet the comprehensive result tracking information in the target configuration file, sending the netlist file to a second target server, and sending the netlist file and the comprehensive input data to a third target server.
2. The method of claim 1, further comprising:
sending a starting command of a time sequence analysis tool to the second target server;
sending a start command of a formal verification tool to the third target server;
acquiring a second report file obtained by the second target server running the timing analysis tool and performing timing analysis on the netlist file;
obtaining a third report file obtained by the third target server running the formal verification tool and performing formal verification on the netlist file;
and when the second report file and the third report file are determined to meet the result judgment information in the target configuration file, delivering the netlist file.
3. The method of claim 1, wherein prior to sending the consolidated input data for the target module and the start command for the logical consolidation tool to the first target server, the method further comprises:
and determining a server with a corresponding load meeting a first preset condition in the server cluster as the first target server.
4. The method according to claim 3, wherein the determining, as the first target server, a server in the server cluster whose corresponding load meets a first preset condition includes:
determining a server with a normal state in the server cluster;
sequencing the servers in the normal state according to the sequence of the utilization rates from small to large, and determining the servers with the utilization rates arranged in the first preset number;
sequencing the servers with the utilization rates ranked in the first preset number according to the sequence of the unused memories from small to large, and determining the servers with the unused memories ranked in the first preset number;
and determining the unused memory as the first target server according to a second preset number of servers before the unused memory.
5. The method of claim 3 or 4, wherein after sending the synthetic input data of the target module and the start command of the logical synthesis tool to the first target server, the method further comprises:
inquiring the working state of the first target server at a preset frequency;
if the working state of the first target server is determined to be the running state, determining to execute a step of obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool and performing logic synthesis on the synthesis input data of the target module when the first target server is determined to be completely run;
and if the working state of the first target server is determined to be the non-running state, returning to execute the step of determining the server with the corresponding load meeting the first preset condition in the server cluster as the first target server.
6. The method of claim 3 or 4, wherein the number of target modules is plural;
the determining, as the first target server, a server in the server cluster whose corresponding load meets a first preset condition includes:
determining a plurality of servers of which the corresponding loads meet a first preset condition in the server cluster as a plurality of first target servers, and determining a mapping relation between the first target servers and a target module;
the sending of the integrated input data of the target module and the start command of the logic integration tool to the first target server includes:
and sending the integrated input data of the corresponding target module and the starting command of the logic integrated tool to the first target server in batch.
7. The method of any of claims 2 to 4, wherein the obtaining the third target server runs the formal verification tool, and after performing the formal verification on the netlist file to obtain a formal verified third report file, the method further comprises:
displaying at least one of the netlist file, the first report file, the second report file, and the third report file; and/or the presence of a gas in the gas,
and sending at least one of the netlist file, the first report file, the second report file and the third report file to a mail address in a preset mail list.
8. The method of any of claims 1 to 4, wherein prior to sending the netlist file to a second target server, sending the netlist file and the synthesis input data to a third target server, the method further comprises:
determining a server with a corresponding load meeting a second preset condition in the server cluster as the second target server;
and determining a server with a corresponding load meeting a third preset condition in the server cluster as the third target server.
9. Method according to any of claims 1 to 4, characterized in that the start command of the logical synthesis tool comprises parameter information of the logical synthesis tool.
10. The method of any of claims 1 to 4, wherein the integrated result tracking information comprises: general integrated result tracking information and integrated result tracking information specific to the target module.
11. A logic synthesis device, characterized in that the device comprises a memory, a processor, a program stored on the memory and executable on the processor, and a data bus for implementing a connection communication between the processor and the memory, the program, when executed by the processor, implementing the steps of the logic synthesis method according to any one of claims 1 to 10.
12. A storage medium for computer readable storage, wherein the storage medium stores one or more programs which are executable by one or more processors to implement the steps of the logic synthesis method of any one of claims 1 to 10.
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| PCT/CN2021/113292 WO2022042397A1 (en) | 2020-08-25 | 2021-08-18 | Method and device for logic synthesis, and storage medium |
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| CN116542191B (en) * | 2023-07-06 | 2023-12-05 | 奇捷科技(深圳)有限公司 | Logic correction method, device, equipment and storage medium |
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| CN105718367A (en) * | 2015-10-28 | 2016-06-29 | 北京圣涛平试验工程技术研究院有限责任公司 | Method and system for automatically evaluating quality of IP core |
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| CN116542190B (en) * | 2023-06-02 | 2023-09-01 | 英诺达(成都)电子科技有限公司 | User design comprehensive method, device, equipment, medium and product |
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