CN113595511A - Open loop amplifier circuit - Google Patents
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Abstract
The invention discloses an open-loop amplifier circuit, which comprises a bias circuit, an amplifying circuit and a compensating circuit; the bias circuit generates bias current to supply to the amplifying circuit; the amplifying circuit comprises an input port and an output port, and a signal input from the input port is amplified by the amplifying circuit and output from the output port; the compensation circuit compensates the output of the amplification circuit. According to the invention, no additional clock signal is introduced, only one group of amplifiers is used, and the static compensation mode is adopted, so that the sensing signal can be fixedly amplified, the offset voltage can be eliminated, the clock signal is prevented from being interfered, a higher signal-to-noise ratio can be obtained, and higher measurement accuracy can be obtained.
Description
Technical Field
The invention relates to the field of signal amplification of analog sensors, in particular to an open-loop amplifier circuit for amplifying weak sensor electrical signals.
Background
Analog signals are signals that are continuous in time and in value, and information expressed by continuously changing physical quantities, such as temperature, humidity, pressure, length, current, voltage, etc., and are often referred to as continuous signals, which can have an infinite number of different values over a certain time. While a digital signal refers to a signal that is discrete and discontinuous in value.
Various physical quantities in daily life, such as sound, pressure, flow rate, rotation speed, humidity, etc., are analog signals. The digital signal is formed by sampling, quantizing and encoding on the basis of the analog signal. The quantization is to represent the sampled values at each time by a binary code system, and the coding is to arrange the binary numbers generated by quantization together to form a sequential pulse sequence. These analog signals need to be first collected by various sensors and then amplified and converted into digital signals for processing by the system.
Generally, analog sensing signals directly acquired are weak and have a certain offset voltage; in the traditional method, an instrument amplifier and a chopper circuit are adopted to counteract offset voltage; the offset voltage, also called input offset voltage, refers to the difference between the dc voltages applied to the two input terminals in the differential amplifier or differential input operational amplifier in order to obtain a constant zero voltage output at the output terminal. This parameter characterizes the degree of matching of the present stage of the differential amplifier. When equal input voltages are applied to the two input terminals of the differential amplifier, the differential output voltage is referred to as an output offset voltage. If the inputs of the op-amp are shorted together and grounded (as shown in fig. 1), some dc voltage is present at the output. This voltage is called the "output offset voltage" (output offset voltage), which is the differential input voltage that exists between the two ports in the absence of any external input. In other words, it can be considered as an input voltage applied between the input ports forcing the output voltage to zero. Shown in fig. 1 is a conventional amplifier circuit that cancels the offset voltage in the manner of an instrumentation amplifier + chopper. Differential input signals VIP and VIN enter an input circuit and then pass through an operational amplifier to an output circuit to form output differential signals VOP and VON, wherein the input circuit and the output circuit respectively need to introduce clock signals CLK1 and CLK2, the clock signals can bring interference, and the signal-to-noise ratio of the signals can be reduced.
Disclosure of Invention
The invention aims to provide an open-loop amplifier circuit which is used for amplifying a generated weak sensor electrical signal.
In order to solve the above problems, the open-loop amplifier circuit according to the present invention amplifies a weak electrical signal of a sensor or other circuits, and includes a bias circuit, an amplifying circuit, and a compensating circuit; the bias circuit generates a bias current to supply to the amplifying circuit.
The amplifying circuit comprises an input port and an output port, and signals input from the input port are amplified by the amplifying circuit and output from the output port.
The compensation circuit compensates the output of the amplifying circuit to prevent the drift of the output port.
In a further improvement, the bias circuit is a current source, and includes a first PMOS, a fourth PMOS, a fifth PMOS, a third NMOS, a fourth NMOS, a seventh NMOS, and a second resistor.
The grid electrodes of the first PMOS and the fifth PMOS are in short circuit to form a first node which is connected with the amplifying circuit; the source electrodes of the first PMOS and the fifth PMOS are connected with a power supply, and the grid electrode of the first PMOS is in short circuit with the drain electrode.
And the source electrode of the fourth PMOS is connected with the power supply, and the grid electrode of the fourth PMOS is in short circuit with the drain electrode to form a second node which is connected with the amplifying circuit.
And the drain electrode of the fourth PMOS is connected with the drain electrode of the seventh NMOS, and the source electrode of the seventh NMOS is grounded.
And the grid electrode of the fourth NMOS is connected with the grid electrode of the seventh NMOS and the grid electrode of the third NMOS to form a third node which is connected with the amplifying circuit.
The source electrode of the fourth NMOS is grounded, and the source electrode of the third NMOS is grounded through a second resistor.
And the grid electrode and the drain electrode of the fourth NMOS are in short circuit and connected to the drain electrode of the fifth PMOS.
And the drain electrode of the third NMOS is connected with the drain electrode of the first PMOS.
In a further improvement, the output current of the bias circuit is determined by a second resistor, namely a current I flowing through a third NMOS tube1Comprises the following steps:
wherein L isN4Is the gate length of the fourth NMOS, WN4The gate width of the fourth NMOS, and beta is the gain coefficient of the fourth NMOS; r2Is a second resistanceThe value is obtained.
The current flowing through the third NMOS tube is equal to the current flowing through the fourth NMOS tube.
In a further improvement, the input port and the output port of the amplifying circuit are both differential signal ports.
In a further improvement, the amplifying circuit comprises a first NMOS, a second NMOS, a fifth NMOS, a sixth NMOS, an eighth NMOS, a second PMOS, a third PMOS, a sixth PMOS and a seventh PMOS; the circuit also comprises a first resistor and a third resistor;
the grid electrode of the second PMOS is connected with the grid electrode of the third PMOS and then is connected to the first node of the bias circuit;
the source electrode of the second PMOS and the source electrode of the third PMOS are connected with a power supply;
the grid electrode of the sixth PMOS is connected with the grid electrode of the seventh PMOS and then is connected to the second node of the bias circuit;
the grid electrodes of the fifth NMOS and the sixth NMOS are in short circuit, the source electrode of the fifth NMOS and the source electrode of the sixth NMOS are grounded, the drain electrode of the fifth NMOS is connected with the drain electrode of the sixth PMOS, and the drain electrode of the sixth NMOS is connected with the drain electrode of the seventh PMOS;
two ends of the first resistor are respectively connected with the drain electrode and the grid electrode of the sixth NMOS, and two ends of the third resistor are respectively connected with the drain electrode and the grid electrode of the fifth NMOS; the drain electrode of the fifth NMOS and the drain electrode of the sixth NMOS form a differential output port of the amplifying circuit;
the drain electrode of the first NMOS is connected with the drain electrode of the third PMOS, and the drain electrode of the eighth NMOS is connected with the drain electrode of the second PMOS;
the grid electrode of the first NMOS and the grid electrode of the eighth NMOS form a differential input port of the amplifying circuit;
the source electrode of the first NMOS is connected with the source electrode of the eighth NMOS and then connected with the drain electrode of the second NMOS; the source electrode of the second NMOS is grounded;
and the grid electrode of the second NMOS is connected with a third node of the biasing circuit.
In a further improvement, the voltage gain a of the amplifying circuit is related to the width-to-length ratio of the gate of the second resistor, the third resistor and the third, fourth and eighth NMOS transistors:
I2＝KI1；
wherein, the I2The current flowing through the second NMOS tube is the mirror image current of the fourth NMOS tube,
is the gate width-to-length ratio of the third NMOS,
is the gate width-to-length ratio of the eighth NMOS,
the gate width-to-length ratio of the fourth NMOS.
The further improvement is that the voltage gain A of the amplifying circuit is determined by the characteristic parameters of the second resistor, the third NMOS tube, the fourth NMOS tube and the eighth NMOS tube, and has a compensation calibration function, so that the drift of the amplifier can be counteracted, and the offset voltage of the input signal can be counteracted.
In a further improvement, the compensation circuit is a current mode DAC; the reference current input end of the amplifier is connected with a third node of the bias circuit, the output end of the amplifier is respectively connected with a differential output port of the amplifier circuit, and the grounding port of the amplifier is connected with the ground;
the current mode DAC compensates the amplifier circuit to ensure that VOP-VON is 0 when VIN-VIP is 0.
In a further improvement, in the bias circuit, a third NMOS and a fourth NMOS form a static operating point circuit, and the size ratio of the third NMOS to the fourth NMOS is 4: 1.
In a further improvement, the first resistor and the third resistor have the same resistance.
In a further improvement, the current mode DAC circuit is a current mode DAC with N +1 bits.
The open-loop amplifier circuit provided by the invention does not introduce extra clock signals, only uses one group of amplifiers, adopts a static compensation mode, can fixedly amplify sensing signals, can eliminate offset voltage, is free from the interference of clock signals, can obtain higher signal-to-noise ratio, and obtains higher measurement accuracy.
Drawings
Fig. 1 is a schematic diagram of a conventional amplifier circuit.
Fig. 2 is a schematic diagram of the open loop amplifier circuit of the present invention.
Fig. 3 is a schematic diagram of the current-mode DAC in the circuit diagram shown in fig. 2.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The open-loop amplifier circuit amplifies weak electric signals of a sensor or other circuits, and comprises a bias circuit, an amplifying circuit and a compensating circuit; the bias circuit generates a bias current to supply to the amplification circuit as shown in fig. 2.
The amplifying circuit comprises differential input ports VIP and VIN and differential output ports VOP and VON, signals input from the input ports are amplified through the amplifying circuit and output through the output ports;
the compensation circuit compensates the output of the amplifying circuit to prevent the drift of the output port.
For convenience of description, referring to fig. 2, in the present invention, the first to seventh PMOS correspond to P1 to P7, the first to eighth NMOS correspond to N1 to N8, and the first to third resistors correspond to R1 to R3, respectively.
Note that the above element designations are for fig. 2 and 3 only, and not for fig. 1.
A bias circuit:
the bias circuit is a current source, and comprises P1, P4, P5, N3, N4, N7, and a second resistor R2.
The P1 and the P5 are in gate short circuit to form a first node VBP1, and the first node VBP is connected with the amplifying circuit of the secondary side; the sources of P1 and P5 are connected with the power VCC, and the grid of P1 is short-circuited with the drain.
The source electrode of the P4 is connected with a power supply VCC, the grid electrode of the fourth PMOS is in short circuit with the drain electrode to form a second node VBP2, and the second node VBP2 is connected with the secondary amplifying circuit.
The drain of the P4 is connected with the drain of the N7, and the source of the N7 is grounded.
The gate of the N4 is connected to the gate of the N7 and the gate of the N3 to form a third node VBN, which is connected to the secondary amplifying circuit.
The source of the N4 is grounded, and the source of the N3 is grounded through a second resistor R2.
The gate and drain of the N4 are shorted and connected to the drain of the P5.
The drain of the N3 is connected with the drain of the P1.
The transistors N3 and N4 form a static operating point circuit, and the size ratio of N3 to N4 in the embodiment of the invention is 4: 1.
An amplifying circuit:
the amplifying circuit comprises NMOS transistors N1, N2, N5, N6 and N8, and PMOS transistors P2, P3, P6 and P7; also includes a first resistor R1 and a third resistor R3.
The gate of P2 is connected to the gate of P3 and to the first node of the bias circuit VBP 1.
The source of the P2 and the source of the P3 are connected with a power supply VCC.
The gate of P6 is connected to the gate of P7 and to the second node of the bias circuit VBP 2.
The N5 is in short circuit with the gate of N6, the source of N5 and the source of N6 are grounded, the drain of N5 is connected with the drain of P6, and the drain of N6 is connected with the drain of P7.
Two ends of the first resistor R1 are respectively connected with the drain and the gate of the N6, and two ends of the third resistor R3 are respectively connected with the drain and the gate of the N5; the drain of the N5 and the drain of the N6 form the differential output ports VON, VOP of the amplifying circuit, respectively. The first resistor R1 and the third resistor R3 have the same resistance.
The drain of the N1 is connected with the drain of the P3, and the drain of the N8 is connected with the drain of the P2.
The gate of N1 and the gate of N8 form the differential input ports VIN, VIP of the amplification circuit, respectively.
The source of the N1 is connected with the source of the N8 and then connected with the drain of the N2; the source of the N2 is grounded.
The gate of the N2 is coupled to the third node VBN of the bias circuit.
The output current of the bias circuit is determined by a second resistor R2, i.e. the current I flowing through the N3 tube1Comprises the following steps:
wherein L isN4Is the gate length of the fourth NMOS, WN4The gate width of the fourth NMOS, and beta is the gain coefficient of the fourth NMOS; r2Is the second resistance value.
The N3 tube and the N4 tube form a micro current source, and the current flowing through the N3 tube is equal to the current flowing through the N4 tube.
The voltage gain A of the amplifying circuit is related to the gate width-length ratio of the second resistor R2, the third resistor R3, the N3, the N4 and the N8:
I2＝KI1；
wherein, the I2The current flowing through the N2 tube, which is a mirror current of N4,
is the gate width to length ratio of N3,
is the gate width to length ratio of N8,
is the gate width to length ratio of N4.
The voltage gain A of the amplifying circuit is determined by the characteristic parameters of the second resistor R2, the third resistor R3, the N3, the N4 and the N8, and has a compensation and calibration function, so that the drift of the amplifier can be counteracted, and the offset voltage of an input signal can be counteracted.
The compensation circuit:
the compensation circuit is a current-mode DAC with N +1 bits, and as shown in fig. 3, includes an array formed by a plurality of transistors connected in parallel, a reference current input terminal of the compensation circuit is connected to a third node VBN of the bias circuit, output terminals of the compensation circuit are respectively connected to differential output ports VON and VOP of the amplification circuit, and a ground port is connected to ground.
The current mode DAC compensates the amplifier circuit to ensure that VOP-VON is 0 when VIN-VIP is 0.
The scheme adopts a static compensation mode, not only can the amplified sensing electrical signal be fixed, but also the offset voltage can be eliminated, and the drift of the amplifying circuit can be eliminated by a current type DAC. Because the clock signal is cancelled, the interference of the clock signal can be avoided, a high signal-to-noise ratio can be obtained, and higher measurement accuracy can be obtained. Meanwhile, only one amplifier is used in the whole amplifying circuit, and a sample-hold filter circuit of the Chopper circuit is removed, so that power consumption is saved, and the circuit area is reduced.
While there have been shown and described what are at present considered to be the fundamental principles of the invention and its essential features and advantages, it will be understood by those skilled in the art that the invention is not limited by the embodiments described above, which are merely illustrative of the principles of the invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (12)
1. An open loop amplifier circuit, characterized by: the open-loop amplifier circuit amplifies weak electric signals of a sensor or other circuits and comprises a bias circuit, an amplifying circuit and a compensating circuit; the bias circuit generates bias current to supply to the amplifying circuit;
the amplifying circuit comprises an input port and an output port, and a signal input from the input port is amplified by the amplifying circuit and output from the output port;
the compensation circuit compensates the output of the amplifying circuit to prevent the drift of the output port.
2. The open loop amplifier circuit of claim 1, wherein: the bias circuit is a current source.
3. The open loop amplifier circuit of claim 2, wherein: the current source comprises a first PMOS, a fourth PMOS, a fifth PMOS, a third NMOS, a fourth NMOS, a seventh NMOS and a second resistor;
the grid electrodes of the first PMOS and the fifth PMOS are in short circuit to form a first node which is connected with the amplifying circuit; the source electrodes of the first PMOS and the fifth PMOS are connected with a power supply, and the grid electrode of the first PMOS is in short circuit with the drain electrode;
the source electrode of the fourth PMOS is connected with the power supply, and the grid electrode of the fourth PMOS is in short circuit with the drain electrode to form a second node which is connected with the amplifying circuit;
the drain electrode of the fourth PMOS is connected with the drain electrode of the seventh NMOS, and the source electrode of the seventh NMOS is grounded;
the grid electrode of the fourth NMOS is connected with the grid electrode of the seventh NMOS and the grid electrode of the third NMOS to form a third node which is connected with the amplifying circuit;
the source electrode of the fourth NMOS is grounded, and the source electrode of the third NMOS is grounded through a second resistor;
the grid electrode and the drain electrode of the fourth NMOS are in short circuit and connected to the drain electrode of the fifth PMOS;
and the drain electrode of the third NMOS is connected with the drain electrode of the first PMOS.
4. The open loop amplifier circuit of claim 3, wherein: the output current of the bias circuit is determined by a second resistor, namely the current I flowing through a third NMOS tube1Comprises the following steps:
wherein L isN4Is the gate length of the fourth NMOS, WN4The gate width of the fourth NMOS, and beta is the gain coefficient of the fourth NMOS; r2Is the second resistance value.
The current flowing through the third NMOS tube is equal to the current flowing through the fourth NMOS tube.
5. The open loop amplifier circuit of claim 1, wherein: the input port and the output port of the amplifying circuit are both differential signal ports.
6. The open loop amplifier circuit of claim 1 or 3, wherein: the amplifying circuit comprises a first NMOS, a second NMOS, a fifth NMOS, a sixth NMOS, an eighth NMOS, a second PMOS, a third PMOS, a sixth PMOS and a seventh PMOS; the circuit also comprises a first resistor and a third resistor;
the grid electrode of the second PMOS is connected with the grid electrode of the third PMOS and then is connected to the first node of the bias circuit;
the source electrode of the second PMOS and the source electrode of the third PMOS are connected with a power supply;
the grid electrode of the sixth PMOS is connected with the grid electrode of the seventh PMOS and then is connected to the second node of the bias circuit;
the grid electrodes of the fifth NMOS and the sixth NMOS are in short circuit, the source electrode of the fifth NMOS and the source electrode of the sixth NMOS are grounded, the drain electrode of the fifth NMOS is connected with the drain electrode of the sixth PMOS, and the drain electrode of the sixth NMOS is connected with the drain electrode of the seventh PMOS;
two ends of the first resistor are respectively connected with the drain electrode and the grid electrode of the sixth NMOS, and two ends of the third resistor are respectively connected with the drain electrode and the grid electrode of the fifth NMOS; the drain electrode of the fifth NMOS and the drain electrode of the sixth NMOS form a differential output port of the amplifying circuit;
the drain electrode of the first NMOS is connected with the drain electrode of the third PMOS, and the drain electrode of the eighth NMOS is connected with the drain electrode of the second PMOS;
the grid electrode of the first NMOS and the grid electrode of the eighth NMOS form a differential input port of the amplifying circuit;
the source electrode of the first NMOS is connected with the source electrode of the eighth NMOS and then connected with the drain electrode of the second NMOS; the source electrode of the second NMOS is grounded;
and the grid electrode of the second NMOS is connected with a third node of the biasing circuit.
7. The open loop amplifier circuit of claim 6, wherein: the voltage gain A of the amplifying circuit is related to the width-to-length ratios of the second resistor, the third resistor and the grid electrodes of the third NMOS tube, the fourth NMOS tube and the eighth NMOS tube:
I2＝kI1；
wherein, the I2 is the current flowing through the second NMOS transistor, which is the mirror image current of the fourth NMOS transistor,
is the gate width-to-length ratio of the third NMOS,
is the gate width-to-length ratio of the eighth NMOS,
the gate width-to-length ratio of the fourth NMOS.
8. The open loop amplifier circuit of claim 7, wherein: the voltage gain A of the amplifying circuit is determined by the characteristic parameters of the second resistor, the third NMOS tube, the fourth NMOS tube and the eighth NMOS tube, and has a compensation calibration function, so that the drift of the amplifier can be counteracted, and the offset voltage of an input signal can be counteracted.
9. The open loop amplifier circuit of claim 1, wherein: the compensation circuit is a current type DAC; the reference current input end of the amplifier is connected with a third node of the bias circuit, the output end of the amplifier is respectively connected with a differential output port of the amplifier circuit, and the grounding port of the amplifier is connected with the ground;
the current mode DAC compensates the amplifier circuit to ensure that VOP-VON is 0 when VIN-VIP is 0.
10. The open loop amplifier circuit of claim 3, wherein: in the bias circuit, a third NMOS and a fourth NMOS form a static operating point circuit, and the size ratio of the third NMOS to the fourth NMOS is 4: 1.
11. The open loop amplifier circuit of claim 6, wherein: the first resistor and the third resistor are equal in resistance value.
12. The open loop amplifier circuit of claim 9, wherein: the current type DAC circuit is a current type DAC with N +1 bits.
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| CN202110854075.6A CN113595511B (en) | 2021-07-28 | 2021-07-28 | Open loop amplifier circuit |
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| CN202110854075.6A CN113595511B (en) | 2021-07-28 | 2021-07-28 | Open loop amplifier circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397944A (en) * | 1993-04-09 | 1995-03-14 | Crystal Semiconductor Corporation | Dense offset calibration circuitry and method |
| CN107168440A (en) * | 2017-06-07 | 2017-09-15 | 电子科技大学 | The loop compensation circuit of alternative inside and outside a kind of piece based on error amplifier |
| CN109062310A (en) * | 2018-07-13 | 2018-12-21 | 厦门芯豪科技有限公司 | A kind of low-power consumption band-gap reference circuit with source compensated by using high-order curvature |
| US20200358406A1 (en) * | 2019-05-10 | 2020-11-12 | Cirrus Logic International Semiconductor Ltd. | Highly linear input and output rail-to-rail amplifier |
-
2021
- 2021-07-28 CN CN202110854075.6A patent/CN113595511B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397944A (en) * | 1993-04-09 | 1995-03-14 | Crystal Semiconductor Corporation | Dense offset calibration circuitry and method |
| CN107168440A (en) * | 2017-06-07 | 2017-09-15 | 电子科技大学 | The loop compensation circuit of alternative inside and outside a kind of piece based on error amplifier |
| CN109062310A (en) * | 2018-07-13 | 2018-12-21 | 厦门芯豪科技有限公司 | A kind of low-power consumption band-gap reference circuit with source compensated by using high-order curvature |
| US20200358406A1 (en) * | 2019-05-10 | 2020-11-12 | Cirrus Logic International Semiconductor Ltd. | Highly linear input and output rail-to-rail amplifier |
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| CN113595511B (en) | 2024-07-30 |
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