CN113594317B - Ultraviolet light emitting diode epitaxial wafer capable of reducing working voltage and preparation method thereof - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
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Abstract
The disclosure provides an ultraviolet light-emitting diode epitaxial wafer for reducing working voltage and a preparation method thereof, belonging to the technical field of light-emitting diodes. A p-type composite contact layer is added between the p-type AlGaN layer and the indium tin oxide layer and comprises a Mg contact sub-layer, a MgN sub-layer, a p-type GaN sub-layer and a p-type InGaN sub-layer which are sequentially stacked on the p-type AlGaN layer. The Mg contact sublayer reduces the resistance and increases the hole concentration. The MgN sublayer has a higher hole concentration and a lower overall resistance. The MgN sublayer is transited to the p-type GaN sublayer and the p-type InGaN sublayer, and the resistance is reduced. The overall body resistance of the light-emitting diode epitaxial wafer is reduced, the working voltage of the finally obtained ultraviolet light-emitting diode chip is further reduced, and the service life of the ultraviolet light-emitting diode chip is prolonged.
Description
Technical Field
The disclosure relates to the technical field of light emitting diodes, in particular to an ultraviolet light emitting diode epitaxial wafer for reducing working voltage and a preparation method thereof.
Background
The ultraviolet light emitting diode is a light emitting product for photocuring, is commonly used for sterilization, disinfection, curing of food sealing materials, curing of medical glue and the like, and an ultraviolet light emitting diode epitaxial wafer is a basic structure for preparing the ultraviolet light emitting diode. The ultraviolet light emitting diode epitaxial wafer generally comprises a substrate, and an n-type AlGaN layer, a multi-quantum well layer, a p-type AlGaN layer, a p-type GaN contact layer and an indium tin oxide layer which are grown on the substrate.
In the process of preparing the ultraviolet light emitting diode epitaxial wafer into the ultraviolet light emitting diode chip, a p electrode needs to be prepared on the surface of the p-type contact layer, and the p electrode conducts current into the indium tin oxide layer and the p-type GaN contact layer to realize current conduction and pn junction luminescence. However, ohmic contact between the p-type GaN contact layer and the indium tin oxide layer is high, so that the overall body resistance of the ultraviolet light emitting diode chip can be improved, the working voltage of the ultraviolet light emitting diode chip can be increased on the premise that the working current of the ultraviolet light emitting diode chip is not changed, and the service life of the ultraviolet light emitting diode chip is shortened.
Disclosure of Invention
The embodiment of the disclosure provides an ultraviolet light emitting diode epitaxial wafer capable of reducing working voltage and a preparation method thereof, which can reduce the working voltage of an ultraviolet light emitting diode chip and prolong the service life of the ultraviolet light emitting diode chip. The technical scheme is as follows:
the embodiment of the present disclosure provides an ultraviolet light emitting diode epitaxial wafer capable of reducing an operating voltage, which includes a substrate, and an n-type AlGaN layer, a multiple quantum well layer, a p-type AlGaN layer, a p-type composite contact layer, and an indium tin oxide layer sequentially stacked on the substrate,
the p-type composite contact layer comprises an Mg contact sublayer, an MgN sublayer, a p-type GaN sublayer and a p-type InGaN sublayer which are sequentially laminated on the p-type AlGaN layer, and the Mg contact sublayer comprises a plurality of Mg metal islands which are mutually spaced and laminated on the p-type AlGaN layer;
and growing an indium tin oxide layer on the p-type composite contact layer.
Optionally, a ratio of a thickness of the Mg contact sublayer to a thickness of the MgN sublayer is 1:1 to 1: 2.
Optionally, the thickness of the Mg contact sub-layer is 10-50 nm, and the thickness of the MgN sub-layer is 20-50 nm.
Optionally, the distance between two adjacent Mg metal islands is 0.5-3 nm.
Optionally, the thickness of the MgN sublayer is less than or equal to the thickness of the p-type GaN sublayer.
Optionally, the thickness of the p-type GaN sublayer is smaller than the thickness of the p-type InGaN sublayer.
Optionally, the thickness of the p-type GaN sublayer is 20-50 nm, and the thickness of the p-type InGaN sublayer is 50-100 nm.
Optionally, the p-type impurities in the p-type GaN sublayer and the p-type InGaN sublayer are both Mg, and the doping concentration of Mg in the p-type GaN sublayer is less than that of Mg in the p-type InGaN sublayer.
The embodiment of the disclosure provides a preparation method of an ultraviolet light emitting diode epitaxial wafer for reducing working voltage, which comprises the following steps:
providing a substrate;
growing an n-type AlGaN layer on the substrate;
growing a multi-quantum well layer on the n-type AlGaN layer;
growing a p-type AlGaN layer on the multi-quantum well layer;
growing a p-type composite contact layer on the p-type AlGaN layer, wherein the p-type composite contact layer is made of a material comprising a Mg contact sub-layer, a MgN sub-layer, a p-type GaN sub-layer and a p-type InGaN sub-layer which are sequentially stacked on the p-type AlGaN layer, and the Mg contact sub-layer comprises a plurality of Mg metal islands which are spaced from each other and stacked on the p-type AlGaN layer;
and growing an indium tin oxide layer on the p-type composite contact layer.
Optionally, growing a p-type composite contact layer on the p-type AlGaN layer, comprising:
introducing an Mg source with the flow rate of 100-600 sccm for 10-60 s into the reaction cavity to form a plurality of spaced Mg metal islands on the p-type AlGaN layer to obtain the Mg contact sub-layer;
and sequentially growing an MgN sublayer, a p-type GaN sublayer and a p-type InGaN sublayer on the Mg metal sublayer.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure include:
a p-type composite contact layer is added between the p-type AlGaN layer and the indium tin oxide layer and comprises a Mg contact sub-layer, a MgN sub-layer, a p-type GaN sub-layer and a p-type InGaN sub-layer which are sequentially stacked on the p-type AlGaN layer. The Mg contact sublayer on the p-type AlGaN layer comprises a plurality of spaced Mg metal islands stacked on the p-type AlGaN layer, the Mg metal islands have the function of reducing resistance, and Mg in the Mg metal islands can permeate into the p-type AlGaN layer to play a role of improving the hole concentration. The MgN sublayer on the Mg contact sublayer can realize good transition with the Mg contact sublayer, and the material characteristics of the MgN sublayer can ensure that the MgN sublayer has higher hole concentration and lower overall resistance. And the MgN sub-layer is sequentially transited to the p-type GaN sub-layer and the p-type InGaN sub-layer, so that the quality of the p-type GaN sub-layer and the p-type InGaN sub-layer grown on the MgN sub-layer can be ensured, and the In element In the p-type InGaN sub-layer can improve the lattice matching degree with the indium tin oxide layer, so that the quality of the indium tin oxide layer grown on the p-type InGaN sub-layer is improved. And the ohmic contact between the p-type InGaN sublayer and the ITO layer is smaller, and the resistance of the ohmic contact between the p-type InGaN sublayer and the ITO layer is also reduced. The p-type composite contact layer has good overall quality and high overall hole concentration, and the reduction of the ohmic contact resistance between the p-type InGaN sublayer and the indium tin oxide layer can reduce the overall body resistance of the light-emitting diode epitaxial wafer, so that the finally obtained working voltage of the ultraviolet light-emitting diode chip is reduced, and the service life of the ultraviolet light-emitting diode chip is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an ultraviolet light emitting diode epitaxial wafer for reducing an operating voltage according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another ultraviolet light emitting diode epitaxial wafer with reduced operating voltage provided by an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage according to an embodiment of the present disclosure;
fig. 4 is a flowchart of another method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an ultraviolet light emitting diode epitaxial wafer for reducing an operating voltage according to an embodiment of the present disclosure, and as shown in fig. 1, an ultraviolet light emitting diode epitaxial wafer for reducing an operating voltage according to an embodiment of the present disclosure includes a substrate 1, and an n-type AlGaN layer 2, a multiple quantum well layer 3, a p-type AlGaN layer 4, a p-type composite contact layer 5, and an indium tin oxide layer 6 sequentially stacked on the substrate 1.
The p-type composite contact layer 5 comprises a Mg contact sublayer 51, a MgN sublayer 52, a p-type GaN sublayer 53 and a p-type InGaN sublayer 54 which are sequentially laminated on the p-type AlGaN layer 4, wherein the Mg contact sublayer 51 comprises a plurality of Mg metal islands 511 which are mutually spaced and laminated on the p-type AlGaN layer 4.
A p-type composite contact layer 5 is additionally arranged between the p-type AlGaN layer 4 and the indium tin oxide layer 6, and the p-type composite contact layer 5 comprises a Mg contact sub-layer 51, a MgN sub-layer 52, a p-type GaN sub-layer 53 and a p-type InGaN sub-layer 54 which are sequentially laminated on the p-type AlGaN layer 4. The Mg contact sublayer 51 on the p-type AlGaN layer 4 includes a plurality of Mg metal islands 511 that are spaced apart from each other and stacked on the p-type AlGaN layer 4, the Mg metal islands 511 have a resistance reducing effect, and Mg in the Mg metal islands 511 can penetrate into the p-type AlGaN layer 4 to function to increase the hole concentration. The MgN sublayer 52 on the Mg contact sublayer 51 can realize a good transition with the Mg contact sublayer 51, and the material properties of the MgN sublayer 52 can also make the MgN sublayer 52 have a higher hole concentration and a lower overall resistance. And the MgN sublayer 52 is sequentially transited to the p-type GaN sublayer 53 and the p-type InGaN sublayer 54, so that the quality of the p-type GaN sublayer 53 and the p-type InGaN sublayer 54 grown on the MgN sublayer 52 can be ensured, and the In element In the p-type InGaN sublayer 54 can improve the lattice matching degree with the indium tin oxide layer 6, so that the quality of the indium tin oxide layer 6 grown on the p-type InGaN sublayer 54 is improved. And the ohmic contact between the p-type InGaN sublayer 54 and the ito layer 6 is small, the resistance of the ohmic contact between the p-type InGaN sublayer 54 and the ito layer 6 is also reduced. The p-type composite contact layer 5 has good overall quality and high overall hole concentration, and the reduction of the resistance of ohmic contact between the p-type InGaN sublayer 54 and the indium tin oxide layer 6 can reduce the overall body resistance of the light-emitting diode epitaxial wafer, so that the working voltage of the finally obtained ultraviolet light-emitting diode chip is reduced, and the service life of the ultraviolet light-emitting diode chip is prolonged. In fact, the addition of the plurality of Mg metal islands 511 can increase the roughness of the surface of the p-type AlGaN layer 4 to a certain extent, so as to improve the diffuse reflection of light on the surface of the p-type AlGaN layer 4, reduce the total reflection of light on the surface of the p-type AlGaN layer 4, and increase the light emitting efficiency of the ultraviolet light emitting diode chip.
Note that, if the quality of the entire p-type composite contact layer 5 is good, the defects existing inside the p-type composite contact layer 5 are small, and the possibility of capturing carriers by the defects is low, so that the influence of the defects on the carrier flow rate is small, and the increase in the carrier flow rate is equivalent to the resistance decrease to a certain extent, and the carriers include electrons and holes. An increase in hole concentration may also reduce resistance to some extent.
Optionally, the distance between two adjacent Mg metal islands 511 is 0.5-3 nm.
When the distance between two adjacent Mg metal islands 511 is within the above range, the Mg metal islands 511 in the Mg contact sublayer 51 have a good roughening effect on the surface of the p-type AlGaN layer 4, and the light emitting efficiency of the ultraviolet light emitting diode epitaxial wafer can be effectively improved. And also the bulk resistance of the p-type AlGaN layer 4 and the p-type composite contact layer 5 can be effectively reduced.
The distance between two adjacent Mg metal islands 511 is the distance between two closest points on the two adjacent Mg metal islands 511.
Illustratively, the ratio of the thickness of the Mg contact sublayer 51 to the thickness of the MgN sublayer 52 is 1:1 to 1: 2.
When the ratio of the thickness of the Mg contact sublayer 51 to the thickness of the MgN sublayer 52 is within the above range, it can be ensured that the Mg contact sublayer 51 can be effectively transited to the MgN sublayer 52, and the quality of the MgN sublayer 52 itself is good, so as to ensure that the quality of the finally obtained p-type composite contact layer 5 is good.
Illustratively, the thickness of the MgN sublayer 52 is less than or equal to the thickness of the p-type GaN sublayer 53.
The thickness of the MgN sublayer 52 is smaller than or equal to that of the p-type GaN sublayer 53, the MgN sublayer 52 can be transited to the p-type GaN sublayer 53, the p-type GaN sublayer 53 is guaranteed to have good quality, the p-type GaN sublayer 53 is thick, and the quality of the p-type InGaN sublayer 54 grown on the p-type GaN sublayer 53 can be guaranteed.
Optionally, the thickness of the Mg contact sub-layer 51 is 10-50 nm, and the thickness of the MgN sub-layer 52 is 20-50 nm.
When the thickness of the Mg contact sublayer 51 and the thickness of the MgN sublayer 52 are within the above ranges, the quality of the Mg contact sublayer 51 and the quality of the MgN sublayer 52 are good, and the MgN sublayer 52 can also provide a good growth foundation for the subsequent growth of the p-type GaN sublayer 53, so as to ensure that the quality of the finally obtained p-type composite contact layer 5 is good.
Illustratively, the thickness of the p-type GaN sublayer 53 is less than the thickness of the p-type InGaN sublayer 54.
After the p-type GaN sublayer 53 plays a transition role, the p-type InGaN sublayer 54 with a larger thickness grows on the p-type GaN sublayer 53, on one hand, the cost is controlled more reasonably, on the other hand, the quality of the p-type InGaN sublayer 54 with a larger thickness is better, and the p-type InGaN sublayer 54 can also realize good transition and matching with the indium tin oxide layer 6.
Optionally, the thickness of the p-type GaN sublayer 53 is 20-50 nm, and the thickness of the p-type InGaN sublayer 54 is 50-100 nm.
When the thickness of the p-type GaN sublayer 53 and the thickness of the p-type InGaN sublayer 54 are within the above ranges, the preparation specifications of most ultraviolet light emitting diode epitaxial wafers can be met, and the quality of the p-type GaN sublayer 53 and the quality of the p-type InGaN sublayer 54 are good.
Optionally, the p-type impurities in the p-type GaN sublayer 53 and the p-type InGaN sublayer 54 are both Mg, and the doping concentration of Mg in the p-type GaN sublayer 53 is less than that of Mg in the p-type InGaN sublayer 54.
The doping concentration of Mg in the p-type GaN sublayer 53 and the doping concentration of Mg in the p-type InGaN sublayer 54 conform to the size relationship in the previous section, so that the p-type GaN sublayer 53 and the p-type InGaN sublayer 54 can be well matched, the holes can be promoted to move towards the multiple quantum well layer 3, and the light emitting efficiency of the finally obtained ultraviolet light emitting diode chip is improved.
Illustratively, the doping concentration of Mg in the p-type GaN sublayer 53 is 1 × E21-1 × E22cm-3The doping concentration of Mg in the p-type InGaN sublayer 54 is 1 × E21-1 × E22cm-3。
The doping concentration of Mg in the p-type GaN sublayer 53 and the doping concentration of Mg in the p-type InGaN sublayer 54 are respectively in the above ranges, so that the p-type GaN sublayer 53 and the p-type InGaN sublayer 54 can be well matched, the quality of the p-type GaN sublayer 53 and the quality of the p-type InGaN sublayer 54 are good, a large number of holes can be promoted to move towards the multiple quantum well layer 3, and the light emitting efficiency of the finally obtained ultraviolet light emitting diode chip is improved.
Optionally, the In composition of the p-type InGaN sublayer 54 is 2-3 × E2 cm-3。
When the In composition In the p-type InGaN sublayer 54 is within the above range, the p-type InGaN sublayer 54 can be well matched and contacted with the indium tin oxide layer 6, the quality of the finally obtained p-type InGaN sublayer 54 and the indium tin oxide layer 6 is improved, and the contact resistance between the p-type InGaN sublayer 54 and the indium tin oxide layer 6 can be reduced.
Illustratively, the thickness of the ITO layer 6 is 10to 20 nm.
When the thickness of the ito layer 6 is within the above range, the obtained led epitaxial wafer has good quality, and the ito layer 6 itself has relatively low manufacturing cost.
Fig. 2 is a schematic structural diagram of another ultraviolet light emitting diode epitaxial wafer for reducing an operating voltage according to an embodiment of the present disclosure, and as can be seen from fig. 2, in another implementation manner according to an embodiment of the present disclosure, the ultraviolet light emitting diode epitaxial wafer may include a substrate 1, and a buffer layer 7, an undoped AlGaN layer 8, an n-type AlGaN layer 2, a multiple quantum well layer 3, an electron blocking layer 9, a p-type AlGaN layer 4, a p-type composite contact layer 5, and an indium tin oxide layer 6, which are sequentially stacked on the substrate 1.
The structure of the p-type composite contact layer 5 and the structure of the ito layer 6 in fig. 2 are the same as the structure of the p-type composite contact layer 5 and the structure of the ito layer 6 shown in fig. 1, respectively, and therefore, the description thereof is omitted.
Illustratively, the buffer layer 7 is an AlN layer. The lattice mismatch of the structure behind the substrate 1 and the buffer layer 7 can be effectively alleviated.
Optionally, the thickness of the buffer layer 7 is 15-35 nm. The lattice mismatch can be effectively alleviated without excessively increasing the preparation cost.
Alternatively, the thickness of the undoped AlGaN layer 8 may be 0.1 to 3.0 micrometers.
The thickness of the undoped AlGaN layer 8 is proper, the cost is reasonable, and the quality of the ultraviolet light-emitting diode can be effectively improved.
Alternatively, the thickness of the n-type AlGaN layer 2 can be between 1.5 and 3.5 micrometers.
The n-type AlGaN layer 2 can provide carriers reasonably, and the quality of the n-type AlGaN layer 2 itself is also good.
Illustratively, the n-type element doped in the n-type AlGaN layer 2 may be a Si element.
Illustratively, the multiple quantum well layer 3 may be a multiple quantum well structure. The multiple quantum well layer 3 includes GaN layers 31 and AlxGa1-xN layers 32 alternately stacked, wherein 0< x < 0.3. The luminous efficiency is better.
The number of layers of the GaN layer 31 and the AlxGa1-xN layer 32 may be the same, and the number of layers may be 4 to 12. The obtained multi-quantum well layer 3 has good quality and reasonable cost.
Alternatively, the thickness of the GaN layer 31 may be around 3nm, and the thickness of the AlxGa1-xN layer 32 may be between 8nm and 20 nm. Carriers can be efficiently trapped and light can be emitted.
Illustratively, the electron blocking layer 9 may be P-type AlyGa1-yN layer 0.2<y<0.5, P type AlyGa1-yThe thickness of the N layer may be between 15nm and 60 nm. The effect of blocking electrons is better.
Optionally, the thickness of the p-type AlGaN layer 4 is 50-300 nm. The obtained p-type AlGaN layer 4 has good quality as a whole.
Compared with the ultraviolet light emitting diode epitaxial wafer shown in fig. 1, the ultraviolet light emitting diode epitaxial wafer shown in fig. 2 is added with the hierarchical structures of the buffer layer 7, the undoped AlGaN layer 8 and the electron blocking layer 9, so that the quality of the finally obtained ultraviolet light emitting diode can be further improved.
Fig. 2 is only one implementation manner of the uv led provided by the embodiment of the present disclosure, and in other implementation manners provided by the present disclosure, the uv led may also be other forms of uv leds including a reflective layer, which is not limited by the present disclosure.
Fig. 3 is a flowchart of a method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage according to an embodiment of the present disclosure, and as shown in fig. 3, the method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage includes:
s101: a substrate is provided.
S102: an n-type AlGaN layer is grown on a substrate.
S103: and growing a multi-quantum well layer on the n-type AlGaN layer.
S104: and growing a p-type AlGaN layer on the multi-quantum well layer.
S105: the p-type composite contact layer grows on the p-type AlGaN layer, the material of the p-type composite contact layer comprises a Mg contact sub-layer, a MgN sub-layer, a p-type GaN sub-layer and a p-type InGaN sub-layer which are sequentially stacked on the p-type AlGaN layer, and the Mg contact sub-layer comprises a plurality of Mg metal islands which are spaced from each other and stacked on the p-type AlGaN layer.
S106: and growing an indium tin oxide layer on the p-type composite contact layer.
The technical effect of the method for manufacturing an ultraviolet light emitting diode epitaxial wafer for reducing the operating voltage shown in fig. 3 is the same as the technical effect corresponding to the structure of the ultraviolet light emitting diode epitaxial wafer for reducing the operating voltage shown in fig. 1, and therefore the technical effect of the method for manufacturing shown in fig. 3 can refer to the technical effect shown in fig. 1, and is not repeated here.
Illustratively, in step S105, growing a p-type composite contact layer on the p-type AlGaN layer, includes:
introducing an Mg source with the flow rate of 100-600 sccm for 10-60 s into the reaction cavity to form a plurality of spaced Mg metal islands on the p-type AlGaN layer to obtain an Mg contact sublayer; and sequentially growing an MgN sublayer, a p-type GaN sublayer and a p-type InGaN sublayer on the Mg metal sublayer.
And (3) introducing a 10-60 s Mg source with the flow of 100-600 sccm into the reaction cavity, so that a Mg metal island with good quality and stable form can be obtained, the quality of the Mg contact sublayer is good, and the stable growth of a subsequent structure can be ensured.
Optionally, the growth temperature and growth pressure of the p-type composite contact layer are 1100-1300 ℃ and 100-200 torr, respectively.
The p-type composite contact layer grows integrally under the conditions of high temperature and low pressure, so that the growth efficiency and the growth quality of the p-type composite contact layer can be ensured, p-type impurities doped In the p-type composite contact layer and In atoms In a p-type InGaN sublayer can better permeate into crystal cells of the layer under lower pressure, the finally obtained p-type composite contact layer is improved, the hole concentration In the p-type composite contact layer is ensured, and the matching degree with an indium tin oxide layer is ensured.
It should be noted that the MgN sublayer, the p-GaN sublayer, and the p-InGaN sublayer in the p-type composite contact layer can be grown by introducing related reaction gases and metal organic sources into the reaction chamber.
Fig. 4 is a flowchart of another method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage according to an embodiment of the present disclosure, and as shown in fig. 4, the method for manufacturing an ultraviolet light emitting diode epitaxial wafer with reduced operating voltage includes:
s201: a substrate is provided.
Alternatively, the substrate may be a sapphire substrate.
S202: and growing a buffer layer on the substrate, wherein the buffer layer is an AlN layer.
The AlN layer in step S202 may be obtained by magnetron sputtering,
optionally, the AlN layer is sputtered at 400-700 deg.C under 3000-5000W and 1-10 torr. A buffer layer of better quality can be obtained.
Optionally, step S202 further includes: and carrying out in-situ annealing treatment on the buffer layer, wherein the temperature is 1000-1200 ℃, the pressure range is 150-500 Torr, and the time is 5-10 minutes. The crystal quality of the buffer layer can be further improved.
S203: and growing an undoped AlGaN layer on the buffer layer.
Optionally, the undoped AlGaN layer grows at a temperature of 1000-1200 ℃ and under a pressure of 50-200 torr. The obtained undoped AlGaN layer has better quality, and the crystal quality of the finally obtained ultraviolet light-emitting diode can be improved.
Optionally, the undoped AlGaN layer is grown to a thickness of between 0.1 and 3.0 microns. The crystal quality of the finally obtained ultraviolet light emitting diode can be improved.
S204: and growing an n-type AlGaN layer on the undoped AlGaN layer.
Optionally, the n-type layer is a Si-doped n-type AlGaN layer. Easy preparation and acquisition.
Optionally, the growth temperature of the n-type AlGaN layer is 1000-1200 ℃, and the pressure is 50-200 torr. The obtained n-type AlGaN layer has better quality, and the crystal quality of the finally obtained ultraviolet light-emitting diode can be improved.
Illustratively, the n-type AlGaN layer is grown to a thickness of between 1 and 4.0 microns. The crystal quality of the finally obtained ultraviolet light emitting diode can be improved.
Illustratively, in the n-type AlGaN layer, the doping concentration of Si is 1018cm-3-1020cm-3In the meantime.
S205: and growing a multi-quantum well layer on the n-type AlGaN layer.
Alternatively, the multiple quantum well layer may include a multiple quantum well structure. The multiple quantum well layer comprises multiple alternately stacked GaN layers and AlxGa1-xN layer 0<x<0.3。
Illustratively, the growth temperature of the GaN layer ranges between 850 ℃ and 950 ℃, and the pressure ranges between 100Torr and 300 Torr; al (Al)xGa1-xThe growth temperature of the N layer is 900-1000 ℃, and the growth pressure is 50-200 Torr. A well-qualified multiple quantum well layer can be obtained.
Optionally, the well thickness of the GaN layer is around 3nm and the barrier thickness is between 8nm and 20 nm. The obtained multi-quantum well layer has good quality and reasonable cost.
S206: and growing an electron barrier layer on the multi-quantum well layer.
Alternatively, the electron blocking layer may be p-type AlyGa1-yN layer 0.2<y<0.5。
Alternatively, p-type AlyGa1-yThe growth temperature of the N layer is 900 DEG CAt-1050 ℃ and at a pressure of 50to 200 torr. The obtained p-type doped AlGaN layer has better quality, and the crystal quality of the finally obtained ultraviolet light-emitting diode can be improved.
Illustratively, the p-type doped AlGaN layer is grown to a thickness of between 15 and 60 nanometers. The crystal quality of the finally obtained ultraviolet light emitting diode can be improved.
S207: and growing a p-type AlGaN layer on the electron blocking layer.
Optionally, the growth temperature of the p-type AlGaN layer is 850-1050 ℃, and the pressure is 50-200 torr. The obtained p-type AlGaN layer has better quality, and the crystal quality of the finally obtained ultraviolet light-emitting diode can be improved.
Illustratively, the p-type AlGaN layer is grown to a thickness of between 100 and 300 nanometers. The crystal quality of the finally obtained ultraviolet light emitting diode can be improved.
S208: and growing a p-type composite contact layer on the p-type AlGaN layer.
Step S208 can refer to step S105 in fig. 3, and therefore step S208 is not described herein again.
S209: and growing an indium tin oxide layer on the p-type composite contact layer.
The growth temperature and growth pressure of the ITO layer can be 650-700 deg.C and 200-250 Torr, respectively. The indium tin oxide layer with better quality can be obtained.
The structure of the ultraviolet light emitting diode epitaxial wafer with reduced operating voltage after the step S209 is performed can be seen in fig. 2.
It should be noted that, in the embodiment of the present disclosure, a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition) apparatus is adopted to implement the growth method of the LED. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, silane (SiH4) as an N-type dopant, trimethyl aluminum (TMAl) as an aluminum source, and magnesium dicylocene (CP)2Mg) as a P-type dopant.
Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.
Claims (10)
1. The ultraviolet light-emitting diode epitaxial wafer for reducing the working voltage is characterized by comprising a substrate, and an n-type AlGaN layer, a multi-quantum well layer, a p-type AlGaN layer, a p-type composite contact layer and an indium tin oxide layer which are sequentially laminated on the substrate,
the p-type composite contact layer comprises an Mg contact sublayer, an MgN sublayer, a p-type GaN sublayer and a p-type InGaN sublayer which are sequentially stacked on the p-type AlGaN layer, and the Mg contact sublayer comprises a plurality of Mg metal islands which are spaced from each other and stacked on the p-type AlGaN layer.
2. The ultraviolet light-emitting diode epitaxial wafer as claimed in claim 1, wherein the ratio of the thickness of the Mg contact sub-layer to the thickness of the MgN sub-layer is 1: 1-1: 2.
3. The ultraviolet light-emitting diode epitaxial wafer as claimed in claim 1, wherein the thickness of the Mg contact sub-layer is 10-50 nm, and the thickness of the MgN sub-layer is 20-50 nm.
4. The ultraviolet light-emitting diode epitaxial wafer as claimed in any one of claims 1 to 3, wherein the distance between two adjacent Mg metal islands is 0.5 to 3 nm.
5. The ultraviolet light emitting diode epitaxial wafer as claimed in any one of claims 1 to 3, wherein the thickness of the MgN sub-layer is less than or equal to that of the p-type GaN sub-layer.
6. The ultraviolet light emitting diode epitaxial wafer as claimed in any one of claims 1 to 3, wherein the thickness of the p-type GaN sub-layer is smaller than that of the p-type InGaN sub-layer.
7. The ultraviolet light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the thickness of the p-type GaN sub-layer is 20 to 50nm, and the thickness of the p-type InGaN sub-layer is 50to 100 nm.
8. The ultraviolet light emitting diode epitaxial wafer as claimed in any one of claims 1 to 3, wherein both p-type impurities in the p-type GaN sub-layer and the p-type InGaN sub-layer are Mg, and the doping concentration of Mg in the p-type GaN sub-layer is less than that of Mg in the p-type InGaN sub-layer.
9. The preparation method of the ultraviolet light emitting diode epitaxial wafer capable of reducing the working voltage is characterized by comprising the following steps of:
providing a substrate;
growing an n-type AlGaN layer on the substrate;
growing a multi-quantum well layer on the n-type AlGaN layer;
growing a p-type AlGaN layer on the multi-quantum well layer;
growing a p-type composite contact layer on the p-type AlGaN layer, wherein the p-type composite contact layer is made of a material comprising a Mg contact sub-layer, a MgN sub-layer, a p-type GaN sub-layer and a p-type InGaN sub-layer which are sequentially stacked on the p-type AlGaN layer, and the Mg contact sub-layer comprises a plurality of Mg metal islands which are spaced from each other and stacked on the p-type AlGaN layer;
and growing an indium tin oxide layer on the p-type composite contact layer.
10. The method of claim 9, wherein growing a p-type composite contact layer on the p-type AlGaN layer comprises:
introducing an Mg source with the flow rate of 100-600 sccm for 10-60 s into the reaction cavity to form a plurality of spaced Mg metal islands on the p-type AlGaN layer to obtain the Mg contact sub-layer;
and sequentially growing an MgN sublayer, a p-type GaN sublayer and a p-type InGaN sublayer on the Mg metal sublayer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN106206884A (en) * | 2016-09-26 | 2016-12-07 | 湘能华磊光电股份有限公司 | LED extension P layer growth method |
| CN109920889A (en) * | 2019-01-29 | 2019-06-21 | 华灿光电（浙江）有限公司 | Gallium nitride based LED epitaxial slice and its manufacturing method |
| CN112133797A (en) * | 2020-08-11 | 2020-12-25 | 华灿光电（浙江）有限公司 | Growth method of light emitting diode epitaxial wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101008285B1 (en) * | 2005-10-28 | 2011-01-13 | 주식회사 에피밸리 | ?-nitride semiconductor light emitting device |
| CN106206884A (en) * | 2016-09-26 | 2016-12-07 | 湘能华磊光电股份有限公司 | LED extension P layer growth method |
| CN109920889A (en) * | 2019-01-29 | 2019-06-21 | 华灿光电（浙江）有限公司 | Gallium nitride based LED epitaxial slice and its manufacturing method |
| CN112133797A (en) * | 2020-08-11 | 2020-12-25 | 华灿光电（浙江）有限公司 | Growth method of light emitting diode epitaxial wafer |
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