CN113594130A - Semiconductor package device and method of manufacturing the same - Google Patents

Semiconductor package device and method of manufacturing the same Download PDF

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Publication number
CN113594130A
CN113594130A CN202110818932.7A CN202110818932A CN113594130A CN 113594130 A CN113594130 A CN 113594130A CN 202110818932 A CN202110818932 A CN 202110818932A CN 113594130 A CN113594130 A CN 113594130A
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CN
China
Prior art keywords
capacitor
semiconductor package
package device
layer
circuit layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110818932.7A
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Chinese (zh)
Inventor
吕文隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202110818932.7A priority Critical patent/CN113594130A/en
Publication of CN113594130A publication Critical patent/CN113594130A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a first circuit layer; a second circuit layer; and a capacitor located between and electrically connected to the first and second circuit layers, the capacitor having a Young's modulus greater than that of the second circuit layer. The semiconductor packaging device is beneficial to improving the anti-warping capability of the semiconductor packaging device, reducing the warping degree of the semiconductor packaging device when being heated and further improving the yield of products.

Description

Semiconductor package device and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
In a fan-out Substrate (FOSub) structure, there is a coupling condition between a Redistribution Layer (RDL) line and a Substrate (Substrate) line, resulting in the occurrence of signal noise in the line. In order to eliminate the above-described coupling condition, a decoupling capacitor may be provided between the substrate and the rewiring layer. However, the conventional decoupling capacitor has a large difference in thermal expansion coefficient from the substrate, and the entire structure may warp (warp) when heated.
Therefore, a new technical solution is needed to solve at least one of the above technical problems.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a first circuit layer;
a second circuit layer;
a capacitor located between and electrically connected to the first and second circuit layers, the capacitor having a Young's modulus greater than that of the second circuit layer.
In some alternative embodiments, the capacitor comprises at least one sheet-like single-layer structure, each single-layer structure comprising a respective conductive portion and insulating portion.
In some alternative embodiments, the capacitor includes at least one first single-layer structure and at least one second single-layer structure, the first single-layer structure and the second single-layer structure are alternately stacked, a first conductive portion of the first single-layer structure serves as a positive electrode of the capacitor, and a second conductive portion of the second single-layer structure serves as a negative electrode of the capacitor.
In some alternative embodiments, the capacitor includes at least two first single-layer structures electrically connected to each other and at least two second single-layer structures electrically connected to each other.
In some alternative embodiments, the relative permittivity of the dielectric of the capacitor is greater than 5.
In some alternative embodiments, the relative permittivity of the dielectric of the capacitor is greater than 15 and less than 30.
In some alternative embodiments, the dielectric of the capacitor is a ceramic material.
In some optional embodiments, the semiconductor package device further includes a first conductive via penetrating the capacitor and electrically connected to the first and second circuit layers, respectively.
In some optional embodiments, the semiconductor package device further comprises a second conductive via penetrating the second circuit layer and electrically connected to the second circuit layer and the capacitor, respectively.
In some alternative embodiments, the first conductive hole has a hollow structure.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
bonding a capacitor on the first circuit layer;
forming a first conductive hole on the capacitor to electrically connect the capacitor and the first wiring layer;
bonding a second circuit layer on the capacitor;
forming a second conductive hole on the second circuit layer to electrically connect the second circuit layer and the capacitor.
In some optional embodiments, before the adhering the capacitor on the first circuit layer, the method further comprises:
printing a metal material on the green ceramic material to obtain a single-layer structure;
stacking at least two of the single-layer structures to obtain a stacked structure;
forming an opening in the stacked structure;
sintering the stacked structure to obtain the capacitor.
In the semiconductor packaging device and the manufacturing method thereof provided by the disclosure, the Young modulus of the capacitor is larger than that of the second circuit layer (namely the rewiring layer), so that the anti-warping capability of the semiconductor packaging device is favorably improved, the warping degree of the semiconductor packaging device when being heated is reduced, and the product yield is further improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art semiconductor package device;
fig. 2 and 3 are first and second schematic views of a semiconductor package device according to an embodiment of the present invention;
fig. 4 to 9 are schematic views of a method of manufacturing a semiconductor package device according to an embodiment of the present invention.
Description of the symbols:
11. a substrate; 12. a rewiring layer; 13. a capacitor; 14. an adhesive layer; 100. a first circuit layer; 200. a second circuit layer; 300. a capacitor; 310. a first single-layer structure; 311. a first insulating portion; 312. a first conductive portion; 320. a second single-layer structure; 321. a second insulating portion; 322. a second conductive portion; 400. an adhesive layer; 510. a first conductive via; 520. a second conductive via; 910. masking; 920. scraping the head; 930. a metal material; 940. a carrier; 950. and (6) opening holes.
Detailed Description
The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic diagram of a semiconductor package device in the prior art. As shown in fig. 1, the semiconductor package device includes a substrate 11 and a rewiring layer 12, which are connected by an adhesive layer 14. A capacitor 13 is provided between the substrate 11 and the rewiring layer 12. The capacitor 13 has a multilayer structure, and is formed of a conductive layer and an insulating layer stacked in this order. In the semiconductor package device, the capacitor 13 is formed in a rewiring (fan-out) structure, and the difference between the thermal expansion coefficient thereof and that of the substrate 11 is large, which causes warpage of the entire structure when heated.
Fig. 2 and 3 are first and second schematic views of a semiconductor package device according to an embodiment of the present invention.
As shown in fig. 2, the semiconductor package device in the present embodiment includes a first circuit layer 100, a second circuit layer 200, and a capacitor 300.
In the present embodiment, the first circuit layer 100 and the second circuit layer 200 are connected by the adhesive layer 400. The first wiring layer 100 is, for example, a substrate, and the second wiring layer 200 is, for example, a rewiring layer.
In the present embodiment, the capacitor 300 is located between the first circuit layer 100 and the second circuit layer 200 and electrically connected to the first circuit layer 100 and the second circuit layer 200. The young's modulus of the capacitor 300 is greater than the young's modulus of the second line layer 200. The capacitor 300 includes a conductive material and a dielectric (i.e., an insulating material), and the young's modulus of the capacitor 300 can be obtained by considering the young's modulus of the conductive material and the young's modulus of the dielectric together.
In the present embodiment, the young's modulus of the capacitor 300 is greater than that of the second wiring layer 200 (i.e., the rewiring layer), and therefore the young's modulus of the capacitor 300 in the present embodiment is greater than that of a capacitor (manufactured using a rewiring structure) in the related art, and therefore the capacitor 300 in the present embodiment has a higher ability to resist warpage.
In one example, the dielectric material of the capacitor 300 may be a Ceramic material (Ceramic) with a large young's modulus (300 GPa-400GPa), which is advantageous for making the young's modulus of the capacitor 300 larger than the young's modulus of the second line layer 200 (i.e., the redistribution layer). In addition, the ceramic material has a low thermal expansion coefficient, which is beneficial to reducing the difference between the thermal expansion coefficients of the capacitor 300 and other parts, and further reducing the warping degree of the semiconductor packaging device when being heated.
In one example, capacitor 300 may include at least one sheet-like, single-layer structure. Each single-layer structure includes a respective conductive portion and an insulating portion. The conductive portion is made of a metal such as copper, and the insulating portion is made of a ceramic.
In one example, the capacitor 300 may include at least one first single-layer structure 310 and at least one second single-layer structure 320, the first single-layer structure 310 and the second single-layer structure 320 being alternately stacked. The first single-layer structure 310 includes a first conductive portion 312 and a first insulating portion 311. The second single-layer structure 320 includes a second conductive portion 322 and a second insulating portion 321. The first conductive portion 312 of the first single-layered structure 310 serves as a positive electrode of the capacitor 300, and the second conductive portion 322 of the second single-layered structure 320 serves as a negative electrode of the capacitor 300. The first conductive portions 312 of the respective first single-layer structures 310 are electrically connected to each other, and the second conductive portions 322 of the respective second single-layer structures 320 are electrically connected to each other.
The prior art capacitor usually uses PI material (Polyimide) as a dielectric, and the relative dielectric constant (relative dielectric constant) of the PI material is small (about 5), so that it needs to be made into a multi-layer structure to meet the capacity requirement.
In the present embodiment, a material having a higher relative permittivity (i.e., greater than 5) may be employed as the dielectric of the capacitor 300 in order to increase the capacitance of the capacitor 300 and reduce the thickness of the capacitor 300, thereby further reducing the warpage of the structure. For example, a ceramic material (having a relative dielectric constant greater than 15 and less than 30) may be employed as the dielectric of the capacitor 300.
In the present embodiment, the semiconductor package device further includes a first conductive via 510 and a second conductive via 520. The first conductive via 510 penetrates the capacitor 300 and is electrically connected to the first and second circuit layers 100 and 200, respectively. And a second conductive via 520, the second conductive via 520 penetrating the second circuit layer 200 and electrically connected to the second circuit layer 200 and the capacitor 300, respectively.
Through the first conductive via 510 and the second conductive via 520, electrical connection between the first circuit layer 100, the second circuit layer 200, and the capacitor 300 may be achieved. In addition, the first circuit layer 100, the second circuit layer 200 and the capacitor 300 may be electrically connected by a bonding wire or the like, which is not limited in this embodiment.
As shown in the upper part of fig. 3, the first conductive hole 510 may have a hollow structure. As shown in the lower portion of fig. 3, the first conductive hole 510 may have a solid structure. Above-mentioned hollow structure is favorable to reducing material consumption, and above-mentioned solid construction is favorable to realizing better electric connection effect.
In the present embodiment, the young's modulus of the capacitor 300 is greater than the young's modulus of the second circuit layer 200 (i.e., the redistribution layer), which is beneficial to improving the anti-warpage capability of the semiconductor package device, reducing the warpage of the semiconductor package device when being heated, and further improving the product yield.
The embodiment also provides a manufacturing method of the semiconductor packaging device. As shown in fig. 4-9, the method includes the steps of:
first, as shown in fig. 7, the capacitor 300 is bonded to the first wiring layer 100 by the bonding layer 400.
In a second step, as shown in fig. 8, a first conductive via 510 is formed on the capacitor 300 to electrically connect the capacitor 300 and the first wiring layer 100.
Third, as shown in fig. 8, the second circuit layer 200 is bonded to the capacitor 300.
Fourth, as shown in fig. 9, a second conductive via 520 is formed on the second wiring layer 200 to electrically connect the second wiring layer 200 and the capacitor 300.
Prior to the first step described above, the capacitor 300 may be formed by:
first, as shown in fig. 4, the metal material 930 on the mask 910 is scraped by the scraping head 920 to print the metal material 930 on the green ceramic material to obtain a single-layer structure.
Next, as shown in fig. 5, at least two single-layer structures are stacked on the carrier 940 to obtain a stacked structure.
Thereafter, as shown in fig. 6, an opening 950 is formed in the stacked structure.
Finally, the stacked structure is sintered to obtain the capacitor 300.
The method for manufacturing a semiconductor package device in this embodiment can achieve the technical effects of the semiconductor package device described above, and will not be described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:
a first circuit layer;
a second circuit layer;
a capacitor located between and electrically connected to the first and second circuit layers, the capacitor having a Young's modulus greater than that of the second circuit layer.
2. The semiconductor package device of claim 1, wherein the capacitor comprises at least one sheet-like single-layer structure, each single-layer structure comprising respective conductive and insulating portions.
3. The semiconductor package device of claim 2, wherein the capacitor comprises at least one first monolayer structure and at least one second monolayer structure, the first monolayer structure and the second monolayer structure being alternately stacked, a first conductive portion of the first monolayer structure serving as a positive electrode of the capacitor, and a second conductive portion of the second monolayer structure serving as a negative electrode of the capacitor.
4. The semiconductor package device of claim 3, wherein the capacitor comprises at least two first monolayer structures and at least two second monolayer structures, the at least two first monolayer structures being electrically connected to each other and the at least two second monolayer structures being electrically connected to each other.
5. The semiconductor package device of claim 1, wherein the relative permittivity of the capacitor dielectric is greater than 5.
6. The semiconductor package device of claim 5, wherein the relative permittivity of the capacitor dielectric is greater than 15 and less than 30.
7. The semiconductor package device of claim 1, wherein the capacitor dielectric is a ceramic material.
8. The semiconductor package device of claim 1, further comprising a first conductive via that extends through the capacitor and is electrically connected to the first and second circuit layers, respectively.
9. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises a second conductive via that penetrates the second circuit layer and is electrically connected to the second circuit layer and the capacitor, respectively.
10. The semiconductor package device of claim 8, wherein the first conductive via has a hollow structure.
CN202110818932.7A 2021-07-20 2021-07-20 Semiconductor package device and method of manufacturing the same Pending CN113594130A (en)

Priority Applications (1)

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CN202110818932.7A CN113594130A (en) 2021-07-20 2021-07-20 Semiconductor package device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110818932.7A CN113594130A (en) 2021-07-20 2021-07-20 Semiconductor package device and method of manufacturing the same

Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259479A (en) * 2021-12-01 2023-06-13 日月光半导体制造股份有限公司 Capacitor and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259479A (en) * 2021-12-01 2023-06-13 日月光半导体制造股份有限公司 Capacitor and electronic device

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