CN108682630B - Method for manufacturing package substrate - Google Patents
Method for manufacturing package substrate Download PDFInfo
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- CN108682630B CN108682630B CN201810463523.8A CN201810463523A CN108682630B CN 108682630 B CN108682630 B CN 108682630B CN 201810463523 A CN201810463523 A CN 201810463523A CN 108682630 B CN108682630 B CN 108682630B
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- layer
- metal layer
- manufacturing
- package substrate
- laminated structure
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 238000004806 packaging method and process Methods 0.000 claims abstract description 14
- 238000000059 patterning Methods 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 9
- 238000003825 pressing Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 206010040954 Skin wrinkling Diseases 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention relates to a method for manufacturing a package substrate. The method for manufacturing a package substrate according to an embodiment of the invention includes providing a first stacked structure, providing a carrier, laminating a first dielectric layer and the first stacked structure on a first surface and a second surface of the carrier, patterning a first metal layer of the first stacked structure, providing a third stacked structure, patterning a second metal layer of the third stacked structure, and laminating the second dielectric layer and the patterned third stacked structure on the patterned first stacked structure. The manufacturing method of the packaging substrate provided by the invention not only realizes the fine layout of the internal elements of the packaging substrate, but also improves the output efficiency of the packaging substrate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a packaging substrate.
Background
In the current semiconductor packaging technology, a capacitor element is arranged inside a packaging substrate, which is a solution for realizing the miniaturization of an electronic system, and the solution is generally applied to electronic products such as microphones, wearable devices and the like, and can play roles in filtering, timing, decoupling and storing electric energy. In this way, not only can the stability and reliability of the product be improved, but also the physical size of the product is reduced.
The capacitor element is generally composed of two copper foils having a thickness of 35 μm or 70 μm and a dielectric material layer having a thickness of 20 μm or less between the two copper foils. Since the dielectric material layer is very thin, it is difficult to provide sufficient support in the manufacturing process, the conventional technology usually manufactures the circuits on the upper and lower sides of the dielectric material layer in two steps, but only one substrate can be produced at a time in the process, and the production efficiency is low. Moreover, since the thickness of the package substrate to be manufactured is too thin, the conventional technology also has a high requirement on the thin plate capability of the machine.
Therefore, there is a need for an improved method for manufacturing a package substrate to solve the above-mentioned problems of the prior art.
Disclosure of Invention
An objective of the present invention is to provide a method for manufacturing a package substrate, in which an embedded capacitor is combined with a micro circuit, and a carrier is used to provide support in the manufacturing method, so as to improve the yield efficiency of the package substrate.
An embodiment of the present invention provides a method for manufacturing a package substrate, including: providing a first laminated structure, wherein the first laminated structure comprises a first metal layer; providing a carrier plate, wherein the carrier plate is provided with a first surface and a second surface which are opposite; pressing a first dielectric layer and a first laminated structure on the first surface and the second surface of the carrier plate, wherein the first dielectric layer is positioned between the carrier plate and the first laminated structure; patterning the first metal layer of the first laminated structure to form a first circuit layer; providing a third laminated structure, wherein the third laminated structure comprises a second metal layer, a third metal layer and a capacitor dielectric layer positioned between the second metal layer and the third metal layer; patterning the second metal layer of the third laminated structure to form a second circuit layer; and pressing the second dielectric layer and the patterned third laminated structure on the patterned first laminated structure, wherein the second dielectric layer is positioned between the patterned third laminated structure and the patterned first laminated structure.
According to an embodiment of the present invention, the first stacked structure further includes a resistive material layer between the first dielectric layer and the first metal layer.
According to an embodiment of the present invention, the carrier includes a sacrificial layer, a fourth metal layer disposed on two opposite surfaces of the sacrificial layer, and a fifth metal layer disposed on a surface of the fourth metal layer.
According to an embodiment of the invention, the manufacturing method of the package substrate further includes patterning the resistance material layer to form the resistance layer.
According to an embodiment of the present invention, the method for manufacturing the package substrate further includes removing the sacrificial layer and the fourth metal layer.
According to an embodiment of the present invention, the method for manufacturing the package substrate further includes forming a plurality of conductive vias in the first dielectric layer, the second dielectric layer and the capacitor dielectric layer, wherein the conductive vias are conductive to at least two of the second metal layer, the second circuit layer, the first circuit layer and the fifth metal layer. And patterning the second metal layer to form a third circuit layer. The fifth metal layer is patterned to form a fourth line layer. A solder mask is formed on a surface of the package substrate.
The packaging substrate provided by the embodiment of the invention is different from the traditional design, has the layout characteristics of the embedded capacitor and the fine circuit, and utilizes the carrier plate to provide support in the manufacturing method, thereby not only realizing the fine layout of the elements in the packaging substrate, but also improving the output efficiency of the packaging substrate.
Drawings
FIGS. 1-10 are cross-sectional views of a package substrate at various stages of its manufacture according to an embodiment of the present invention
Detailed Description
In order that the spirit of the invention may be better understood, some preferred embodiments of the invention are described below.
Fig. 1-10 are cross-sectional views of a package substrate at various stages of its manufacture according to an embodiment of the present invention. However, it is fully understood by those skilled in the art that the package substrate 100 shown in fig. 10 can be obtained according to other embodiments of the present invention without being limited to the steps illustrated in fig. 1-10. In other words, as will be apparent to those skilled in the art based on the following disclosure, the manufacturing process of the package substrate is adjusted according to the structure or production requirement of the package substrate, and the embodiment is merely an example of the manufacturing process of the package substrate and is not intended to limit the specific manufacturing method thereof.
First, referring to fig. 1, a first stacked structure 10 and a carrier 20 are provided. The first laminated structure 10 includes a first metal layer 11 and a resistive material layer 12. The resistance material layer 12 in this embodiment may be a copper foil with one surface coated with a nickel-phosphorus alloy, and the thickness is greater than 0 micrometer and equal to or less than 0.5 micrometer. The carrier 20 has a first surface 201 and a second surface 202 opposite to each other, and includes a sacrificial layer 21, a fourth metal layer 22 respectively disposed on the two opposite surfaces of the sacrificial layer 21, and a fifth metal layer 23 disposed on the fourth metal layer 22, wherein the fourth metal layer 22 is located between the sacrificial layer 21 and the fifth metal layer 23.
Next, referring to fig. 2, the first dielectric layer 13 and the first stacked structure 10 are laminated on the first surface 201 and the second surface 202 of the carrier 20. The first dielectric layer 13 is located between the carrier 20 and the first stacked structure 10, and directly contacts the fifth metal layer 23 of the carrier 20 and the resistive material layer 12 of the first stacked structure 10.
Referring to fig. 3, a first patterning process is performed on a portion of the first stacked structure 10, for example, corresponding regions of the first metal layer 11 and the resistive material layer 12 may be sequentially etched until corresponding regions of the first dielectric layer 13 are exposed.
Next, as shown in fig. 4, a second patterning process is performed on the first stacked structure 10. The sub-patterned region does not overlap with the first sub-patterned region shown in fig. 3, and the sub-patterning exposes only the resistive material layer 12, thereby forming the first wiring layer 14 and the resistive layer 15.
Referring to fig. 5, a third stacked configuration 30 is provided. The third stacked structure 30 includes a second metal layer 31, a third metal layer 32, and a capacitor dielectric layer 33. The capacitor dielectric layer 33 is located between the second metal layer 31 and the third metal layer 32, and has a thickness greater than 0 micron and less than or equal to 20 microns. Further, the third metal layer 32 of the third stacked structure 30 is patterned to form a second circuit layer 34.
Next, referring to fig. 6, the second dielectric layer 16 and the patterned third stacked structure 30 are pressed on the first circuit layer 14, so that the first circuit layer 14 is embedded in the second dielectric layer 16, i.e., the bottom surface of the second dielectric layer 16 is flush with the bottom surface of the first circuit layer 14, and meanwhile, the second circuit layer 34 is also embedded in the second dielectric layer 16, i.e., the top surface of the second dielectric layer 16 is flush with the top surface of the second circuit layer 34.
The sacrificial layer 21 and the fourth metal layer 22 are removed to obtain two identical substrate structures, wherein one substrate structure is shown in fig. 7.
Next, referring to fig. 8, via holes are formed on the respective ones of the second metal layer 31, the capacitor dielectric layer 33, the second line layer 34, the second dielectric layer 16, the first line layer 14, the resistive layer 15, and the first dielectric layer 13 using a drilling method such as laser drilling, which is commonly used in the art, and the via holes 17 are further formed by filling with metal. The conductive via 17 may conduct at least two of the second metal layer 31, the second line layer 34, the first line layer 14, and the fifth metal layer 23.
Next, referring to fig. 9, a partial region of the second metal layer 31 is patterned until the capacitor dielectric layer 33 is exposed, thereby forming a third circuit layer 35. Meanwhile, a partial region of the fifth metal layer 23 is patterned until the first dielectric layer 13 is exposed, thereby forming a fourth wiring layer 24.
Finally, the solder mask layer 18 is formed on a partial area of the exposed surfaces of the third circuit layer 35 and the fourth circuit layer 24, and the package substrate 100 shown in fig. 10 is finally formed.
Compared with the traditional manufacturing method of the packaging substrate with the embedded capacitor, the manufacturing method of the packaging substrate provided by the embodiment of the invention has the following advantages: on one hand, the carrier plate introduced in the embodiment of the invention can provide good support, so that the risk of wrinkling of the carrier plate and the plate is avoided, and the operability of the packaging substrate in the whole circuit manufacturing process is improved; on the other hand, in the manufacturing method provided by the embodiment of the invention, two packaging substrates can be obtained by one-time operation, so that the output efficiency of the packaging substrates is doubled, and the production cost is reduced.
As will be appreciated by those skilled in the art, the above embodiments only demonstrate a method for manufacturing a package substrate, which is fully applicable to the manufacturing process of other package substrates including embedded capacitors, for example, it can further stack more circuit layers.
While the foregoing has been with reference to the disclosure of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the invention, which are covered by the claims of the present patent application.
Claims (9)
1. A method of manufacturing a package substrate, comprising:
providing a first laminated structure, wherein the first laminated structure comprises a first metal layer;
providing a carrier plate, wherein the carrier plate is provided with a first surface and a second surface which are opposite;
pressing a first dielectric layer and the first laminated structure on the first surface and the second surface of the carrier plate, wherein the first dielectric layer is positioned between the carrier plate and the first laminated structure;
patterning the first metal layer of the first laminated structure to form a first circuit layer;
providing a third laminated structure, wherein the third laminated structure comprises a second metal layer, a third metal layer and a capacitor dielectric layer positioned between the second metal layer and the third metal layer;
patterning the third metal layer of the third stacked structure to form a second circuit layer; and
and pressing a second dielectric layer and the patterned third laminated structure on the patterned first laminated structure, wherein the second dielectric layer is positioned between the patterned third laminated structure and the patterned first laminated structure.
2. The method of manufacturing a package substrate according to claim 1, wherein the first stacked structure further comprises:
a resistive material layer between the first dielectric layer and the first metal layer.
3. The method of manufacturing a package substrate according to claim 1, wherein the carrier comprises:
the metal layer comprises a sacrificial layer, fourth metal layers arranged on two opposite surfaces of the sacrificial layer and fifth metal layers arranged on the surfaces of the fourth metal layers.
4. The method of manufacturing a package substrate according to claim 2, further comprising:
and patterning the resistance material layer to form a resistance layer.
5. The method of manufacturing a package substrate according to claim 3, further comprising:
removing the sacrificial layer and the fourth metal layer.
6. The method of manufacturing a package substrate according to claim 3, further comprising:
and forming a plurality of conduction columns in the first dielectric layer, the second dielectric layer and the capacitor dielectric layer, wherein the conduction columns conduct at least two of the second metal layer, the second circuit layer, the first circuit layer and the fifth metal layer.
7. The method of manufacturing a package substrate of claim 1, further comprising:
and patterning the second metal layer to form a third circuit layer.
8. The method of manufacturing a package substrate according to claim 3, further comprising:
patterning the fifth metal layer to form a fourth line layer.
9. The method of manufacturing a package substrate of claim 1, further comprising:
and forming a solder mask layer on the surface of the packaging substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810463523.8A CN108682630B (en) | 2018-05-15 | 2018-05-15 | Method for manufacturing package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810463523.8A CN108682630B (en) | 2018-05-15 | 2018-05-15 | Method for manufacturing package substrate |
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| Publication Number | Publication Date |
|---|---|
| CN108682630A CN108682630A (en) | 2018-10-19 |
| CN108682630B true CN108682630B (en) | 2020-04-24 |
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| CN201810463523.8A Active CN108682630B (en) | 2018-05-15 | 2018-05-15 | Method for manufacturing package substrate |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1832664A (en) * | 2005-03-11 | 2006-09-13 | 三星电机株式会社 | Method of fabricating printed circuit board having embedded multi-layer passive devices |
| CN108174514A (en) * | 2018-02-24 | 2018-06-15 | 苏州生益科技有限公司 | A kind of production method of burying capacitance circuit board |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3810311B2 (en) * | 2001-12-04 | 2006-08-16 | 日本ビクター株式会社 | Printed circuit board and manufacturing method thereof |
| JP2003332749A (en) * | 2002-01-11 | 2003-11-21 | Denso Corp | Passive device built-in substrate, its fabrication method, and material for building passive device built-in substrate |
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2018
- 2018-05-15 CN CN201810463523.8A patent/CN108682630B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1832664A (en) * | 2005-03-11 | 2006-09-13 | 三星电机株式会社 | Method of fabricating printed circuit board having embedded multi-layer passive devices |
| CN108174514A (en) * | 2018-02-24 | 2018-06-15 | 苏州生益科技有限公司 | A kind of production method of burying capacitance circuit board |
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| Publication number | Publication date |
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| CN108682630A (en) | 2018-10-19 |
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