CN113593621A - SRAM memory cell capable of double-node inversion - Google Patents

SRAM memory cell capable of double-node inversion Download PDF

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Publication number
CN113593621A
CN113593621A CN202110811803.5A CN202110811803A CN113593621A CN 113593621 A CN113593621 A CN 113593621A CN 202110811803 A CN202110811803 A CN 202110811803A CN 113593621 A CN113593621 A CN 113593621A
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China
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inverter
node
previous
phase inverter
storage node
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刘中阳
肖军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an SRAM memory cell capable of double-node overturning. The method comprises the following steps: the circuit comprises a latch circuit and a transmission circuit, wherein the latch circuit comprises eight inverters which are sequentially connected to form a ring-shaped passage; the output end of the current phase inverter is connected with the first input end of the previous phase inverter of the current phase inverter to form a storage node of the current phase inverter; the transmission circuit comprises eight transmission MOS tubes, any one transmission MOS tube is correspondingly connected with a storage node of a phase inverter, and each storage node is sequentially and alternately connected with a first bit line and a second bit line through the corresponding transmission MOS tube according to the connection direction of the annular passage; the eight transmission MOS tubes are connected with a word line, and the conduction of the transmission MOS tubes is controlled through the word line; and the second input end of the previous inverter of the current inverter is connected with the output end of the previous mth inverter of the current inverter, and the storage node of the previous mth inverter and the storage node of the previous inverter are connected with the same bit line together.

Description

SRAM memory cell capable of double-node inversion
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an SRAM memory cell capable of double-node overturning.
Background
The advancement of integrated circuit technology nodes brings a lot of challenges to the reliability of chips, and one of the challenges is soft errors caused by single event effect. I.e., a single energetic particle hitting a sensitive node of the semiconductor device, the ionization caused by the particle will create a current pulse in the device, which in turn will cause a device logic soft error.
Fig. 1 shows a circuit structure of a storage unit of an SRAM (Static Random Access Memory) in the related art, and it can be seen from fig. 1 that the SRAM includes a first NOMS pass transistor and a second NMOS pass transistor, a source and a drain of the first NOMS pass transistor are respectively connected to a bit line BL and a storage node Q, a source and a drain of the second NOMS pass transistor are respectively connected to a bit line BLB and a storage node QN, a first inverter and a second inverter that are interlocked with each other are connected between the storage node Q and the storage node QN, and the first inverter and the second inverter have the same structure and are both CMOS inverters formed by connecting one NMOS transistor and one PMOS transistor.
However, when the data of the storage node of the SRAM memory shown in fig. 1 is inverted, the SRAM memory cell that can be inverted by one-bit node fails due to the double-node inversion caused by charge sharing, and the SRAM memory does not have the function of tolerating soft errors.
Disclosure of Invention
The application provides an SRAM memory cell capable of double-node inversion, which can solve the problem that the storage function is invalid due to the fact that the SRAM memory cell does not have soft error resistance in the related technology.
In order to solve the technical problem described in the background art, the present application provides an SRAM memory cell capable of double node inversion, including: latch circuit and transmission circuit
The latch circuit comprises eight phase inverters, and the eight phase inverters are sequentially connected to form an annular passage; each of the inverters includes a first input terminal, a second input terminal, and an output terminal;
determining any one phase inverter in the latch circuit as a current phase inverter, wherein the output end of the current phase inverter is connected with the first input end of the previous phase inverter of the current phase inverter to form a storage node of the current phase inverter;
the transmission circuit comprises eight transmission MOS tubes, any one transmission MOS tube is correspondingly connected with a storage node of a phase inverter, and each storage node is sequentially and alternately connected with a first bit line and a second bit line through the corresponding transmission MOS tube according to the connection direction of the annular passage; the eight transmission MOS tubes are connected with word lines, and the conduction of the transmission MOS tubes is controlled through the word lines;
and the second input end of the previous inverter of the current inverter is connected with the output end of the previous mth inverter of the current inverter, and the storage node of the previous mth inverter and the storage node of the previous inverter are connected with the same bit line together.
Optionally, the second input terminal of the previous inverter is connected to the previous sixth inverter output terminal of the current inverter, and the storage node of the previous sixth inverter and the storage node of the current inverter are connected to the same bit line in common.
Optionally, any one of the inverters in the latch circuit includes an NMOS transistor and a PMOS transistor;
one source drain end of the PMOS tube is connected with a power supply, the other source drain end of the PMOS tube is connected with one source drain end of the NMOS tube to serve as the output end of the phase inverter, and the other source drain end of the NMOS tube is grounded;
two input ends of the phase inverter are respectively a grid electrode of a PMOS tube and a grid electrode of an NMOS tube in the phase inverter.
Optionally, the first input end of the inverter is a gate of the NMOS transistor of the inverter, and the second input end of the inverter is a gate of the PMOS transistor of the inverter.
Optionally, the first input end of the inverter is a gate of the PMOS transistor of the inverter, and the second input end of the inverter is a gate of the NMOS transistor of the inverter.
Optionally, a source-drain end of each of the transfer MOS transistors is connected to the output end of the corresponding inverter, another source-drain end of the transfer MOS transistor is connected to the first bit line or the second bit line, and a gate of the transfer MOS transistor is connected to the word line.
Alternatively, the first input terminal and the second input terminal of any one of the inverters in the latch circuit are configured to simultaneously input a high-level signal or simultaneously input a low-level signal.
Optionally, eight inverters in the latch circuit are sequentially arranged and connected in a clockwise direction to form a ring-shaped path.
The technical scheme at least comprises the following advantages: the SRAM storage unit capable of allowing the double-node turnover can allow the problem that two storage nodes are turned over at the same time, namely when two storage nodes are turned over simultaneously in a transient error mode, the SRAM storage unit can enable the storage nodes to return to the original correct logic level through self feedback.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a circuit configuration of an SRAM memory cell in the related art;
FIG. 2 is a schematic diagram illustrating a structure of an SRAM memory cell capable of dual-node inversion according to an embodiment of the present application;
FIG. 3 is a simplified schematic diagram of the SRAM cell of FIG. 2 that is capable of two-node inversion;
FIG. 4 is a schematic diagram of an embodiment of the circuit structure of the SRAM memory cell with double node inversion shown in FIG. 2;
FIG. 5 is a schematic diagram of the SRAM memory cell circuit structure with double node flip shown in FIG. 2, showing another embodiment;
fig. 6 shows the node level variation curves of the SRAM cell provided in fig. 4 when various operations are performed.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 shows a schematic diagram of a structure of a dual-node flip-flop SRAM memory cell according to an embodiment of the present application, and as can be seen from fig. 2, the dual-node flip-flop SRAM memory cell according to this embodiment includes a ring-shaped latch circuit and a transmission circuit located in a ring of the ring-shaped latch circuit.
The transmission circuit comprises eight transmission MOS tubes (M1-M8), namely a first transmission MOS tube M1, a second transmission MOS tube M2, a third transmission MOS tube M3, a fourth transmission MOS tube M4, a fifth transmission MOS tube M5, a sixth transmission MOS tube M6, a seventh transmission MOS tube M7 and an eighth transmission MOS tube M8. One end of any one of the eight transmission MOS transistors (M1-M8) is connected with the first bit line BL or the second bit line BLB, and all the transmission MOS transistors are connected with a word line, and the conduction of the transmission MOS transistors is controlled by the word line.
The latch circuit includes eight inverters (C1 to C8), a first inverter C1, a second inverter C2, a third inverter C3, a fourth inverter C4, a fifth inverter C5, a sixth inverter C6, a seventh inverter C7, and an eighth inverter C8. Each inverter includes a first input terminal, a second input terminal, and an output terminal.
The eight inverters (C1-C8) are sequentially arranged in a clockwise direction, and the output end of any one of the eight inverters (C1-C8) is connected with the first input end of the previous inverter to form a storage node of the inverter, so that eight storage nodes (N1-N8) are formed, the eight inverters (C1-C8) are sequentially connected to form a ring-shaped path, the input-output direction of each inverter is a loop signal propagation direction, and the input-output direction of each inverter is consistent with the connection direction of the eight inverters (C1-C8) in the latch circuit.
Any one of the transmission MOS tubes in the transmission circuit is correspondingly connected with a storage node of an inverter, and eight storage nodes (Q1-Q8) are sequentially and alternately connected with the first bit line BL and the second bit line BLB through the corresponding transmission MOS tubes according to the connection direction of a ring-shaped path formed by the eight inverters (C1-C8).
And the second input end of the previous inverter is connected with the output end of the previous mth inverter, and the storage node of the previous mth inverter and the storage node of the previous inverter are connected with the same bit line together.
The previous inverter refers to the first inverter in the clockwise direction ahead of the current inverter, the mth previous inverter refers to the mth inverter in the clockwise direction ahead of the current inverter, and m is an integer greater than 1 and less than or equal to 7.
For example, as shown in fig. 2, if the first inverter C1 is determined to be the current inverter and the previous inverter of the first inverter C1 is the second inverter C2, the output terminal S1 of the first inverter C1 is connected to the first input terminal of the second inverter C2, forming the storage node of the first inverter C1, i.e., the first storage node Q1. A second input of the second inverter C2 is connected to the output of the first sixth inverter. It should be noted that the first sixth inverter of the first inverter C1 is the sixth inverter in the clockwise direction of the first inverter C1, i.e., the seventh inverter C7 of the latch circuit. The output terminal S7 of the seventh inverter C7 is connected to the second input terminal of the second inverter C2. The storage node Q7 of the seventh inverter C7 and the storage node Q1 of the first inverter C1 are connected to the first bit line BL through corresponding transfer MOS transistors.
If the second inverter C2 is determined to be the current inverter, the previous inverter of the second inverter C2 is the third inverter C3, and the output terminal S2 of the second inverter C2 is connected to the first input terminal of the third inverter C3, forming the storage node of the second inverter C2, i.e., the second storage node Q2. A second input of the second inverter C2 is connected to the output of the first sixth inverter. It should be noted that the first sixth inverter of the second inverter C2 is the sixth inverter in the clockwise direction of the second inverter C2, i.e., the eighth inverter C8 of the latch circuit. The output terminal S8 of the eighth inverter C8 is connected to the second input terminal of the third inverter C3. Wherein the storage node Q8 of the eighth inverter C8 and the storage node Q2 of the second inverter C2 are connected to the second bit line BLB through corresponding transfer MOS transistors.
Fig. 3 shows a simplified schematic diagram of the SRAM cell with double node flip shown in fig. 2. as can be seen from fig. 3, two input terminals of the first inverter C1 are respectively connected to the output terminal S6 of the sixth inverter C6 and the output terminal S8 of the eighth inverter C8. Two input ends of the second inverter C2 are connected to the output end S7 of the seventh inverter C7 and the output end S1 of the first inverter C1, respectively. Two input ends of the third inverter C3 are connected to the output end S8 of the eighth inverter C8 and the output end S2 of the second inverter C2, respectively. Two input ends of the fourth inverter C4 are connected to the output end S1 of the first inverter C1 and the output end S3 of the third inverter C3, respectively. Two input ends of the fifth inverter C5 are connected to the output end S2 of the second inverter C2 and the output end S4 of the fourth inverter C4, respectively. Two input ends of the sixth inverter C6 are connected to the output end S3 of the third inverter C3 and the output end S5 of the fifth inverter C5, respectively. Two input ends of the seventh inverter C7 are connected to the output end S4 of the fourth inverter C4 and the output end S6 of the sixth inverter C6, respectively. Two input terminals of the eighth inverter C8 are connected to the output terminal S5 of the fifth inverter C5 and the output terminal S7 of the seventh inverter C7, respectively, to form a ring-shaped latch path.
The working principle of the SRAM memory cell with double-node inversion shown in FIG. 2 and FIG. 3 is as follows:
if the data of the first storage node Q1 and the third storage node Q3 are flipped simultaneously, the data of the output terminal S1 of the first inverter C1 and the data of the output terminal S3 of the third inverter C3 are flipped simultaneously. The output terminal S1 of the first inverter C1 and the output terminal S3 of the third inverter C3 act as two input terminals of the fourth inverter C4, thereby causing the output terminal S4 of the fourth inverter C4 to flip data. Namely, S1, S3 and S4 flip, but since the levels of S2 and S8 are correct, S3 restores the correct level from the flip, and then S3 and S5 with the correct level ensure that the level of S6 is correct, S6 and S8 with the correct level make the level of S1 correct from the flip, and S1 and S3 correct from the flip make the level of S4 correct, so far, all flip nodes restore the correct level data.
It can be seen from the foregoing that the SRAM memory cell capable of dual-node inversion provided in the embodiment of the present application can tolerate the problem that two storage nodes are inverted at the same time, that is, when two storage nodes are inverted by a transient error at the same time, the SRAM memory cell can return each storage node to the original correct logic level through its own feedback.
Fig. 4 is a schematic diagram illustrating an embodiment of the circuit structure of the SRAM memory cell with double node flip shown in fig. 2, and it can be seen from fig. 4 that any one of the inverters in the latch circuit includes an NMOS transistor and a PMOS transistor. One source drain end of the PMOS tube is connected with a power supply, the other source drain end of the PMOS tube is connected with one source drain end of the NMOS tube to be used as the output end of the phase inverter, and the other source drain end of the NMOS tube is grounded; two input ends of the phase inverter are respectively a grid electrode of a PMOS tube and a grid electrode of an NMOS tube in the phase inverter. In the embodiment shown in fig. 4, a first input terminal of any one of the inverters in the latch circuit is a gate of an NMOS transistor of the inverter, and a second input terminal of the inverter is a gate of a PMOS transistor of the inverter. Therefore, the output end of any one inverter in the latch circuit and the current inverter are connected with the grid electrode of the NMOS tube of the previous inverter, and the grid electrode of the PMOS tube of the previous inverter is connected with the output end of the sixth previous inverter of the current inverter.
Fig. 5 shows a circuit structure of the SRAM memory cell with double node flip shown in fig. 2, and another embodiment is schematically shown, in the embodiment shown in fig. 5, the structure of any one inverter in the latch circuit is the same as that in the embodiment shown in fig. 4, that is, any one inverter in the latch circuit comprises one NMOS transistor and one PMOS transistor. One source drain end of the PMOS tube is connected with a power supply, the other source drain end of the PMOS tube is connected with one source drain end of the NMOS tube to be used as the output end of the phase inverter, and the other source drain end of the NMOS tube is grounded; two input ends of the phase inverter are respectively a grid electrode of a PMOS tube and a grid electrode of an NMOS tube in the phase inverter. However, in the embodiment shown in fig. 5, the first input terminal of any one of the inverters in the latch circuit is the gate of the PMOS transistor of the inverter, and the second input terminal is the gate of the NMOS transistor of the inverter. Therefore, the output end of any one inverter in the latch circuit and the output end of the current inverter are connected with the grid electrode of the PMOS tube of the previous inverter, and the grid electrode of the NMOS tube of the previous inverter is connected with the output end of the sixth previous inverter of the current inverter.
Fig. 6 shows the node level variation curve of the SRAM memory cell provided in fig. 4 when performing various operations, with reference to fig. 6:
when the SRAM memory cell performs a write operation, the word line WL is set to a high level, and the transfer MOS transistors M1 and M8 shown in fig. 4 are all turned on. The first bit line BL is set to a high level and the second bit line BLB is set to a low level, or the first bit line BL is set to a low level and the second bit line BLB is set to a high level. Data is transferred into the SRAM memory cell through the first bit line BL and the second bit line BLB, and reaches storage nodes Q1 to Q8 in the SRAM memory cell through the transfer MOS transistor M1 and the value M8, so that a '0' or a '1' write operation is realized.
When the SRAM memory cell performs the holding operation, the word line WL is set to the low level, so that the transfer MOS transistors M1 to M8 shown in fig. 4 are all in the off state. The first bit line BL is disconnected from the inverter storage nodes Q1, Q3, Q5 and Q7, and the second bit line BLB is disconnected from the inverter storage nodes Q2, Q4, Q6 and Q8, and the storage nodes in the SRAM memory cell, i.e., the inverter storage nodes Q1 to Q8, are locked with each other, and can maintain a data storage data state. In the variation curve shown in fig. 5, when the SRAM memory cell performs the holding operation stage, at the time of 12ns, the output terminal S1 of the first inverter C1 and the output terminal S3 of the third inverter C3 are affected by the disturb pulse SEU, so that the transient error flip occurs, but as can be seen from fig. 6, the SRAM memory cell capable of double-node flip provided in this embodiment can return each storage node to the original correct logic level through its own feedback. Similarly, at the time of 52ns, the output terminal S1 of the first inverter C1 and the output terminal S3 of the third inverter C3 are affected by the glitch pulse SEU to generate transient error flip, but as can be seen from fig. 6, the SRAM cell with double node flip provided in this embodiment can return the storage nodes to the original correct logic level through self-feedback.
When the SRAM memory cell is read, the first bit line BL and the second bit line BLB are precharged. The word line WL is set to high level, so that the transfer MOS transistors M1-M8 shown in fig. 4 are all in an on state. Data are transmitted to the corresponding first bit line BL and second bit line BLB through the storage nodes Q1 to Q8 in the SRAM storage unit and the transmission MOS transistors M1 to M8, and the read operation after the data of the SRAM storage unit are kept is realized.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. An SRAM memory cell capable of double node flipping, comprising: latch circuit and transmission circuit
The latch circuit comprises eight phase inverters, and the eight phase inverters are sequentially connected to form an annular passage; each of the inverters includes a first input terminal, a second input terminal, and an output terminal;
determining any one phase inverter in the latch circuit as a current phase inverter, wherein the output end of the current phase inverter is connected with the first input end of the previous phase inverter of the current phase inverter to form a storage node of the current phase inverter;
the transmission circuit comprises eight transmission MOS tubes, any one transmission MOS tube is correspondingly connected with a storage node of a phase inverter, and each storage node is sequentially and alternately connected with a first bit line and a second bit line through the corresponding transmission MOS tube according to the connection direction of the annular passage; the eight transmission MOS tubes are connected with word lines, and the conduction of the transmission MOS tubes is controlled through the word lines;
and the second input end of the previous inverter of the current inverter is connected with the output end of the previous mth inverter of the current inverter, and the storage node of the previous mth inverter and the storage node of the previous inverter are connected with the same bit line together.
2. The dual node flipped-tolerant SRAM memory cell of claim 1,
and the second input end of the previous inverter is connected with the output end of a previous sixth inverter of the current inverter, and the storage node of the previous sixth inverter and the storage node of the current inverter are connected to the same bit line together.
3. The dual node flipped-tolerant SRAM memory cell of claim 1 or 2,
any one phase inverter in the latch circuit comprises an NMOS tube and a PMOS tube;
one source drain end of the PMOS tube is connected with a power supply, the other source drain end of the PMOS tube is connected with one source drain end of the NMOS tube to serve as the output end of the phase inverter, and the other source drain end of the NMOS tube is grounded;
two input ends of the phase inverter are respectively a grid electrode of a PMOS tube and a grid electrode of an NMOS tube in the phase inverter.
4. The SRAM memory cell with double-node flip of claim 1 or 2, wherein the first input terminal of the inverter is a gate of the NMOS transistor of the inverter, and the second input terminal of the inverter is a gate of the PMOS transistor of the inverter.
5. The dual node flipped-tolerant SRAM memory cell of claim 1 or 2,
the first input end of the phase inverter is the grid electrode of the PMOS tube of the phase inverter, and the second input end of the phase inverter is the grid electrode of the NMOS tube of the phase inverter.
6. The SRAM memory cell with double-node flip function as claimed in claim 1, wherein one source drain terminal of each of the transfer MOS transistors is connected to an output terminal of the corresponding inverter, the other source drain terminal of the transfer MOS transistor is connected to the first bit line or the second bit line, and a gate of the transfer MOS transistor is connected to the word line.
7. The double-node-flip-flop-capable SRAM memory cell of claim 1, wherein the first input and the second input of any one of the inverters in the latch circuit are configured to simultaneously input a high-level signal or simultaneously input a low-level signal.
8. The dual-node flipped-enabled SRAM cell of claim 1 wherein eight inverters in said latch circuit are sequentially arranged in a clockwise direction to form a circular path.
CN202110811803.5A 2021-07-19 2021-07-19 SRAM memory cell capable of double-node inversion Pending CN113593621A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177846B1 (en) * 1998-04-27 2001-01-23 Kabushiki Kaisha Toshiba Ring oscillator type voltage controlled oscillator
US20130229858A1 (en) * 2012-03-02 2013-09-05 Maxwell Consulting Fault Tolerant Static Random-Access Memory
CN104700889A (en) * 2015-03-27 2015-06-10 中国科学院自动化研究所 Storage unit based on DICE structure for static random access storage device
CN111091855A (en) * 2018-10-24 2020-05-01 中国科学院上海微系统与信息技术研究所 Single event upset detection circuit and method based on static random access memory cell array

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177846B1 (en) * 1998-04-27 2001-01-23 Kabushiki Kaisha Toshiba Ring oscillator type voltage controlled oscillator
US20130229858A1 (en) * 2012-03-02 2013-09-05 Maxwell Consulting Fault Tolerant Static Random-Access Memory
CN104700889A (en) * 2015-03-27 2015-06-10 中国科学院自动化研究所 Storage unit based on DICE structure for static random access storage device
CN111091855A (en) * 2018-10-24 2020-05-01 中国科学院上海微系统与信息技术研究所 Single event upset detection circuit and method based on static random access memory cell array

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