KR101958405B1 - Memory cell and operation method thereof - Google Patents

Abstract

The memory cell is started. The memory cell includes a first load transistor, a second load transistor, a third load transistor, and a fourth load transistor connected between a corresponding one of the plurality of storage nodes and a power supply line, A first drive transistor, a second drive transistor, a third drive transistor and a fourth drive transistor, each of which is connected between a corresponding storage node of the plurality of storage nodes and a ground line, A first access transistor, a second access transistor, and a third access transistor connected between either a bit line and a complementary bit line and a corresponding storage node of the plurality of storage nodes, Transistor and a fourth access transistor.

Description

[0001] MEMORY CELL AND OPERATION METHOD THEREOF [0002]

An embodiment according to the concept of the present invention relates to a radiation-resistant memory cell and a method of operating the same, and more particularly to a memory cell capable of stably flipping the potential of a storage node using an additional access transistor and an operation method thereof will be.

The reliability of the operation of the hardware system may be lowered due to a soft-error due to radiation in an environment where extreme radiation exists, such as a space. Particularly, on-chip static random access memory (SRAM) occupies a significant portion of the chip area (about 50% or more), so it can be exposed to soft errors with high probability. MA Bajura, Y. Boulghassoul, R. Naseer, S. Das Gupta, A. Witulski, and J. Sondeen, et al., "A Modified and Algorithmic Limits for an ECC-based Approach to Hardening Sub- 4, pp. 935-945, Aug. 2007), typical 6T (6-transistor) SRAMs do not provide sufficient reliability in extreme radiation environments such as space. Therefore, in the present specification, an inner radiation memory cell, for example, an SRAM cell, which is resistant to process variation, is proposed.

M. A. Bajura, Y. Boulghassoul, R. Naseer, S. Das Gupta, A. Witulski, and J. Sondeen et al., "Modes and algorithmic limits for an ECC-based approach to hardening sub-100 nm SRAMs", IEEE Trans. Nucl. Sci., Vol. 54, no. 4, pp. 935-945, Aug. 2007. Shah M. Jahinuzzaman and Manoj Sachdev, "A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability ", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. 56, NO. 6, DECEMBER 2009.

SUMMARY OF THE INVENTION The present invention provides a memory cell and a method of driving the same that can additionally include an access transistor to stably flip the potential of all the storage nodes.

A memory cell according to an embodiment of the present invention includes a first load transistor, a second load transistor, a third load transistor, and a second load transistor connected between a power supply line and a corresponding one of the plurality of storage nodes, A fourth drive transistor, a fourth drive transistor, a third drive transistor, and a fourth drive transistor, each of which is connected between a ground line and a corresponding storage node of the plurality of storage nodes, A first access transistor, a second access transistor, and a second access transistor connected between any one of the bit line and the complementary bit line and a corresponding one of the plurality of storage nodes, 3 access transistor and a fourth access transistor.

A memory cell according to another embodiment of the present invention includes a first PMOS transistor connected between a first storage node and a power supply line, a second PMOS transistor connected between a second storage node and the power supply line, A third PMOS transistor connected between the first storage node and the power supply line, a fourth PMOS transistor connected between the fourth storage node and the power supply line, a first NMOS transistor connected between the first storage node and the ground line, A second NMOS transistor connected between the second storage node and the ground line, a third NMOS transistor connected between the third storage node and the ground line, a fourth NMOS transistor connected between the fourth storage node and the ground line, An NMOS transistor, a fifth NMOS transistor connected between the complementary bit line and the first storage node, A sixth NMOS transistor connected between the storage node, a seventh NMOS transistor connected between the bit line and the third storage node, and an eighth NMOS transistor connected between the complementary bit line and the fourth storage node, Wherein a gate of the first PMOS transistor is connected to the third storage node, a gate of the second PMOS transistor is connected to the fourth storage node, and a gate of the third PMOS transistor is connected to the fourth storage node Wherein the gate of the fourth PMOS transistor is connected to the third storage node, the gate of the first NMOS transistor is connected to the second storage node, and the gate of the second NMOS transistor is connected to the first storage node The gate of the third NMOS transistor is connected to the first storage node, the fourth NM The gates of the OS transistors are connected to the second storage node, and the gates of the fifth to eighth NMOS transistors are connected to a word line.

A method of operating a memory cell according to an embodiment of the present invention includes applying a voltage and a driving voltage of 0V to each of a bit line and a complementary bit line, activating a word line, A second access transistor connected between the bit line and the second storage node, a third access transistor connected between the bit line and the third storage node, and a third access transistor connected between the complementary bit line and the fourth storage node, Turning on a fourth access transistor connected between the storage nodes and turning on of the first access transistor and turning on of the fourth access transistor, And the fourth storage node are pulled up, and the turn-on operation of the second access transistor and the turn- - by the third operation on the storage node pool to the second storage node, and a step-down is.

According to the memory cell and the driving method thereof according to the embodiment of the present invention, a radiation-resistant memory cell having improved writing stability, read stability, and read access stability can be provided.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a circuit diagram of a conventional SRAM (Static Random Access Memory) cell.
FIG. 2A shows the voltage waveform during the write operation period of the 10T SRAM cell shown in FIG.
FIG. 3 shows a simulation result for evaluating the write failure probability of the 10T SRAM cell shown in FIG.
4 is a circuit diagram of a cell according to an embodiment of the present invention.
5A shows the layout of the SRAM cell shown in FIG.
Fig. 5B shows the layout of the cell shown in Fig.
Figs. 6A and 6B are diagrams for explaining a write operation of the cell shown in Fig. 4, in which Fig. 6A shows the current flow and Fig. 6B shows the voltage waveform resulting from the simulation.
FIG. 7 shows simulation results of write performance for these cells, respectively.
Figure 8 shows the results of lead SNM evaluation for each cell.
9 is a graph showing the comparison result of the development time of the bit line swing.
Figure 10 shows a simulation scenario borrowing the exponential current power model.
11 shows the results of the simulation of Fig.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example, without departing from the scope of the right according to the concept of the present invention, the first element may be referred to as a second element, The component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having" and the like are used to specify that there are features, numbers, steps, operations, elements, parts or combinations thereof described herein, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

1 is a circuit diagram of a conventional SRAM (Static Random Access Memory) cell.

Referring to Figure 1, a 10T SRAM cell, also known as a 10-transistor Quatro SRAM cell, includes four interlocked storage nodes A, B, C, The structure of the interlocked storage node has the effect of preventing data flipping due to soft-error. Also, since the storage node in the interlock structure of a 10T SRAM cell is the gate input of two PMOS transistors (p-channel metal oxide semiconductor transistors) or two NMOS transistors (n-channel metal oxide semiconductor transistors) single event transient noise may weaken (or enhance) the pull-up of the PMOS transistors or the pull-down of the NMOS transistors. However, the interlock structure does not provide soft-error immunity to other complimentary transistors. For example, a radiation particle may hit node B of a 10T SRAM cell, causing the potential of node B to drop temporarily. SET noise can weaken the pull-down of transistors N1 and N4. However, since SET noise does not affect transistors P1 and P4, the voltages at nodes A and D hardly change. As a result, the voltage of the node B is recovered after a certain time, and the original cell data can be protected from the SET noise.

Hereinafter, the write stability of a 10T SRAM cell will be described. To write a value that is contrary to the value stored in the 10T SRAM cell, each of node A and node B must be pulled up and pulled down by two access transistors N5 and N6. First, when the access transistors are turned on, the access transistor N6 pulls down the voltage of the node B, which may weaken the pull-down strength of the drive transistor N1. At this time, since the access transistor N5 pulls up the node A, the potential of the node A may increase. This can enhance the pull-down of the drive transistor N2 and lower the voltage at node C. [ At this time, since the potential of the node D is still " 0 ", the pull-up intensity of the load transistor P2 is not yet weakened. This may imply that the pull-up of the load transistor P2 and the pull-down of the drive transistor N2 are in conflict. In order to successfully perform the write operation, the pull-down of the drive transistor N2 must be strong enough to sufficiently lower the potential of the node C. [ In addition, a pool of access transistor N5 - it can be seen that because the up suffered a threshold voltage (V _th) drop hayeoteum not sufficiently reach the node A and the voltage level '1' of the potential. This weakens the pull-down of the drive transistor N2 and, as a result, may be a factor that hinders the light stability of the 10T SRAM cell.

FIG. 2A shows the voltage waveform during the write operation period of the 10T SRAM cell shown in FIG. 2A, it is possible to explain a write failure due to a process variation. Due to the weak pull-up intensity of access transistor N5, node A is not flipped sufficiently. When the potential of node B is lowered, P4 and N4 are both turned off, node D becomes temporarily floating, and capacitive coupling between node B and node D The potential drop of the node B caused a negative potential of the node D. This further enhances the pull-up of P2 and destroys the light stability of the 10T SRAM cell. The above-described problem can be alleviated by introducing a boosted word line.

2B shows a result of applying the boosted word line as another example of the voltage waveform during the write operation period of the 10T SRAM cell shown in FIG.

In FIG. 2B, a word line voltage of 1.1 V, which is 100 mV larger than the word line voltage of FIG. 2A, is used. Since the boosted word line voltage enhances the pull-up of the access transistor N5, a successful write operation can be performed despite the drawbacks described with FIG. 2A. However, this approach is undesirable from a power point of view because it must generate a boosted power supply.

FIG. 3 shows a simulation result for evaluating the write failure probability of the 10T SRAM cell shown in FIG.

The simulation was performed at the worst process and temperature corner. Also, assuming a temperature variation between 0 ° C and 85 ° C, the worst process and temperature corner is observed at 0 ° C with SS (slow NMOS and slow PMOS). Because the write failure probability depends on the transistor size of the SRAM cell, the MC simulation was performed under several sizing scenarios. This is shown below.

To obtain good read static noise margin (SNM), the pull-down1 (N1 and N3) -to-access (N5 and N6) ratios are between 1.5 and 1.7.

- For reliable light, the pull-up1 (P1 and P3) -to-access (N5 and N6) ratio is 1 and the pull-up2 (P2 and P4) -to-pull-down2 Lt; 0.75.

It has also been assumed that all the pull-up transistors P1, P2, P3 and P4 and all the access transistors N5 and N6 have a minimum width under the logic design rule. However, the width of the pull-down transistors N1, N2, N3 and N4 varies according to the above-described assumption. In addition, it is assumed that all transistors have a minimum length. Among the above-mentioned two widths, the electrons are denoted by W _NA in FIG. 3 and the latter by W _ND . In SRAM, the probability of a write failure is highly related to the write access rate. In the simulation of FIG. 3, a normal access rate of 250 MHz is assumed. Nonetheless, the write failure probability of a 10T SRAM cell is quite large, regardless of the size of the transistor. In addition, the simulation results show that the write failure probability is significantly reduced when using a word line with a boosted voltage of 100 mV, but does not provide sufficient light stability.

4 is a circuit diagram of a cell according to an embodiment of the present invention.

Referring to FIG. 4, a cell, which may be referred to as an SRAM cell, a memory cell, a 12T SRAM cell, or the like, may include 12 transistors. In a conventional 10T SRAM cell, only storage nodes node A and node B are connected to a bit line (BL) and a complementary bit line (BLB) through corresponding access transistors, respectively, Node C and node D are isolated from the bit lines BL and BLB. However, a cell according to an embodiment of the present invention includes four access transistors connecting node B and node C to the bit line BL and connecting node A and node D to the complementary bit line BLB. Through this structure, four storage nodes can be accessed in parallel during a write operation.

Specifically, the cell 100 includes a plurality of nodes A, B, C and D, a plurality of load transistors P1, P2, P3 and P4, a plurality of drive transistors N1 N2, N3 and N4 and a plurality of access transistors N5, N6, N7 and N8.

Data may be stored in each of a plurality of nodes A, B, C, and D, each of which may be referred to as storage nodes. For example, when either one of the logic high value ('1') and the logic low value ('0') is stored in the node A and the node D, And a logic low value ('0'). Data stored in each of the plurality of nodes A, B, C, and D is output to the bit line BL or the complementary bit line BLB through the corresponding access transistor, or to the bit line BL or the complementary bit line BL BLB may be stored in each of the plurality of nodes A, B, C, and D through corresponding access transistors.

Each of the plurality of load transistors P1, P2, P3, and P4 may be connected between a corresponding one of the plurality of nodes A, B, C, and D and the power supply line. Specifically, the first load transistor P1 is connected between the node A and the power supply line for supplying the driving voltage VDD, and the second load transistor P3 is connected between the node B and the power supply line , The third load transistor P2 may be connected between the node C and the power supply line, and the fourth load transistor P4 may be connected between the node D and the power supply line.

Further, the gate of each of the plurality of load transistors P1, P2, P3, and P4 may be connected to any one of the plurality of nodes A, B, C, For example, the gate of the first load transistor P1 is connected to the node C, the gate of the second load transistor P3 is connected to the node D, the gate of the third load transistor P2 is connected to the node D, And the gate of the fourth load transistor P4 may be connected to the node C. [

In addition, each of the plurality of load transistors P1, P2, P3, and P4 may be implemented with a first type of transistor, for example, a PMOS transistor. However, the scope of the present invention is not limited to the respective types of the plurality of load transistors P1, P2, P3 and P4, and it is also possible to arrange the plurality of load transistors P1, P2, P3 and P4 May be implemented with a second type of transistor, e.g., an NMOS transistor.

Each of the plurality of drive transistors N1, N2, N3, and N4 may be connected between a corresponding one of the plurality of nodes A, B, C, and D and a ground line. Specifically, the first drive transistor N1 is connected between the node A and the ground line for supplying the ground voltage (GND), the second drive transistor N3 is connected between the node B and the ground line, The three-driver transistor N2 may be connected between the node C and the ground line, and the fourth driver transistor N4 may be connected between the node D and the ground line.

Further, the gate of each of the plurality of drive transistors N1, N2, N3, and N4 may be connected to any one of the plurality of nodes A, B, C, and D. [ For example, the gate of the first drive transistor N1 is connected to the node B, the gate of the second drive transistor N3 is connected to the node A, the gate of the third drive transistor N2 is connected to the node A, And the gate of the fourth drive transistor N4 may be connected to the node B. [

In addition, each of the plurality of drive transistors N1, N2, N3, and N4 may be implemented with a second type of transistor, for example, an NMOS transistor. However, the scope of the present invention is not limited to the type of each of the plurality of drive transistors N1, N2, N3 and N4, and the plurality of drive transistors N1, N2, N3 and N4 May be implemented with a first type of transistor, e.g., a PMOS transistor.

Each of the plurality of access transistors N5, N6, N7, and N8 may be connected between any one of the bit line BL and the complementary bit line BLB and a corresponding one of the plurality of nodes. Specifically, the first access transistor N5 is connected between the node A and the complementary bit line BLB, the second access transistor N6 is connected between the node B and the bit line BL, The node N8 may be connected between the node C and the bit line BL and the fourth access transistor N7 may be connected between the node D and the bit line BL.

Further, the gates of each of the plurality of access transistors N5, N6, N7 and N8 may be connected to a word line (WL).

Further, each of the plurality of access transistors N5, N6, N7, and N8 may be implemented with a second type of transistor, e.g., an NMOS transistor. However, the scope of the present invention is not limited to the type of each of the plurality of access transistors N5, N6, N7, and N8, but may be a plurality of access transistors N5, N6, N7, and N8 May be implemented with a first type of transistor, e.g., a PMOS transistor.

The cell shown in Fig. 4 includes four access transistors, which can cause a problem that the area of the cell or chip can be increased. A detailed description thereof will be given later with reference to Figs. 5A and 5B.

FIG. 5A shows the layout of the SRAM cell shown in FIG. 1, and FIG. 5B shows the layout of the cell shown in FIG. 5A and 5B show only an active layer, a poly layer and a P-well layer.

A first metal layer (metal-1 layer) and a second metal layer (metal-2 layer) were used to wire the transistors in the cell. Also, although there is no known layout for a 10T SRAM cell, the layout shown in Figure 5A can be an optimal layout in cell area. Compared with the layout of a 6T SRAM cell, the layout of a 10T SRAM cell under a logic design rule of the 28nm FD-SOI (Fully Depleted Silicon On Insulator) technique has a cell area 2.1 times larger. However, it can be seen that the SRAM cell according to an embodiment of the present invention has a cell region having the same size as the 10T SRAM cell. This is because the load transistor N7 and the load transistor N8 can be arranged in the blank space of the 10T SRAM cell.

Figs. 6A and 6B are diagrams for explaining a write operation of the cell shown in Fig. 4, in which Fig. 6A shows the current flow and Fig. 6B shows the voltage waveform resulting from the simulation. At this time, the simulation of FIG. 6B was performed under a certain condition (VDD = 1V, SS corner, 0 ° C).

Consider a case where '0' is stored in node A and node D, and '1' is stored in node B and node C, and data contrary to the current data is stored. During the write operation, the bit line BL and the complementary bit line BLB are supplied with 0V and the driving voltage VDD, respectively. At this time, the node B and the node C are pulled down by the access transistor N6 and the access transistor N8. At the same time, the access transistor N5 and the access transistor N7 pull the node A and the node B pull-up. Unlike the conventional 10T SRAM cell, according to the present invention, all the storage nodes A, B, C, and D can be biased to represent write data, thereby providing good writeability.

In FIG. 2B, the potential of the node A does not reach the VDD due to the weak pull-up operation of the NMOS, and the write operation performance of the 10T SRAM cell is poor. However, in accordance with the present invention, when word line WL is enabled, node C is pulled down by access transistor N8. At this time, because the node C is pulled-down, the load transistor P1 is turned on and the voltage of the node A can be strongly pulled up to VDD due to the turn-on of the load transistor P1. This positive feedback can further improve the write performance of the memory cell according to an embodiment of the present invention.

The inventor of the present invention conducted a 1000 MC simulation on three SRAM cells (6T SRAM cell, 10T SRAM cell, and SRAM cell according to the present invention) in order to compare writability. In a simulation, all SRAMs have the same sizing approach, i.e., full-up PMOS and access transistors have a minimum geometry size, and full-down NMOS transistors have a width (width) is 1.5x times larger than that in the case of the first embodiment, the simulation is performed under a certain condition (SS conrner, 0 ° C). Also, the MC simulation was performed at a nominal driving voltage (VDD) of 1 V with a 2 GHz access rate.

Referring to FIG. 7, which illustrates the write performance simulation results for each of these cells, a significant write failure is shown for a 10T cell. This result is lower than the simulation result shown in FIG. 3, which can be attributed to a tendency that the write failure probability of the SRAM cell increases as the access rate increases. On the other hand, the write failure does not occur in the 6T SRAM cell and the SRAM cell according to the present invention.

Simulation results when driving voltage (VDD) is lowered to 0.6V provides a more accurate write performance comparison of the three SRAM cells. The simulation was performed at two access rates (200 MHz and 333 MHz). The scenario where the access rate is 333 MHz is the worst scenario in terms of write failure probability.

Referring again to FIG. 7, in a simulation at a low access rate (i.e., an access rate of 200 MHz), a 10T SRAM cell exhibits a very high write failure probability, whereas a 6T SRAM cell and an SRAM cell according to the present invention exhibit a write failure Is not generated. In simulations at an access rate of 333 MHz, very few write failures occurred in both the 6T SRAM cell and the SRAM cell according to the present invention. By simulation, it can be seen that the SRAM cell according to the present invention provides significantly improved write performance compared to a 10T SRAM cell, especially at low drive voltages. The write performance of the SRAM cell according to the present invention is comparable to the write performance of the 6T SRAM cell.

In SRAM, read failure can be classified into two mechanisms: data flipping and read accessing failure due to a lack of read static noise margin (SNM).

When the word line WL is activated for the read operation, the storage nodes of the SRAM cell are accessed by the bit lines BL and BLB. Since the two bit lines BL and BLB are initially pre-charged to VDD, the bit line access can increase the potential of the node and reduce the SNM. This disturbance may cause flipping of cell data when the SNM has a negative value.

The inventors of the present invention compared the probability that the lead SNM will have a negative value for each of the three SRAM cells, that is, the 6T SRAM cell, the 10T SRAM cell, and the SRAM cell according to the present invention.

Under the same conditions as the simulations of Fig. 7, 1000 MC simulations were performed on each VDD. Simulations were performed down to VDD of 0.6V by decreasing by 50mV from VDD of 0.8V. In each VDD, the result of counting the number of cells having a negative read SNM is shown in FIG.

As shown in Fig. 8, neither the 10T SRAM cell up to 0.65V nor the SRAM cell according to the present invention had negative read SNM. However, in the case of a 6T SRAM cell, a large number of cells having a negative read SNM from 0.7V were found. This means that the 10T SRAM cell and the SRAM cell according to the present invention provide improved read stability compared to the 6T SRAM cell. At VDD of 0.6V, more negative lead SNMs were found in SRAM cells according to the present invention than in 10T SRAM cells. In the case of a 10T SRAM cell, it is understood that the effect of bit line access was less due to isolation (isolation) of the two storage nodes during the read operation. However, in the case of the SRAM cell according to the present invention, since all the storage nodes are influenced by the bit line access, it can be considered that the lead SNM deteriorates. In SRAM, lead SNM and writeability tend to have conflicting design requirements, so these factors must be considered simultaneously. As described above, the 10T SRAM cell does not provide sufficient light stability for the process variation of the 28nm FDSOI technique, whereas the SRAM cell according to the present invention shows high reliability for both read SNM and write stability.

Three SRAM cells (a 6T SRAM cell, a 10T SRAM cell, and an SRAM cell according to an embodiment of the present invention) in terms of read accessing stability are as follows.

First, the read access in the SRAM will be described. For a read operation, the two bit lines of the SRAM need to be pre-charged to VDD. A word line is then activated which electrically connects the bit lines to the storage nodes of the selected SRAM cell through the access transistors. At this time, the bit line connected to the storage node storing the data '0' is more dis-charged than the non-charged bit line, which causes a potential swing between the two bit lines . After the bit line swing is fully developed, a sense-amplifier is activated, and the sense-amplifier senses and stores the cell data.

It should be noted here that there is a close relationship between the time required to generate a sufficient bit line swing and the read access stability of the SRAM. This is because the smaller the required time, the larger the timing margin for the read access can be secured. Since a bit line swing of at least 100 mV is required for reliable sensing, the time required to achieve a bit line swing of 100 mV for each of the above three SRAM cells will be compared. The simulation was performed at the process corners of SS (slow NMOS and slow PMOS), FF (fast NMOS and fast PMOS) and typical NMOS and typical PMOS (TT) process cores.

Ideally, only the bit line connected to the node storing data '0' is discharged and the other bit line maintains its original potential. However, practically, bit-line leakage noise tends to increase the time for the bit line swing to evolve by discharging two bit lines. Therefore, the worst temperature corner of 85 DEG C was applied in connection with the bit line leakage noise. A study of prior researchers (Kenichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, and Tadahiro Kuroda, A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs, IEEE Journal of Solid State Circulation, vol. 36, no. , 2001), the intensity of the bit line leakage noise depends on the data pattern of the SRAM cell on the column sharing the bit line. In this simulation, we assumed the worst data pattern as in the case of currently accessed SRAM cells with data contrary to other SRAM cells on the same column.

9 is a graph showing the comparison result of the development time of the bit line swing. 6T SRAM cells and 10T SRAM cells have similar development times at all corners. Compared with the 6T SRAM cell and the 10T SRAM cell, the SRAM cell according to the present invention shows a development time of at least 27% smaller. Simulation results show that the SRAM cell according to the present invention has improved read access stability. With respect to the read access mechanism of the SRAM cell, there are three bit lines, including discharging on-current, bit-line leakage noise and bit-line capacitance. It can be inferred that this is the main determinant of the line swing deployment time. Here, the bit line capacitance is caused by the parasitic junction capacitance of the access transistors and the metal capacitance. The SRAM cell according to the present invention includes four access transistors, which are twice as large as the 6T SRAM cell and the 10T SRAM cell, so that the bit line capacitance can be increased. However, the metal layer capacitances of the three SRAM cells described above are almost the same. Therefore, in the case of the post-layout model according to the present invention, the SRAM cell according to the present invention has a bit line capacitance which is approximately 1.3 times larger than other SRAM cells. On the other hand, as the number of access transistors doubles, dischaging on-current also doubles, which is a reason why the bit line development time of the SRAM cell according to the present invention is remarkably improved. An increase in the number of access transistors can cause greater bit line leakage noise and can have some adverse effects on the bit line deployment time. However, the dischaging on-current at the nominal drive voltage (nominal VDD) is very large compared to the bit line leakage noise, which has a limited impact due to the increased bit line leakage noise.

Hereinafter, soft-error resilience will be described.

SET noise can be simulated by adding and temporarily activating an independent current source to the memory node. The exponential current power source proposed in Robert C. Baumann's "Radiation-induced soft errors in advanced semiconductor technologies" (IEEE Trans. On Devi., And Mate Reli., Vol 5, no. A simulation scenario borrowing from an exponential current source model is shown in FIG. During a read operation or a write operation, the memory nodes (or storage nodes) are electrically connected to the bit line capacitance and are therefore less susceptible to soft errors. Therefore, consider a hold mode in which a low VDD (i.e., a VDD of 0.6V) is applied to deactivate the word line and reduce the leakage current.

First, an exponential current source is applied to the node that is most sensitive to soft errors. The reason for considering node A as the most sensitive node is as follows. The SET noise that occurs at node B and node D weakens pull-down of N1 and N4 or pull-up of P2 and P3, but does not directly cause flipping of cell data. On the other hand, SET noise applied to nodes A and D temporarily turns on transistors with node A and node D as gate inputs, causing a data flip. In SRAM cells, node A is more sensitive to soft errors than node C because the full-down NMOS transistors have a wider width than the full-up PMOS transistors.

10, the peak current (I _peak ) of the current source was increased and the maximum value at which no data flip occurred was observed, and the simulation was performed in all process corners of the SRAM cell according to the present invention. In addition, the same simulation was performed for a 6T SRAM cell and a 10T SRAM cell, and the simulation result is shown in FIG. Here, FS and SF are abbreviated as fast NMOS and slow PMOS, and slow NMOS and fast PMOS, respectively. Referring to FIG. 11, the SRAM cell according to the present invention has almost the same soft error tolerance as the 10T SRAM cell.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (12)

delete delete delete delete delete delete delete delete delete delete A first PMOS transistor connected between the first storage node and the power supply line;
A second PMOS transistor connected between the second storage node and the power supply line;
A third PMOS transistor connected between the third storage node and the power supply line;
A fourth PMOS transistor connected between the fourth storage node and the power supply line;
A first NMOS transistor connected between the first storage node and a ground line;
A second NMOS transistor connected between the second storage node and the ground line;
A third NMOS transistor connected between the third storage node and the ground line;
A fourth NMOS transistor connected between the fourth storage node and the ground line;
A fifth NMOS transistor connected between the complementary bit line and the first storage node;
A sixth NMOS transistor connected between the bit line and the second storage node;
A seventh NMOS transistor connected between the bit line and the third storage node; And
And an eighth NMOS transistor connected between the complementary bit line and the fourth storage node,
A gate of the first PMOS transistor is connected to the third storage node,
A gate of the second PMOS transistor is connected to the fourth storage node,
A gate of the third PMOS transistor is connected to the fourth storage node,
A gate of the fourth PMOS transistor is connected to the third storage node,
A gate of the first NMOS transistor is connected to the second storage node,
A gate of the second NMOS transistor is connected to the first storage node,
A gate of the third NMOS transistor is connected to the first storage node,
A gate of the fourth NMOS transistor is connected to the second storage node,
And the gates of the fifth to eighth NMOS transistors are connected to a word line,
Memory cell.
12. The method of claim 11,
Wherein the memory cell is an SRAM cell.

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