CN113591424A - Circuit signal offset adjusting device and adjusting method - Google Patents

Abstract

The invention provides an adjusting device and an adjusting method for circuit signal offset. The circuit signal offset adjusting method comprises the following steps: providing a controller to perform: partitioning the circuit according to a network link table of the circuit based on each of a plurality of clock signals to generate a plurality of circuit partitions; performing clustering actions respectively aiming at the circuit partitions to obtain a plurality of circuit clusters; identifying adjacent states of layout positions for the circuit groupings; and adjusting the offset value of each circuit group according to the adjacent state.

Description

Circuit signal offset adjusting device and adjusting method

Technical Field

The present invention relates to an adjusting apparatus and an adjusting method for circuit signal skew (skew), and more particularly, to an adjusting apparatus and an adjusting method for circuit signal skew analyzed according to a clock tree (clock tree).

Background

In the field of circuit design, a large number of registers may occur during operation, and a transition phenomenon occurs at the same time, which results in a situation where the operating voltage is momentarily greatly pumped, causing a voltage drop. To avoid this, it is necessary to perform appropriate offset value (skew) adjustment in the circuit.

In the prior art, designers need to consider various factors of a circuit, such as the architecture of a clock signal, the power consumption of the circuit, and the layout position of a physical element, so as to effectively perform an offset value adjustment operation. This is when the circuit architecture is more and more complex today, which makes the analysis of the circuit useless.

In addition, in the prior art, designers often only consider the number of buffers in the circuit, and thus the circuit benefit that can be improved by the adjustment operation of the offset value is limited.

Disclosure of Invention

The invention aims at a device and a method for adjusting circuit signal offset, which can simply adjust the signal offset in a circuit and improve the performance quality of the circuit.

According to the embodiment of the invention, the method for adjusting the circuit signal offset comprises the following steps: providing a controller to perform: partitioning the circuit according to a network link table of the circuit based on each of a plurality of clock signals to generate a plurality of circuit partitions; performing clustering actions respectively aiming at the circuit partitions to obtain a plurality of circuit clusters; identifying adjacent states of layout positions for the circuit groupings; and adjusting the offset value of each circuit group according to the adjacent state.

According to an embodiment of the present invention, an apparatus for adjusting a circuit signal offset includes a controller and a storage element. The controller is coupled to the storage element and is used for executing the adjustment method of the circuit signal offset.

In view of the above, the present invention divides a circuit and performs grouping, recognizes an adjacent state of a layout position of the circuit grouping, and performs an adjustment operation of an offset value of each circuit grouping according to the adjacent state of the circuit grouping. The adjustment of the circuit signal offset can be simplified. The circuit offset is adjusted on the premise of considering both the signal quality and the design time.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a flowchart illustrating a method for adjusting a circuit signal offset according to an embodiment of the present invention;

FIG. 2, FIG. 3A and FIG. 3B are schematic diagrams illustrating a circuit partition generation method according to an embodiment of the present invention;

FIG. 4 and FIGS. 5A-5B are schematic diagrams of the clustering operation of circuit partitions according to the embodiment of the present invention;

FIG. 6 is a diagram illustrating an operation of recognizing an adjacent state of layout positions of circuit groups according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating an exemplary adjustment of offset values for circuit clustering;

FIG. 8 is a schematic diagram of a current-time table of an embodiment of the present invention;

fig. 9 is a schematic diagram of an apparatus for adjusting circuit signal offset according to an embodiment of the invention.

Description of the reference numerals

200: a circuit;

610: circuit layout;

810: an ammeter;

820: a time axis;

830: the sum of the currents;

900: an adjustment device;

910: a controller;

920: a storage element;

A. b, C, D: a branch port;

A1-A3, B1, B: a sub-branch port;

BT: an upper layer block;

CLI: delay information;

CLK: a clock signal;

CM, CM 1-CMN: a value matrix;

CRA 1-CRA 3, CRB1, CRB2, CRC: a circuit;

G1C-G4C: the distribution range;

G1C1, G1C 2: a sub-distribution range;

GA. GB, GC, G1-G4: grouping the circuits;

PI: power supply information;

PT1, PT2, PTA: partitioning a tree;

RG 1-RG 4, RG1a, RG2 a: a buffer;

SNA, SNB, SNC, SNA 1-SNA 3, SNB1, SNB 2: a branch node;

s110 to S140: adjusting circuit signal deviation;

s310 to S314: establishing a partition tree;

s410 to S4110: a clustering action step of circuit partitions;

s710 to S790: adjusting the offset value;

SB1, SB 2: a lower layer block.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for adjusting a circuit signal offset according to an embodiment of the invention. The operation flow of the embodiment of the present invention may be performed for a network link table (netlist) of a circuit. In step S110, the circuit is divided according to the network link table of the circuit based on each of the plurality of clock signals in the circuit to generate a plurality of circuit partitions. In step S110, a plurality of circuit partitions generated by dividing the circuit may generate corresponding partition trees (partition trees). A partition tree may be used to represent the architecture of the corresponding circuit partition.

In step S120, clustering is performed on each circuit partition to obtain a plurality of circuit clusters, so that the size of the partition tree of each circuit partition can be reduced and the complexity of calculation can be reduced.

Next, in step S130, the adjacent state of the physical layout position of the circuit group in the circuit is identified, and in step S140, the offset value is adjusted for each circuit group according to the adjacent state.

In the embodiment of the present invention, the circuit dividing operation in step S110 is performed from the upper layer to the lower layer (top-down) according to the network link table of the circuit. In step S120, the clustering operation for the circuit partitions is performed from the lower layer to the upper layer (bottom-up). It should be noted that the present invention can effectively simplify the complexity of the offset analysis by aiming at the partitioning and clustering operations of the circuit, and perform the adjustment operation of the offset value of the circuit in accordance with the adjacent state of the circuit cluster. The analysis speed of circuit deviation can be improved on the premise of considering circuit representation degree.

Referring to fig. 2, fig. 3A and fig. 3B, fig. 2, fig. 3A and fig. 3B are schematic diagrams illustrating a circuit partition generation method according to an embodiment of the invention. In fig. 2, the circuit 200 is a portion of a complete circuit. The circuit 200 has an upper block BT including lower blocks SB1 and SB 2. The circuit 200 operates based on a clock signal CLK. Based on the clock signal CLK to track the circuit 200, branch ports A and B are available at the lower block SB 1. From branch A, tracking in the direction of lower layer block SB2, branch ports C and D are obtained.

Fig. 3A shows a partition tree PT1 generated in response to the circuit trace operation described above. The flow of actions to build the partition tree PT1 is shown in fig. 3B. In an initial state of circuit tracing, a root node RN of the partition tree PT1 may be generated. Next, in fig. 3B, when each branch port is found, step S310 is executed to determine whether the number of control registers on each branch port or the power consumption of the control registers is less than a predetermined threshold. When the number of control registers on the branch port or the power consumption of the control registers is smaller than a predetermined threshold, the trace of the path is terminated (step S320). On the contrary, when the number of the control registers on the branch port or the power consumption of the control registers is not less than the predetermined threshold, the corresponding branch port is tracked (step S311). Then, step S312 establishes a branch node corresponding to each branch port in the partition tree. And in step S313, a connection is made with the branch node as a child (child) branch node. And the generation operation of each circuit partition is completed in step S314.

For example, according to the circuit 200 of FIG. 2, in FIG. 3A, when circuit trace finds branch ports A and B, branch nodes SN11 and SN21 are established according to branch ports A and B, respectively. And connects the branch nodes SN11 and SN21 to the root node RN. The branch nodes SN11 and SN21 may be child branch nodes of the root node RN, and the opposite root node RN is parent node of the branch nodes SN11 and SN 21. Here, the number of control registers or power consumption of the control registers of the branch ports a and B is determined, for example, if the number of control registers or power consumption of the control registers of the branch ports B is less than a threshold, tracking for the circuits downstream of the branch port B may be terminated. If the number of control registers of branch port a or the power consumption of the control registers is not less than a threshold, tracking is performed for the circuits downstream of branch port a, and branch ports C and D of lower block SB2 are obtained. Corresponding to branch ports C and D, branch nodes SN12 and SN22 can be established, respectively.

If the number of the control registers of the branch ports C and D or the power consumption of the control registers are smaller than the threshold, the tracking operation of the circuit 200 may be terminated. The circuit division operation can be completed at the same time as the tracking operation of the circuit 200 is completed. The building of partition tree PT1 for circuit 200 may also be completed.

Please refer to fig. 4 and fig. 5A to 5B. Fig. 4 and fig. 5A to 5B are schematic diagrams illustrating a clustering operation of circuit partitions according to an embodiment of the present invention. Fig. 4 is a flowchart of the clustering operation for the circuit partition. In step S410, the deepest level D is obtained for each partition tree of the circuit partitions, and in step S420, the current level is set to level i, where i is D-1. That is, the current level (level i) is a level higher than the deepest level D.

Next, in step S430, the branch node corresponding to the deepest level D in the level i is taken as the child branch node, and the parent branch node corresponding to the child branch node in the level i is taken.

It should be noted that, in the partition tree of each circuit partition, the branch node has a plurality of values, wherein the plurality of values respectively represent the number of buffers or the power consumption corresponding to the branch node.

In step S440, a temporary field p is established, wherein the temporary field p has a capacity value. Step S440 determines the sub-branch node k with the largest value among the sub-branch nodes, and moves the sub-branch node k to the temporary storage field p. In addition, the capacity value of the temporary storage field p is subtracted from the value of the sub branch node k, and the remaining capacity value of the temporary storage field p is obtained.

In step S450, another sub-branch node c that is not clustered is taken from the plurality of branch nodes. Step S460 determines whether the remaining capacity of the temporary storage field p is greater than the value of the sub branch node c, so as to determine whether the remaining capacity of the temporary storage field p is insufficient. If the remaining capacity of the temporary field p is insufficient, another temporary field p 'is created, the sub-branch node c is placed in the temporary field p' (step S4120), and step S480 is executed again. On the contrary, if the remaining capacity of the temporary field p is sufficient, the sub-branch node c is moved to the temporary field p, and the remaining capacity of the temporary field p is calculated again (step S470).

In step S480, it is determined whether there is any unclustered child branch node in the hierarchy D. If there are no sub-branch nodes that have not been clustered, steps S450 to S470 are repeated until all the sub-branch nodes in level D have been clustered. Step S490 is then performed.

In step S490, it is determined whether there is another parent branch node in the current level i. If there are other parent branch nodes, step S430 is executed again to perform clustering operation on the child branch nodes of another parent branch node. On the other hand, if there is no other parent branch node, i is decremented by 1 (step S4100).

In step S4110, it is determined whether i is equal to 0, and when i is equal to 0, the clustering operation of the circuit partition is ended. If i is not equal to 0, step S480 is executed again. When i is 0, all the hierarchical branch nodes complete the clustering operation.

In the exemplary embodiment of fig. 5A-5B, circuit partition Z1 includes port T and sub-circuit partitions SZ1 SZ 3. Port T receives a clock signal CLK. The circuit partition SZ1 includes a branch port A and sub-branch ports A1-A3. The sub-branch ports a 1-A3 correspond to the connection circuits CRA 1-CRA 3, respectively, and the circuits CRA 1-CRA 3 have the same or different magnitudes of control buffer amount or control buffer power consumption, respectively. The circuit partition SZ3 includes a branch port B and sub-branch ports B1 and B2. The sub-branch ports B1 and B3 are respectively connected to the circuits CRB1 and CRB2, and the circuits CRB1 and CRB2 respectively have control buffer amounts or control buffer power consumption with different magnitudes. The circuit partition SZ2 includes a branch port C. The branch port C corresponds to the connection circuit CRC.

In the embodiment of the present invention, the partition tree PTA can be established according to the circuit partition Z1. The partition tree PTA has a plurality of branch nodes SNA, SNB, SNC, SNA1 to SNA3, SNB1, and SNB 2. The branch nodes SNA, SNB, SNC, SNA1 to SNA3, SNB1, and SNB2 correspond to the branch port A, B, C and the sub-branch ports a1 to A3, B1, and B2, respectively. In the partition tree PTA, a plurality of values are recorded in the branch nodes SNC, SNA1 to SNA3, SNB1, and SNB2 at the bottom, respectively, and in the present embodiment, the values recorded in the branch nodes SNC, SNA1 to SNA3, SNB1, and SNB2 are 4, 2, 1, 5, and 2, respectively. The values recorded by the branch nodes SNC, SNA 1-SNA 3, SNB1 and SNB2 respectively represent the number of control buffers connected to the corresponding branch ports or the amount of power consumption of the control buffers. Taking the number of control registers as an example, a value of 4 recorded by the branch node SNA1 may indicate that the sub-branch port A1 is connected to 4000 control registers.

Then, through a partitioning algorithm (partitioning algorithm), a clustering action may be performed on the partition tree PTA, and a plurality of circuit clusters G1-G4 are generated. The clustering operation of the present embodiment can be adjusted based on the uniformity of the total of the plurality of cluster values in the circuit clusters G1-G4. The so-called clustering value summation is a summation of values recorded in all branch nodes included in each circuit cluster. Taking circuit subgroup G1 as an example, the total of the values of circuit subgroup G1 may be equal to the sum of the values of branch nodes SNB1, SNB2, SNC (2 +5+ 4-11). The uniformity of the total of the plurality of clustering values can be obtained by the standard deviation of the total of the plurality of clustering values. In the present embodiment, the clustering operation of the segmentation algorithm may be performed in such a manner that the standard deviation of the sum of the plurality of clustering values is minimized.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating an operation of recognizing an adjacent state of layout positions of circuit groups according to an embodiment of the present invention. After the clustering of the plurality of circuit clusters in the circuit is completed, the physical layout positions of the plurality of registers in the circuit clusters in the circuit can be analyzed.

In fig. 6, the circuit layout 610 includes a plurality of buffers RG1 to RG4, RG1a, and RG2 a. The buffers RG1 and RG1a belong to the same first circuit group; the buffers RG2, RG2a belong to the same second circuit group; the buffer RG3 belongs to the same third circuit group; the buffer RG4 belongs to the same fourth circuit group. In the case of the identification of adjacent states of the layout positions of the circuit groups, the circuit layout 610 may be analyzed by a clustering analysis (clustering analysis) algorithm known to those skilled in the art, for example, a K-average algorithm or a Density-based spatial clustering algorithm (dbsca), or other clustering analysis algorithms, and distribution ranges G1C to G4C of a plurality of groups may be generated, and the adjacent states may be established according to the distances between the distribution ranges G1C to G4C.

It is noted that the distribution ranges G1C G4C correspond to the first circuit grouping to the fourth circuit grouping, respectively. The distribution ranges G1C-G4C do not necessarily include all of the buffers of the corresponding circuit grouping. Taking the registers RG1a and RG2a as examples, since the registers RG1a and RG2a are far away from the other registers RG1 and RG2 of the same circuit group, the registers RG1a and RG2a are excluded during the clustering operation. In addition, the distribution ranges G1C-G4C may overlap each other and are not necessarily isolated from each other. And the distribution range of the same cluster may be distributed in two separate regions, for example, the distribution range G1C is composed of sub-distribution ranges G1C1 and G1C2, and the sub-distribution ranges G1C1 and G1C2 are separated from each other.

Referring to fig. 7 and 8, the adjustment operation of the offset value of each circuit group is shown. FIG. 7 is a flowchart illustrating an operation of adjusting offset values of circuit groups according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a current-time table according to an embodiment of the present invention.

In fig. 7, in step S710, the maximum offset (i) that can be adjusted by the circuit cluster (i) is found by receiving each circuit cluster (i) that has completed the clustering operation. In step S720, a current waveform analysis is performed for each circuit group (i), and each circuit-time table (i) is obtained. In step S720, the current waveform of each circuit group (i) is analyzed by the delay information CLI of the clock signal and the power supply information PI. The delay information CLI records the delay state of the clock signal during the circuit operation, and the power information PI records the power consumption state of the circuit during the circuit operation. And the resulting current-time table is shown in fig. 8. Ammeter 810, in which the first row records the current state distribution over time; the second row is a time axis 820 corresponding to the delay of the clock signal, wherein the time axis 820 is divided into a plurality of time intervals 0 to 6; the third row is a plurality of current sums 830 corresponding to time intervals 0 through 6.

In step S730, the panning operation of each circuit-schedule (i) is performed according to a plurality of reference offset values sk smaller than the maximum offset (i). Step S740 is to shift the circuit-time tables (i) corresponding to the respective circuit groups (i) based on the plurality of reference offset values sk, to compare the shifted circuit-time tables (i) with each other in an overlapping manner, and to generate a sum of currents between any two circuit groups at different reference offset values in step S750. In step S760, a bid matrix CM is established according to the calculated sum of the currents. The cost matrix CM may be established according to the reference offset sk, that is, the number of the cost matrices CM is the same as the number of the set reference offset sk.

Additionally, when the relationship between the current summation values of any two circuit groups is generated, the current summation values can be properly adjusted according to the adjacent states of the circuit groups. Briefly, when two circuit groups have a relatively high degree of adjacency (the distance between each other is smaller than a first threshold), the corresponding current summation value can be adjusted higher. Conversely, when there is a relatively low degree of adjacency between two circuit groups (the distance between them is greater than a second threshold), there is no need to adjust the corresponding current summation values. The second threshold value may be greater than or equal to the first threshold value.

In fig. 7, a single cost matrix (e.g., the cost matrix CM1) may correspond to one of the plurality of reference offset values sk. The cost matrix CM1 records the sum of the currents corresponding to any two of the plurality of circuit groups GA to GF. The sum of the currents corresponding to GA and GB in the circuit group is denoted as Cost (a, B), and the rest can be analogized in this manner.

In step S770, the sum of the currents corresponding to the respective circuit groups is added to all of the cost matrices CM1 to CMN, and the total sum corresponding to the respective circuit groups is obtained. Taking the circuit cluster GA as an example, the sum of the total sum of the currents in the corresponding circuit cluster GA is equal to the sum of the total currents from Cost (A, B) to Cost (A, F) in all of the Cost matrices CM 1-CMN. The sum of the total area of the corresponding circuit groups GC is equal to the sum of the current sums Cost (C, A) to Cost (C, F) in all of the Cost matrices CM 1-CMN. Then, the priority of the adjustment of the offset values of the circuit groups GA-GF is set according to the size of the total sum corresponding to the circuit groups GA-GF. In the present embodiment, the priority of the adjustment of the offset values of the circuit groups GA to GF is positively correlated to the size of the total sum corresponding to the circuit groups GA to GF. That is, if the circuit cluster GA has the largest total sum, the circuit cluster GA has the highest priority.

Step S780 sorts each circuit group GA to GF according to the priorities obtained in step S770. In step S790, a plurality of section sums of the current summation values of the circuit groups GA to GF are calculated for each reference offset value sk based on the priority. In detail, the so-called partition sum is the sum of all the current sums Cost (a, B) to Cost (a, F) in the rows of each circuit cluster (taking circuit cluster GA as an example) in a single Cost matrix (e.g., Cost matrix CM 1). That is, different partition sums can be calculated for the circuit groups GA based on different cost matrices CM1 to CMN. Then, the offset value of the circuit group GA is adjusted according to the reference offset value corresponding to the smallest of all the partition sums. For example, if the partition sum of the circuit groups GA in the cost matrix CM1 is minimum and the cost matrix CM1 corresponds to the offset sk1, the offset adjustment of the circuit groups GA is performed according to the offset sk 1.

Referring to fig. 9, fig. 9 is a schematic diagram of an apparatus for adjusting circuit signal offset according to an embodiment of the invention. The circuit signal offset adjustment apparatus 900 includes a controller 910 and a storage element 920. The controller 910 is coupled to the storage element 920 for receiving the network link table of the circuit. The controller 910 is also used to execute the adjustment method of circuit signal offset of the embodiments as described above, and adjust the offset value for each circuit group by adding a delay element for each circuit group in the network link table of the circuit.

In the physical circuit, the delay element added by the controller 910 can generate the adjusted netlist according to the adjustment of the offset value of the circuit grouping, and the performance of the generated integrated circuit can meet the design expectation by adjusting the layout of the physical circuit.

Incidentally, in the present embodiment, the controller 910 may be a processor with computing capability. Alternatively, the controller 910 may be a Hardware Circuit designed by Hardware Description Language (HDL) or any other digital Circuit design known to those skilled in the art, and implemented by Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD) or Application-specific Integrated Circuit (ASIC). In addition, the memory device 920 can be any type of storage medium such as Random Access Memory (RAM), flash memory (flash), etc., but not limited thereto.

In summary, the present invention divides the circuit to generate a plurality of circuit partitions, and clusters the circuit partitions to simplify the circuit architecture. The present invention analyzes the adjacent state of the layout positions of the circuit groups to perform the adjustment operation of the offset value for each circuit group. Under the circuit-based expression, the time length of the analysis action can be effectively reduced, and the efficiency of the offset value adjustment action is improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. A method for adjusting a signal offset of a circuit, comprising:

providing a controller to perform:

partitioning a circuit according to a network link table of the circuit based on each of a plurality of clock signals to generate a plurality of circuit partitions;

performing a clustering action on the plurality of circuit partitions respectively to obtain a plurality of circuit clusters;

identifying neighboring states of layout positions for the plurality of circuit clusters; and

adjusting an offset value for each of the plurality of circuit groups according to the neighboring state.

2. The method of claim 1, wherein the circuit is partitioned to generate the plurality of circuit partitions according to a clock signal network of a network link table of the circuit.

3. The method of claim 1, wherein the step of partitioning the circuit according to the network link table of the circuit to generate the plurality of circuit partitions comprises:

tracking each of the plurality of clock signals to find a plurality of branch ports, and establishing a plurality of branch nodes of the corresponding circuit partition according to the number of control registers of the plurality of branch ports or the power consumption of the control registers.

4. The method as claimed in claim 3, wherein the step of establishing the branch nodes of the corresponding circuit partition according to the number of control registers of the branch ports or the power consumption of the control registers comprises:

comparing the number of the control buffers of the first branch port or the power consumption of the control buffers with a preset critical value; and

and when the quantity of the control buffers of the first branch port or the power consumption of the control buffers is larger than the critical value, establishing a first branch node corresponding to the first branch port.

5. The adjustment method according to claim 4, further comprising:

tracking at least one second branch port corresponding to the first branch port;

and comparing the number of the control buffers of the at least one second branch port or the power consumption of the control buffers with the preset critical value, and establishing at least one second branch node corresponding to the at least one second branch port when the number of the control buffers of the at least one second branch port or the power consumption of the control buffers is larger than the critical value.

6. The adjustment method according to claim 1, wherein the step of performing a clustering action on the plurality of circuit partitions to obtain the plurality of circuit clusters respectively comprises:

establishing a corresponding partition tree for each of the plurality of circuit partitions, the partition tree having a plurality of branch nodes, a plurality of bottom branch nodes in the plurality of branch nodes respectively recording a plurality of values, each of the plurality of values representing the number of control buffers or the power consumption of the control buffer corresponding to each of the plurality of branch nodes; and

clustering the branch nodes based on a uniformity of a plurality of clustering value sums of the circuit clusters according to a segmentation algorithm.

7. The method as claimed in claim 6, wherein the uniformity of the aggregation of the plurality of the clustering values is obtained according to a standard deviation of the aggregation of the plurality of the clustering values.

8. The adjustment method according to claim 1, wherein the step of identifying the adjacent state of the layout positions for the plurality of circuit groups comprises:

establishing a plurality of physical layout positions of a plurality of buffers corresponding to the plurality of circuit groups in the circuit; and

executing a clustering analysis algorithm to generate a plurality of clusters according to the plurality of entity layout positions; and

and establishing the adjacent state according to the distribution range of each of the plurality of clusters.

9. The adjusting method of claim 8, wherein the adjusting the offset value for each of the plurality of circuit groups according to the neighboring state comprises:

calculating a plurality of maximum possible offset values for the plurality of circuit groups, respectively;

establishing a plurality of current-time tables according to the delay information and the power supply information of the plurality of clock signals;

based on the adjacent state, establishing a plurality of cost matrixes respectively corresponding to a plurality of reference offset values according to the maximum possible offset values and the current-time tables; and

determining an adjustment value for the offset value of each of the plurality of circuit groups according to the plurality of cost matrices.

10. The adjusting method of claim 9, wherein the plurality of cost matrices respectively correspond to the plurality of adjustment reference values, and each of the plurality of cost matrices records any two of the plurality of circuit groups corresponding to the sum of the currents generated by each of the plurality of reference offset values.

11. The adjusting method according to claim 9, wherein the step of establishing a plurality of cost matrices respectively corresponding to the plurality of reference offset values according to the plurality of maximum possible offset values and the plurality of current-time tables comprises:

shifting and comparing the current-time tables according to any two of the current-time tables of the circuit groups according to the reference offset values to generate a plurality of current summation values; and

adjusting the plurality of current summation values according to the adjacent states.

12. The adjustment method of claim 8, wherein determining the adjustment value for the offset value of each of the plurality of circuit clusters according to the cost matrices comprises:

adding the sum of the currents respectively corresponding to the plurality of circuit groups in the plurality of cost matrices to obtain a plurality of total sums respectively corresponding to the plurality of circuit groups; and

determining the priority of the adjustment action of the offset values of the plurality of circuit groups according to the magnitude of the sum of the plurality of currents.

13. The method of claim 12, wherein determining the adjustment value for the offset value of each of the plurality of circuit clusters based on the cost matrices further comprises:

calculating a plurality of divisional sums of a current summation value for each of the plurality of circuit subgroups, respectively, corresponding to the plurality of reference offset values based on the priority; and

adjusting an offset value of each of the plurality of circuit groups according to a reference offset value corresponding to a lowest of the plurality of partitions and sums.

14. The method of claim 1, wherein the step of adjusting the offset value for each of the plurality of circuit groups according to the neighboring state further comprises:

at least one delay element is added to each of the plurality of circuit groups to adjust the offset value.

15. An apparatus for adjusting a signal offset of a circuit, comprising:

a storage element; and

a controller coupled to the storage element for:

partitioning a circuit according to a network link table of the circuit based on each of a plurality of clock signals to generate a plurality of circuit partitions;

performing a clustering action on the plurality of circuit partitions respectively to obtain a plurality of circuit clusters;

identifying neighboring states of layout positions for the plurality of circuit clusters; and

adjusting an offset value for each of the plurality of circuit groups according to the neighboring state.

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