CN113590400B - Method and equipment for realizing data acquisition through intermediate triggering based on FPGA - Google Patents
Method and equipment for realizing data acquisition through intermediate triggering based on FPGA Download PDFInfo
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Abstract
The application discloses a method and equipment for realizing data acquisition through intermediate triggering based on FPGA, wherein the method comprises the following steps: converting the acquired data into processable data and storing the processable data into a first memory; reading the processable data in the first memory, and writing the read processable data into a second memory; writing a start address corresponding to the processable data in the second memory and a trigger address corresponding to the trigger signal into a third memory based on the trigger of the trigger signal; sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in a fourth memory; and sending the processable data in the fourth memory to an upper computer.
Description
Technical Field
The application relates to the field of data acquisition, in particular to a method and equipment for realizing data acquisition through intermediate triggering based on an FPGA.
Background
Data is the result of facts or observations, which are a logical generalization of objective things. Modern technological research is not separated from data, and a large amount of information can be obtained from data and analysis of the data. Data and information are inseparable, data being an expression of information.
Based on different trigger events, the generated results are different, different information can be obtained by analyzing the pre-cause results of the trigger events, the behavior to be generated can be predicted by analyzing the data, the relation among different objects can be analyzed, the problem of things abnormality can be found out, and the like, so that the society can be continuously developed and improved by acquiring and researching the related data.
In the research of science and technology, there is also trigger based on trigger signal to obtain different scientific research data, and the acquisition of data is crucial to scientific research, and through the data acquisition to the signal, understanding the law of change of data is the thing that technicians are doing always.
Disclosure of Invention
The application provides a method and equipment for realizing data acquisition through intermediate triggering based on an FPGA, and solves the technical problem of how to acquire front and rear data of a trigger signal.
A method for realizing data acquisition through intermediate triggering based on FPGA comprises the following steps:
converting the acquired data into processable data and storing the processable data into a first memory;
reading the processable data in the first memory, and writing the read processable data into a second memory;
writing a start address corresponding to the processable data in the second memory and a trigger address corresponding to the trigger signal into a third memory based on the trigger of the trigger signal;
sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in a fourth memory;
and sending the processable data in the fourth memory to an upper computer.
In one embodiment of the present application, before writing the start address corresponding to the processable data in the second memory and the trigger address corresponding to the trigger signal into the third memory, the method further includes: before the arrival of the trigger signal, the number of the processable data collected before the arrival of the trigger signal and the number of the processable data collected after the arrival of the trigger signal configured by the upper computer are received; setting an address period according to the number of the collected processable data before the trigger signal arrives; and according to the write control instruction of the second memory, the processable data in the first memory are periodically written into the second memory according to the address period.
In an embodiment of the present application, the writing, based on the triggering of the triggering signal, a start address corresponding to the processable data in the second memory and a triggering address corresponding to the triggering signal into the third memory specifically includes: recording the trigger address corresponding to the second memory when the processable data is written in when the trigger signal comes, and stopping writing the processable data continuously in the address period; after the trigger signal comes, according to the number of the collected processable data, continuing to store the processable data in the first memory at the next address of the address period; and after the set collected processable data are collected, storing a starting address and the trigger address corresponding to the processable data in the second memory into the third memory.
In one embodiment of the present application, the sequentially reading the processable data in the second memory according to the start address and the trigger address in the third memory, and storing the read processable data in a fourth memory specifically includes: reading processable data from a next address of the trigger address to a last address in the address cycle; reading processable data from the start address to the trigger address; reading the processable data from the next address to the last address storing the processable data of the address cycle; and restoring the processable data in the second memory read in sequence and sending the data to a fourth memory.
In one embodiment of the present application, status data of the first memory is read; and determining whether to write the processable data in the first memory into a second memory according to the state data of the first memory.
In one embodiment of the present application, the reading the processable data in the first memory and writing the read processable data into the second memory specifically includes: judging whether the state of the first memory is a non-empty state according to the state data of the first memory; if yes, reading the processable data in the first memory; and writing the read processable data into the double-rate synchronous dynamic random access memory.
In one embodiment of the present application, the converting the collected data into processable data and storing the processable data in the first memory specifically includes: converting the acquired data into data to be processed through an analog-to-digital converter; converting the data to be processed into processable data by receiving a double data rate IDDR primitive instruction; storing the processable data to a first memory; the first memory is a first-in first-out buffer.
In one embodiment of the present application, the sending the processable data in the fourth memory to the upper computer specifically includes: performing interface conversion on the fourth memory to convert the fourth memory into a data interface matched with a corresponding controller; and sending the processable data in the fourth memory to the controller, and sending the processable data in the fourth memory to an upper computer through the controller.
In one embodiment of the present application, based on the triggering of the plurality of triggering signals, the start addresses corresponding to the processable data in the plurality of second memories and the triggering addresses corresponding to the plurality of triggering signals are written into the third memory.
An FPGA-based device for implementing data acquisition by intermediate triggering, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
converting the acquired data into processable data and storing the processable data into a first memory;
reading the processable data in the first memory, and writing the read processable data into a second memory;
writing a start address corresponding to the processable data in the second memory and a trigger address corresponding to the trigger signal into a third memory based on the trigger of the trigger signal;
sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in a fourth memory;
and sending the processable data in the fourth memory to an upper computer.
The application provides a method and equipment for realizing data acquisition through intermediate triggering based on FPGA, which at least comprises the following beneficial effects: by the method, data before and after a plurality of trigger signals can be acquired, and a technician can know the change of the signals through observing the data so as to adjust related parameters, so that an experiment achieves an expected effect.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic flow chart of implementing data reading before and after a trigger signal in a Middle-trigger sampling manner according to an embodiment of the present application;
fig. 2 is a schematic diagram of method steps for implementing data acquisition by intermediate triggering based on FPGA according to an embodiment of the present application;
fig. 3 is a schematic diagram of an apparatus for implementing data acquisition by intermediate triggering based on an FPGA according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be clearly and completely described in connection with specific embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The data acquisition card in the quantum chip measurement and control system built by the company researching the quantum equipment is a self-grinding product, and the data acquisition card automatically acquires non-electric quantity or electric quantity signals from analog and digital measured units such as a sensor and other equipment to be measured through data acquisition, and sends the signals to an upper computer for analysis and processing. The data acquisition is that in practical application, the data is stored for a plurality of times by using a mode of triggering Middle-trigger, and then is sent to an upper computer through a PCIE interface, and the upper computer analyzes the data.
The Middle trigger Middle-trigger comprises a front trigger Pre-trigger and a rear trigger Post-trigger, a user can simultaneously acquire M data before the trigger signal and N data after the trigger signal, specific numerical values of M and N are data which the user defines to want to acquire, and the data change before and after the trigger signal can be observed. Pre-trigger is data that is intended to be recorded before the occurrence of a trigger signal; post-trigger is data that is intended to be recorded after the arrival of a trigger signal.
The application is a Data acquisition card realized based on an FPGA, and an FPGA internal module is mainly divided into an ADC acquisition module, a first-in first-out buffer (First Input First Output, FIFO) module, a Double Data Rate (DDR) read/write control module, a DDR-stream interface module and an XDMA module in a stream interface mode.
Fig. 1 is a schematic flow chart of data reading before and after a trigger signal is implemented by a Middle-trigger sampling mode. ADC data is sent to an ADC data acquisition module for analog-to-digital conversion, then the ADC acquisition module sends the data to an acquisition data FIFO module, a DDR write control module reads the data in the acquisition data FIFO module and then writes the data into the DDR, when a trigger signal arrives, a starting address of the stored data and a trigger address corresponding to the trigger signal are stored into a Middle-trigger storage address FIFO module, then the DDR read control module reads the data in the DDR according to the starting address and the trigger address in the Middle-trigger storage address FIFO module in sequence and writes the data into the DDR data storage FIFO module, then the data is transmitted to an XDMA module through a conversion Stream interface, and finally the XDMA module transmits the data to an upper computer. The following is a detailed description.
Fig. 2 is a schematic diagram of steps of a method for implementing data acquisition by intermediate triggering based on an FPGA according to an embodiment of the present application, which may include the following steps:
s101: the collected data is converted into processable data and the processable data is stored to a first memory. The first memory is a first-in first-out buffer FIFO for collecting data.
If data is to be observed, firstly, converting data of a 1G sampling rate ADC chip outside an FPGA into 8-bit data to be processed by an ADC acquisition module in the FPGA, wherein the data to be processed is digital data; because the ADC chip and the FPGA data interface are parallel, IDDR primitives in the FPGA can be adopted to convert data to be processed into processable data, and the processable data is single-edge data which can be processed by the FPGA. The processable data is stored in an acquisition data FIFO.
In one embodiment of the present application, converting the collected data into processable data and storing the processable data in the first memory specifically includes: converting the acquired data into data to be processed through an analog-to-digital converter; converting the data to be processed into processable data by receiving a double data rate IDDR primitive instruction; storing the processable data to a first memory; the first memory is a first-in first-out buffer.
Specifically, the function of the analog-to-digital converter of the ADC acquisition module is used to convert the acquired analog data into digital data, and since the FPGA can only process single-edge data, the digital data needs to be converted into single-edge data that the FPGA can process by receiving the double data rate IDDR primitive, and finally the single-edge data is stored in the FIFO module of the acquired data FIFO for subsequent processing of the data.
S102: and reading the processable data in the first memory, and writing the read processable data into the second memory.
In one embodiment of the present application, status data of a first memory is read; according to the state data of the first memory, it is determined whether the processable data in the first memory is written into the second memory. The second memory is Double Data Rate (DDR) synchronous dynamic random access memory (Double Data Rate).
Specifically, before the data in the collected data FIFO is read and written into the DDR, it is determined whether there is readable processable data in the collected data FIFO, that is, whether the status of the collected data FIFO is a non-empty status, and if the status is a non-empty status, the processable data in the collected data FIFO is allowed to be read.
In one embodiment of the present application, the method for reading the processable data in the first memory and writing the read processable data into the second memory specifically includes: judging whether the state of the first memory is a non-empty state according to the state data of the first memory; if yes, reading the processable data in the first memory; and writing the read processable data into the double-rate synchronous dynamic random access memory.
Specifically, the data acquisition FIFO module is used for receiving the data of the ADC acquisition module, so as to solve the problem that the data transmission cannot be directly performed due to the data acquisition of the ADC acquisition module and the DDR data width. When the data acquisition FIFO receives data to be processed in the ADC, the status data and the data of the FIFO are sent to the DDR write control module. The state data includes an empty state, a full state, and a non-empty, non-full state of the FIFO. When the DDR write control module receives that the status data of the FIFO is in a non-empty state, the DDR write control module performs front-end data acquisition FIFO read control according to the fact that the front-end data acquisition FIFO is in the non-empty state, and executes the operation of reading data from the data acquisition FIFO and writing the data into the DDR.
S103: and writing a starting address corresponding to the processable data in the second memory and a trigger address corresponding to the trigger signal into the third memory based on the trigger of the trigger signal.
In one embodiment of the present application, before writing the start address corresponding to the processable data in the second memory and the trigger address corresponding to the trigger signal into the third memory, the method further includes: before the arrival of the trigger signal, the number of the processable data which is configured by the upper computer and is acquired before the arrival of the trigger signal and the number of the processable data which are acquired after the arrival of the trigger signal are received; setting an address period according to the number of the collected processable data before the arrival of the trigger signal; and according to the write control instruction of the second memory, the processable data in the first memory are periodically written into the second memory according to the address period.
Specifically, after the upper computer is configured with the data size M of the pre-trigger and the data size N of the post-trigger, before the trigger signal comes, DDR starts with the initial address A0 and the address of the A0+M-1 data is one period, and the real-time sampled data is written in the addresses from A0 to A0+M-1; after receiving the trigger signal, the address currently written in the A0 to A0+M-1 data addresses is recorded as a trigger address, and N triggered data are written into the DDR from the next address of the A0+M-1 data addresses, namely from the A0+M in real time. After M+N data are sampled, storing the starting address A0 and the intermediate trigger address AX into a Middle-trigger storage address FIFO at the rear end.
For example, m=100, n=50 is set, then the processable data is written in the DDR periodically in the addresses of A0-a99 starting with the start address A0, before the trigger signal comes. Assuming that when the trigger signal is on, processable data is being written in the data address of a50, the data address corresponding to a50 is saved as an intermediate trigger address, and then 50 data after departure are written in real time from a100 into the DDR.
In one embodiment of the present application, writing a start address corresponding to processable data in the second memory and a trigger address corresponding to the trigger signal into the third memory based on the triggering of the trigger signal specifically includes: when the trigger signal is on the spot, recording the corresponding trigger address when the second memory writes the processable data, and stopping writing the processable data continuously in the address period; after the trigger signal comes, according to the number of the collected processable data, the processable data in the first memory is continuously stored at the next address of the address period; and after the acquisition of the set acquired processable data is completed, storing the start address and the trigger address corresponding to the processable data in the second memory into the third memory. The third memory is a Middle-trigger memory address FIFO.
Specifically, if m=100 and n=50 are set, when the trigger signal arrives, if the corresponding address is a50 when the processable data is being written, then a50 is used as the trigger address, and no data is being written from a51 to a99 after a50, but 50 data read from the collected data FIFO after the trigger signal arrives are written in the DDR from a 100. After M+N data are sampled, storing the addresses A0 and A1 into a Middle-trigger storage address FIFO at the back end, namely storing the starting address A0 and the triggering address A50 into the Middle-trigger storage address FIFO after 50 data are acquired.
In one embodiment of the present application, based on the triggering of the plurality of triggering signals, the start addresses corresponding to the processable data in the plurality of second memories and the triggering addresses corresponding to the plurality of triggering signals are written into the third memory.
Specifically, the trigger addresses corresponding to the trigger signals may be A5, a24, a68, etc., and the third memory stores a plurality of start addresses and a plurality of corresponding trigger addresses by collecting data before and after the plurality of trigger signals.
S104: and sequentially reading the processable data in the second memory according to the starting address and the trigger address in the third memory, and storing the read processable data in the fourth memory.
Specifically, since the FIFO cannot be written when it is in a full state, the DDR read control module determines whether to continue writing data from the DDR read into the FIFO storing DDR data according to whether the FIFO storing DDR data is in a full state. The FIFO is in a full state because the upper computer processes data slowly and DDR processes data quickly, and the FIFO module for storing DDR data plays a role in buffering, so that the problem of inconsistent processing speed can be solved.
In one embodiment of the present application, sequentially reading the processable data in the second memory according to the start address and the trigger address in the third memory, and storing the read processable data in the fourth memory, specifically including: reading the processable data from the next address of the trigger address to the last address in the address cycle; reading the processable data from the start address to the trigger address; reading the processable data from the next address of the address cycle to the last address storing the processable data; and restoring the processable data in the second memory read in sequence and sending the data to the fourth memory. The fourth memory is a FIFO storing DDR data.
Specifically, the DDR read control module sequentially takes sampling data from DDR according to a starting address A0 and a triggering address AX address stored in a Middle-trigger storage address FIFO and sends the sampling data to the FIFO module of which the rear end stores DDR data; the address of the read FIFO is A0 and AX, the sequence of reading data from DDR is that data is read from AX+1 address first, and then data is read from A0 to AX address in sequence after the data is taken out from A0+M-1 address, so that the data before triggering signals are restored to actual data, and then N pieces of data after triggering are read from AM in sequence, and the data before and after triggering are restored to normal data and are sent to the FIFO module at the rear end.
For example, the DDR read control module sequentially takes sampling data from the DDR according to the initial address A0 and the trigger address A50 stored in the Middle-trigger storage address FIFO and sends the sampling data to the FIFO module of the DDR data stored at the rear end; the addresses in the Middle-trigger storage address FIFO are A0 and A50, the sequence of reading data from DDR is that the data is read from an A51 address firstly, the data is read from an A0 address to an A50 address sequentially after the data is taken out from an A99 address, the data before triggering signals are restored to actual data, 50 pieces of triggered data are read from an A100 sequentially, and the data read sequentially is restored to normal data so far and is sent to the FIFO module for storing DDR data.
S105: and sending the processable data in the fourth memory to the upper computer.
In one embodiment of the present application, the sending the processable data in the fourth memory to the upper computer specifically includes: performing interface conversion on the fourth memory to convert the fourth memory into a data interface matched with a corresponding controller; and sending the processable data in the fourth memory to the controller, and sending the processable data in the fourth memory to the upper computer through the controller.
Specifically, the FIFO needs to upload data to the host computer through interface conversion, and the FIFO-to-Stream interface is because the XDMA IP core instantiated by the FPGA is a Stream interface, and the data reading the FIFO needs to be converted by sitting interface. The XDMA module communicated with the upper computer transmits data to the upper computer by utilizing an IP core of the finished product in the FPGA.
The application provides a method for realizing data acquisition through intermediate triggering based on FPGA, which at least comprises the following beneficial effects: by the method, data before and after a plurality of trigger signals can be acquired, and a technician can know the change of the signals through observing the data so as to adjust related parameters, so that an experiment achieves an expected effect.
The method for realizing data acquisition through intermediate triggering based on the FPGA provided by the embodiment of the application is based on the same inventive thought, and the embodiment of the application also provides corresponding equipment for realizing data acquisition through intermediate triggering based on the FPGA, as shown in fig. 3.
The embodiment provides a device for realizing data acquisition through intermediate triggering based on an FPGA, which comprises:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
converting the collected data into processable data and storing the processable data into a first memory;
reading the processable data in the first memory, and writing the read processable data into the second memory;
writing a start address corresponding to the processable data in the second memory and a trigger address corresponding to the trigger signal into the third memory based on the trigger of the trigger signal;
sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in the fourth memory;
and sending the processable data in the fourth memory to the upper computer.
All embodiments in the application are described in a progressive manner, and identical and similar parts of all embodiments are mutually referred, so that each embodiment mainly describes differences from other embodiments. In particular, for the apparatus embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
The devices and the methods provided in the embodiments of the present application are in one-to-one correspondence, so that the devices also have similar beneficial technical effects as the corresponding methods, and since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the device quality are not described here again.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (4)
1. The method for realizing data acquisition through intermediate triggering based on the FPGA is characterized by comprising the following steps:
converting the collected data into processable data and storing the processable data in a first memory, wherein the method specifically comprises the following steps:
converting the acquired data into data to be processed through an analog-to-digital converter;
converting the data to be processed into processable data by receiving a double data rate IDDR primitive instruction;
storing the processable data to a first memory; the first memory is a first-in first-out buffer;
reading the processable data in the first memory, and writing the read processable data into a second memory, wherein the method specifically comprises the following steps:
judging whether the state of the first memory is a non-empty state according to the state data of the first memory;
if yes, reading the processable data in the first memory;
writing the read processable data into a double-rate synchronous dynamic random access memory;
before the arrival of the trigger signal, the number of the processable data which is configured by the upper computer and is acquired before the arrival of the trigger signal and the number of the processable data which are acquired after the arrival of the trigger signal are received;
setting an address period according to the number of the collected processable data before the trigger signal arrives;
according to the write control instruction of the second memory, the processable data in the first memory are periodically written into the second memory according to the address period;
based on the triggering of the triggering signal, writing the starting address corresponding to the processable data in the second memory and the triggering address corresponding to the triggering signal into a third memory, wherein the method specifically comprises the following steps:
recording the trigger address corresponding to the second memory when the processable data is written in when the trigger signal comes, and stopping writing the processable data continuously in the address period;
after the trigger signal comes, according to the number of the collected processable data, continuing to store the processable data in the first memory at the next address of the address period;
after the set collected processable data are collected, storing a starting address and the triggering address corresponding to the processable data in the second memory into the third memory;
sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in a fourth memory, wherein the method specifically comprises the following steps of:
reading processable data from a next address of the trigger address to a last address in the address cycle;
reading processable data from the start address to the trigger address;
reading the processable data from the next address to the last address storing the processable data of the address cycle;
performing a restore operation on the sequentially read processable data in the second memory and sending the data to a fourth memory;
and sending the processable data in the fourth memory to an upper computer.
2. The method of claim 1, wherein sending the processable data in the fourth memory to an upper computer, specifically comprises:
performing interface conversion on the fourth memory to convert the fourth memory into a data interface matched with a corresponding controller;
and sending the processable data in the fourth memory to the controller, and sending the processable data in the fourth memory to an upper computer through the controller.
3. The method according to claim 1, wherein the method further comprises:
and writing the starting addresses corresponding to the processable data in the second memories and the triggering addresses corresponding to the triggering signals into a third memory based on triggering of the triggering signals.
4. An apparatus for implementing data acquisition by intermediate triggering based on FPGA, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
converting the collected data into processable data and storing the processable data in a first memory, wherein the method specifically comprises the following steps:
converting the acquired data into data to be processed through an analog-to-digital converter;
converting the data to be processed into processable data by receiving a double data rate IDDR primitive instruction;
storing the processable data to a first memory; the first memory is a first-in first-out buffer;
reading the processable data in the first memory, and writing the read processable data into a second memory, wherein the method specifically comprises the following steps:
judging whether the state of the first memory is a non-empty state according to the state data of the first memory;
if yes, reading the processable data in the first memory;
writing the read processable data into a double-rate synchronous dynamic random access memory;
before the arrival of the trigger signal, the number of the processable data which is configured by the upper computer and is acquired before the arrival of the trigger signal and the number of the processable data which are acquired after the arrival of the trigger signal are received;
setting an address period according to the number of the collected processable data before the trigger signal arrives;
according to the write control instruction of the second memory, the processable data in the first memory are periodically written into the second memory according to the address period;
based on the triggering of the triggering signal, writing the starting address corresponding to the processable data in the second memory and the triggering address corresponding to the triggering signal into a third memory, wherein the method specifically comprises the following steps:
recording the trigger address corresponding to the second memory when the processable data is written in when the trigger signal comes, and stopping writing the processable data continuously in the address period;
after the trigger signal comes, according to the number of the collected processable data, continuing to store the processable data in the first memory at the next address of the address period;
after the set collected processable data are collected, storing a starting address and the triggering address corresponding to the processable data in the second memory into the third memory;
sequentially reading the processable data in the second memory according to the starting address and the triggering address in the third memory, and storing the read processable data in a fourth memory, wherein the method specifically comprises the following steps of:
reading processable data from a next address of the trigger address to a last address in the address cycle;
reading processable data from the start address to the trigger address;
reading the processable data from the next address to the last address storing the processable data of the address cycle;
performing a restore operation on the sequentially read processable data in the second memory and sending the data to a fourth memory;
and sending the processable data in the fourth memory to an upper computer.
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