CN117234456A - Synchronous FIFO (first in first out) caching method and device and electronic equipment - Google Patents

Abstract

The embodiment of the application discloses a synchronous FIFO (first in first out) caching method, a synchronous FIFO caching device and electronic equipment, and belongs to the field of cache control. The application uses the single-port SRAM to replace the existing register group to buffer data, and can greatly save the area for the high-capacity synchronous FIFO buffer device. The frequency doubling uses a read-before-write time sequence, so that the time sequence of the FIFO interface is kept unchanged, the protocol of the data processing unit is kept unchanged, and the design of the communication protocol is simplified.

Description

Synchronous FIFO (first in first out) caching method and device and electronic equipment

Technical Field

The present application relates to the field of cache control, and in particular, to a method, an apparatus, and an electronic device for synchronous FIFO caching.

Background

When the hardware unit processes data, a FIFO (First In First Out, first-in first-out) buffer device is often used to buffer the data, so as to solve the problem of inconsistent speed and timeliness of processing the data at two ends of the FIFO device. The FIFO buffer device is divided into a synchronous FIFO buffer device and an asynchronous FIFO buffer device, wherein the clock signals at the reading and writing ends of the synchronous FIFO buffer device are synchronous, and the clock signals at the reading and writing ends of the asynchronous FIFO buffer device are asynchronous.

In synchronous FIFO buffers, the buffering is typically implemented with a set of registers. As shown in the schematic structure of the synchronous FIFO buffer device in fig. 1, the register set has real-time read-write characteristics, so that both writing and reading can be performed simultaneously, but when the synchronous FIFO buffer device needs a larger capacity, the area occupied by the register set is larger.

Disclosure of Invention

The embodiment of the application provides a synchronous FIFO (first in first out) caching method, a synchronous FIFO caching device and electronic equipment, which can solve the problem of large occupied area caused by the fact that a register is used for caching data in the prior art. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a method for synchronous FIFO buffering, where the method includes:

the clock generator sends a first clock signal to the synchronous FIFO controller and the data processing unit, and sends a second clock signal to the synchronous FIFO controller, the SRAM controller and the single-port SRAM; the second clock signal is twice the frequency of the first clock signal;

the data processing unit sends FIFO read signals to the synchronous FIFO controller according to the first clock signal;

and the synchronous FIFO controller generates an SRAM read signal corresponding to the FIFO read signal according to the second clock signal, and sends the SRAM read signal to the SRAM controller.

The SRAM controller reads SRAM read data in the single-port SRAM according to the SRAM read signal and sends the SRAM read data to the synchronous FIFO controller;

the synchronous FIFO controller generates FIFO read data according to the SRAM read data and sends the FIFO read data to the data processing unit;

the data processing unit sends FIFO read signals and FIFO write data to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller generates an SRAM write signal corresponding to the FIFO write signal and SRAM write data corresponding to the FIFO write data according to the second clock signal, and sends the SRAM write signal and the SRAM write data to the SRAM controller;

and the SRAM controller writes the SRAM write data into the single-port SRAM according to the SRAM write signal.

In a second aspect, an embodiment of the present application provides a synchronous FIFO buffer device, including:

a clock generator for transmitting a first clock signal to the synchronous FIFO controller and the data processing unit, and transmitting a second clock signal to the synchronous FIFO controller, the SRAM controller, and the single port SRAM; the second clock signal is twice the frequency of the first clock signal;

the data processing unit is used for sending FIFO read signals to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller is used for generating an SRAM read signal corresponding to the FIFO read signal according to the second clock signal and sending the SRAM read signal to the SRAM controller.

The SRAM controller is used for reading SRAM read data in the single-port SRAM according to the SRAM read signal and sending the SRAM read data to the synchronous FIFO controller;

the synchronous FIFO controller is further used for generating FIFO read data according to the SRAM read data and sending the FIFO read data to the data processing unit;

the data processing unit is further used for sending FIFO read signals and FIFO write data to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller is further configured to generate an SRAM write signal corresponding to the FIFO write signal and generate SRAM write data corresponding to the FIFO write data according to the second clock signal, and send the SRAM write signal and the SRAM write data to the SRAM controller;

the SRAM controller is also used for writing the SRAM write data into the single-port SRAM according to the SRAM write signal.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-described method steps.

In a fourth aspect, embodiments of the present application provide an electronic device, which may include the above-described respective components.

The technical scheme provided by the embodiments of the application has the beneficial effects that at least:

the single-port SRAM is used for replacing the existing register set to buffer data, so that the area can be greatly saved for the high-capacity synchronous FIFO buffer device. The frequency doubling uses a read-before-write time sequence, so that the time sequence of the FIFO interface is kept unchanged, the protocol of the data processing unit is kept unchanged, and the design of the communication protocol is simplified.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a synchronous FIFO buffer device according to the prior art;

FIG. 2 is a schematic diagram of a synchronous FIFO buffer device according to an embodiment of the present application;

FIG. 3 is a flow chart of interactions between various components provided by an embodiment of the present application;

FIG. 4 is a flowchart of a synchronous FIFO caching method according to an embodiment of the present application;

FIG. 5 is a timing diagram of a read operation provided by an embodiment of the present application;

FIG. 6 is a timing diagram of a write operation provided by the present application;

fig. 7 is a timing diagram for simultaneously performing a write operation and a read operation provided by the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of a synchronous FIFO buffer device according to an embodiment of the application, which specifically includes a clock generator, a data processing unit, a synchronous FIFO controller, an SRAM controller, and a single-port SRAM. The first output end of the clock generator is respectively connected with the data processing unit and the synchronous FIFO controller, the second output end of the clock generator is respectively connected with the synchronous FIFO controller, the SRAM controller and the single-port SRAM, the data processing unit is connected with the synchronous FIFO controller, and the SRAM controller is connected with the synchronous FIFO controller and the single-port SRAM. The first output terminal of the clock generator outputs a first clock signal fifo_clk, and the second output terminal outputs a second clock signal sram_clk, the period of the first clock signal being 2 times that of the second clock signal.

The components in the synchronous FIFO buffer device may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field-Programmable gate array (FPGA), and Programmable Logic Array (PLA).

In the apparatus provided in the foregoing embodiment, when the synchronous FIFO buffer method is executed, only the division of the functional modules is used for illustration, and in practical application, the allocation of the functions may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the embodiments of the synchronization FIFO buffer device and the synchronization FIFO buffer method provided in the foregoing embodiments belong to the same concept, which embody the implementation process in detail with reference to the method embodiment, and are not repeated herein.

It should be understood that the number of components and the connection relationship in fig. 2 are merely illustrative. Other numbers of components and connections may be used as desired for implementation.

The following describes the synchronous FIFO buffer method according to the embodiment of the application in detail with reference to fig. 3.

Referring to fig. 3 and fig. 4, a flowchart of a synchronous FIFO buffer method is provided in an embodiment of the application. As shown in fig. 2, the method according to the embodiment of the present application may include the following steps:

s401, the clock generator sends a first clock signal to the synchronous FIFO controller and the data processing unit, and sends a second clock signal to the synchronous FIFO controller, the SRAM controller and the single port SRAM.

After the electronic device is started, a data processing unit, a clock generator, a synchronous FIFO controller, an SRAM (Static Random-Access Memory) controller and a single-port SRAM start to work after being powered on, where the data processing unit is configured to perform a read operation or a write operation in the synchronous FIFO buffer device. The synchronous FIFO buffer device comprises a clock generator, a synchronous FIFO controller, an SRAM controller and a single-port SRAM, wherein the single-port SRAM only has one read-write port, namely only has one group of data lines and address lines, and the read operation and the write operation are accessed through ports, namely only can execute the read operation or the write operation at the same moment. The clock generator is used for periodically providing clock signals for all components or units, particularly providing a first clock signal for the data processing unit and the synchronous FIFO controller and providing a second clock signal for the synchronous FIFO controller, the SRAM controller and the single-port SRAM, namely the synchronous FIFO controller inputs the first clock signal and the second clock signal at the same time, and the frequency of the second clock signal is 2 times that of the first clock signal.

For example, referring to the block diagram of the synchronous FIFO buffer shown in fig. 2, the clock generator outputs a first clock signal fifo_clk at a first output and a second clock signal sram_clk at a second output, the frequency of the second clock signal sram_clk being 2 times that of the first clock signal fifo_clk, as can be seen from the timing diagram of fig. 4.

In some embodiments of the application, the electronic device, after power-up, the data processing unit sends a FIFO reset signal fifo_rstn to the synchronous FIFO controller, which resets the write pointer wr_ptr, the read pointer rd_ptr, and the valid data COUNTER based on the FIFO reset signal, the write pointer pointing to the write address of the next data, the read pointer pointing to the read address of the next data, and the count value of the valid data COUNTER representing the number of data in the current queue.

S402, the data processing unit sends FIFO read signals to the synchronous FIFO controller according to the first clock signal.

Referring to the timing chart of the read operation shown in fig. 5, the period of the first clock signal fifo_clk is 2 times that of the second clock signal sram_clk, and then one period of the first clock signal fifo_clk is divided into two time intervals corresponding to 2 second clock signals sram_clk within one period of the first clock signal fifo_clk: t0 time interval and T1 time interval. When the data processing unit detects the rising edge of the first clock signal fifo_clk, it generates a FIFO read signal fifo_rd, and the FIFO read signal fifo_rd is high-level signal, and the duration is the period of the first clock signal fifo_clk.

S403, the synchronous FIFO controller generates an SRAM read signal corresponding to the FIFO read signal according to the second clock signal, and sends the SRAM read signal to the SRAM controller.

When the synchronous FIFO controller detects the rising edge of the second clock signal, an SRAM read signal is generated, the duration of the SRAM read signal is the period of the second clock signal SRAM_CLK, then the synchronous FIFO controller sends the SRAM read signal to the SRAM controller, and the duration of the SRAM read signal is equal to the duration of the T0 time interval. The synchronous FIFO controller maintains a read pointer RD_PTR plus 1, takes the updated read pointer as the read address of the single-port SRAM, and then converts the FIFO read signal into an SRAM read signal under a second clock signal.

S404, the SRAM controller reads the SRAM read data in the single-port SRAM according to the SRAM read signal, and sends the SRAM read data to the synchronous FIFO controller.

Referring to the timing chart of the read operation shown in fig. 5, the SRAM controller reads the SRAM read data sram_rdata indicated by the updated read pointer rd_ptr in the single-port SRAM in response to the SRAM read signal, and then sends the SRAM read data sram_rdata to the synchronous FIFO controller. According to fig. 5, since it takes a certain time to read data, the SRAM controller sends out the SRAM read signal, and then reads the SRAM read data from the single-port SRAM after the end boundary of the SRAM read signal.

S405, the synchronous FIFO controller generates FIFO read data according to the SRAM read data and sends the FIFO read data to the data processing unit.

Referring to the timing chart of the read operation shown in fig. 5, after receiving the SRAM read data sram_rdata, the synchronous FIFO controller takes the SRAM read data as the FIFO read data fifo_rdata, and then sends the FIFO read data to the data processing unit, so as to implement the read operation process of the data processing unit.

S406, the data processing unit sends FIFO read signals and FIFO write data to the synchronous FIFO controller according to the first clock signal.

When the data processing unit executes writing operation in the synchronous FIFO buffer device, the data processing unit sends FIFO writing signals and FIFO writing data to the synchronous FIFO controller according to the first clock signal.

For example, referring to fig. 4 and 6, when the data processing unit detects the rising edge of the first clock signal, it generates FIFO write signal fifo_wr and FIFO write data fifo_wdata, and sends the FIFO write signal fifo_wr to the FIFO controller, where the FIFO write signal fifo_wr is a high level signal, and the duration is the period of the first clock signal fifo_clk, that is, the T0 time interval and the T1 time interval in fig. 6.

S407, the synchronous FIFO controller generates an SRAM write signal corresponding to the FIFO write signal and SRAM write data corresponding to the FIFO write data according to the second clock signal, and sends the SRAM write signal and the SRAM write data to the SRAM controller.

Wherein the synchronous FIFO controller maintains a write pointer wr_ptr, which is incremented by 1 each time a FIFO write signal fifo_wr is received, until fifo_depth-1 returns to the 0 cycle. And converting the FIFO write signal and the FIFO write data sent by the data processing unit into the SRAM write signal and the SRAM write data under the second clock signal, providing the SRAM write signal and the SRAM write data for the SRAM controller, and simultaneously providing a write pointer WR_PTR as a write address of the single-port SRAM.

Referring to the schematic diagram of the write operation shown in fig. 6, when the synchronous FIFO controller detects the rising edge of the second clock signal sram_clk, the synchronous FIFO controller generates the SRAM write signal sram_wr, wherein the SRAM write signal corresponds to the T1 time interval, i.e., the duration of the SRAM write signal sram_wr is equal to the T1 time interval, and then generates the corresponding SRAM write data sram_wdata based on the FIFO write data fifo_wdata.

S408, the SRAM controller writes the SRAM write data into the single-port SRAM according to the SRAM write signal.

The SRAM controller provides a write pointer WR_PTR according to the FIFO controller, and the SRAM write data is written into the single-port SRAM.

Further, the synchronous FIFO controller maintains an effective data COUNTER, the count value of which is incremented by 1 each time a FIFO write signal fifo_wr is received, and decremented by 1 each time a FIFO read signal fifo_rd is received, and the count value remains unchanged if the FIFO write signal fifo_wr and the FIFO write signal fifo_rd are received simultaneously.

With reference to the interactive flowchart shown in FIG. 3, the synchronous FIFO controller provides a queue status signal, i.e., FULL status signal FIFO_FULL or EMPTY status signal FIFO_EMPTY, according to the data processing unit. When receiving FIFO write signal FIFO_WR of the data processing unit, the synchronous FIFO controller judges whether the current queue is in a FULL state, if not, the synchronous FIFO controller cannot execute write operation, and returns a FULL state signal FIFO_full to the data processing unit; if not, the write operation can be performed normally. When receiving the FIFO read signal FIFO_RD of the data processing unit, judging whether the current queue is in an EMPTY state, if so, returning an EMPTY state signal FIFO_EMPTY to the data processing unit, and if not, executing the read operation normally.

Further, the method for determining the queue status by the synchronous FIFO controller may be that if the current count value counter=0 of the valid data COUNTER indicates that the current queue is in an empty state; if the current count value COUNTER of the valid data COUNTER is equal to or greater than (FIFO_DEPTH-1), the current queue is full, and the maximum queue DEPTH is indicated by the FIFO_DEPTH.

Referring to the timing diagrams of the write operation and the read operation shown in fig. 7, the period of the first clock signal fifo_clk is twice that of the second clock signal sram_clk, it can be seen that the SRAM read signal sram_rd is only asserted during the period T0, the SRAM write signal sram_wr is only asserted during the period T1, and the timing of the data processing unit and the synchronous FIFO controller is the same as the timing of the use register in fig. 1, i.e. the shortening of the stable time of fifo_rdata for FIFO read data has no influence on sampling, so that the protocol of the data processing unit is not adjusted in case of a hardware structure change.

In the embodiment of the application, because of the characteristic of a single-port SRAM, each SRAM_CLK can only accept one SRAM_RD or SRAM_WR for access, the application adds the double frequency clock SRAM_CLK of the FIFO_CLK, so that two SRAM_CLK are arranged in one FIFO_CLK period, two access operations can be carried out on the single-port SRAM, namely, the FIFO_WR and the FIFO_RD can be simultaneously realized in one FIFO_CLK without changing the access time sequence of a data processing unit to a synchronous FIFO buffer device.

Because the single-port SRAM characteristic, the sram_rdata can be sampled only in the next cycle of the sram_rd, so that the T0 cycle (the first sram_clk) is fixedly used as the SRAM read cycle, the sram_rd is only validated in the cycle, and the sram_rdata output in the T1 cycle (the second sram_clk) is assigned to the fifo_rdata, so that the sampling of the data processing unit at the time point of SAMPLE is not affected. The read timing of the FIFO by the data processing unit is not changed.

Wherein, the T1 period (the second SRAM_CLK) is fixedly taken as the SRAM writing period, only the SRAM_WR is validated in the period, the FIFO_WDATA is directly assigned to the SRAM_WDATA (only the SRAM_WDATA is validated when the SRAM_WR is valid, and the simplified design does not mask the data of the T0 period), so that the current SRAM writing is not influenced, and the next FIFO_CLK is not influenced to immediately read the data. The write timing of the data processing unit to the FIFO is not changed.

The embodiment of the application has the following beneficial effects:

1. the use of a single port SRAM instead of a register set in the FIFO can save area significantly for a high capacity FIFO, for example, in the WIFI6 baseband protocol, the use of a register set to implement a FIFO with a bit width of 8 bits and a depth of 256 requires about 20K gateount (assuming an area utilization of 78%), while the same process uses an SRAM requiring about 8K gateount (the shape process is different and the area is different), which can save about 60% of the area.

2. By using the design of double frequency SRAM, the synchronous read-write of the synchronous FIFO buffer device can be supported, the high bandwidth is reserved, and the bit width of the synchronous FIFO buffer device is not required to be increased or the frequency-boosting processing of the data processing unit is not required.

3. The frequency doubling uses a read-before-write time sequence, so that the time sequence of the FIFO interface is kept unchanged, the protocol of the data processing unit is kept unchanged, and the design of the communication protocol is simplified.

The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the steps of the method shown in the embodiment of fig. 3, and the specific execution process may refer to the specific description of the embodiment shown in fig. 3, which is not repeated herein.

The application also provides a computer program product storing at least one instruction that is loaded and executed by the processor to implement the synchronous FIFO caching method as described in the various embodiments above.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, or the like.

The foregoing disclosure is illustrative of the present application and is not to be construed as limiting the scope of the application, which is defined by the appended claims.

Claims (7)

1. A method of synchronizing FIFO buffers, the method comprising:

the clock generator sends a first clock signal to the synchronous FIFO controller and the data processing unit, and sends a second clock signal to the synchronous FIFO controller, the SRAM controller and the single-port SRAM; the second clock signal is twice the frequency of the first clock signal;

the data processing unit sends FIFO read signals to the synchronous FIFO controller according to the first clock signal;

and the synchronous FIFO controller generates an SRAM read signal corresponding to the FIFO read signal according to the second clock signal, and sends the SRAM read signal to the SRAM controller.

The SRAM controller reads SRAM read data in the single-port SRAM according to the SRAM read signal and sends the SRAM read data to the synchronous FIFO controller;

the synchronous FIFO controller generates FIFO read data according to the SRAM read data and sends the FIFO read data to the data processing unit;

the data processing unit sends FIFO read signals and FIFO write data to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller generates an SRAM write signal corresponding to the FIFO write signal and SRAM write data corresponding to the FIFO write data according to the second clock signal, and sends the SRAM write signal and the SRAM write data to the SRAM controller;

and the SRAM controller writes the SRAM write data into the single-port SRAM according to the SRAM write signal.

2. The method as recited in claim 1, further comprising:

after power-on, the data processing unit sends a FIFO reset signal to the FIFO controller;

the synchronous FIFO controller resets the count values of the read pointer, the write pointer and the effective data counter according to the FIFO reset signal.

3. The method of claim 1 or 2, wherein the synchronous FIFO controller generating an SRAM read signal corresponding to the FIFO read signal from the second clock signal, and transmitting the SRAM read signal to the SRAM controller, comprises:

the synchronous FIFO controller judges whether the current queue is in a full state, if not, generates an SRAM read signal corresponding to the FIFO read signal according to the second clock signal, and sends the SRAM read signal to the SRAM controller;

the method further comprises the steps of:

and if the current queue is in a full state, the synchronous FIFO controller returns a full state signal to the data processing unit.

4. A method according to claim 3, wherein the synchronous FIFO controller generates FIFO read data from the SRAM read data, and transmits the FIFO read data to the data processing unit, comprising:

the synchronous FIFO controller judges whether the current queue is in an empty state, if not, FIFO read data are generated according to the SRAM read data, and the FIFO read data are sent to the data processing unit;

the method further comprises the steps of:

and if the current queue is in an empty state, the synchronous FIFO controller returns an empty state signal to the data processing unit.

5. The method of claim 4, wherein if the current count value of the valid data COUNTER = 0, then indicating that the current queue is empty; if the current count value COUNTER of the valid data COUNTER is equal to or greater than (FIFO_DEPTH-1), the current queue is in a full state, and the FIFO_DEPTH represents the maximum queue DEPTH.

6. A synchronous FIFO buffer device, comprising:

a clock generator for transmitting a first clock signal to the synchronous FIFO controller and the data processing unit, and transmitting a second clock signal to the synchronous FIFO controller, the SRAM controller, and the single port SRAM; the second clock signal is twice the frequency of the first clock signal;

the data processing unit is used for sending FIFO read signals to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller is used for generating an SRAM read signal corresponding to the FIFO read signal according to the second clock signal and sending the SRAM read signal to the SRAM controller.

The SRAM controller is used for reading SRAM read data in the single-port SRAM according to the SRAM read signal and sending the SRAM read data to the synchronous FIFO controller;

the synchronous FIFO controller is further used for generating FIFO read data according to the SRAM read data and sending the FIFO read data to the data processing unit;

the data processing unit is further used for sending FIFO read signals and FIFO write data to the synchronous FIFO controller according to the first clock signal;

the synchronous FIFO controller is further configured to generate an SRAM write signal corresponding to the FIFO write signal and generate SRAM write data corresponding to the FIFO write data according to the second clock signal, and send the SRAM write signal and the SRAM write data to the SRAM controller;

the SRAM controller is also used for writing the SRAM write data into the single-port SRAM according to the SRAM write signal.

7. An electronic device comprising a synchronous FIFO buffer device as claimed in claim 6.