CN113590026A - Data transmission optimization method of NVMe storage equipment based on eMMC - Google Patents
Data transmission optimization method of NVMe storage equipment based on eMMC Download PDFInfo
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Abstract
The invention discloses a Data transmission optimization method of NVMe storage equipment based on eMMC, which comprises the steps of establishing a mapping Table Command Data Table in an SSD NVMe controller, wherein the Table is the mapping of a Command and a Data block stored in a Data Buffer from a Host, and maintains the relevant state of the Command and the Data block in the Data Buffer; before power-on initialization, setting a maximum time threshold value for execution of an eMMC channel allowed command and data block operation in a configuration file; when each eMMC acquires a Command and a Data block to be executed from a Data Buffer, a corresponding state of the eMMC is searched in a Command Data Table; only when the operation state is the state to be executed, the command and the data block can be read by the eMMC; when the command and data block is read by the eMMC, the operation state is changed from the to-be-executed state to an execution success state. The invention solves the problem of channel blockage caused by unpredictability of Busy time for processing data by the eMMC, thereby improving the data transmission rate and reducing the time delay.
Description
Technical Field
The invention belongs to the technical field of data storage, and relates to a data transmission optimization method of an eMMC-based NVMe storage device.
Background
NVMe protocol was issued in 2011 by INTEL to unify interface protocol set-up ecology. NVM Express (NVMe), or called Non-Volatile Memory Host Controller Interface Specification (English: Non Volatile Memory Host Controller Interface Specification, abbreviated as NVMHCIS), is a logical device Interface Specification. It is a bus transfer protocol specification (equivalent to the application layer in the communication protocol) similar to AHCI based on a logical interface of a device for accessing a non-volatile memory medium (e.g., a solid state drive employing flash memory) attached through a PCI Express (PCIe) bus. NVMe adopts a multi-command queue (65536 command queues at most), each command has variable data length (512B to 2MB), and simultaneously, a data block records and retrieves in a Host-end memory in a mode of supporting Physical Region Page and Scatter Gate List. The NVMe protocol supports out-of-order execution among commands, supports out-of-order transmission of data blocks in the commands and supports variable weight processing among command queues.
In order to increase the capacity and transmission rate of the solid state disk and reduce the latency, a solid state disk based on a RAIM (Redundant Array of Independent memory) architecture is proposed, and the internal architecture thereof is shown in fig. 1.
In the storage device of the framework, a solid state disk (SSD Controller) is provided with a Data Buffer (Data Buffer) for caching Data sent by a Host (Host); the eMMC Host module takes out the Data in the Data Buffer and writes the Data in the respective eMMC.
The eMMC integrates a Flash Controller therein and is used for completing functions of erasing balance, bad block management, ECC check and the like. Compared with the method that the NAND Flash is directly accessed to the Host end, the eMMC shields the physical characteristics of the NAND Flash, can reduce the complexity of software of the Host end, enables the Host end to be concentrated on upper-layer services, and omits special processing of the NAND Flash. But its disadvantages are also evident:
1. the Busy time of the data processing of the eMMC is unpredictable, the eMMC is continuously erased and written along with the increase of time years, the data processing speed of the eMMC is slow, the duration can reach more than 100ms, and therefore data transmission blockage is easily caused.
2. After the Host (Host) sends out a storage operation command, the NVMe protocol supports out-of-order execution among commands and also supports out-of-order transmission of Data blocks in the commands, and the storage master receives the command sent by the Host and temporarily stores the received command in a Buffer (Data Buffer). Commands and Data in the Buffer (Data Buffer) are selected to be sent to the free eMMC according to whether the Channel (Channel) is free. Because the Busy time of data processing by the eMMC is unpredictable, when a channel processes data for a particularly long time, the data of the channel is always blocked and cannot be written into the eMMC, which may cause performance and transmission rate degradation. See fig. 2.
Disclosure of Invention
In order to solve the problems, the invention provides a Data transmission optimization method of NVMe storage equipment based on eMMC, which comprises the steps of establishing a mapping Table Command Data Table in an SSD NVMe controller, wherein the Table is the mapping of a Command and a Data block stored in a Data Buffer from a Host, maintains the state of the Command and the Data block in the Data Buffer, and comprises five parts which are respectively the address of the Command, the address of the Data block, an operation state, an effective bit and a reserved bit;
before power-on initialization, setting a maximum time threshold value for execution of an eMMC channel allowed command and data block operation in a configuration file;
when each eMMC acquires a Command and a Data block to be executed from a Data Buffer, a corresponding state of the eMMC is searched in a Command Data Table; only when the operation state is the state to be executed, the command and the data block can be read by the eMMC; when the command and data block is read by the eMMC, the operation state is changed from the to-be-executed state to an execution success state.
Preferably, the method specifically comprises the following steps:
in the process of transmitting data by an eMMC channel, an internal register of the eMMC is used for timing the operation execution time of a data block under a current command, and then the time is compared with a maximum time threshold value set during initialization;
if the execution is successful within the maximum time threshold, the eMMC gives a successful feedback to the SSD NVMe controller;
then marking the successfully executed Command and the valid bit of the Data block as invalid in the Command Data Table, and waiting for the garbage recovery mechanism to clear;
if the maximum time threshold is exceeded, the eMMC stops executing the current command and returns a failure feedback to the SSD NVMe controller;
and then, the operation states of the Command and the Data block which are executed in failure are rewound into a state to be executed in the Command Data Table, and the Command and the Data block are waited to be selected and executed by other idle eMMC channels.
Preferably, the method specifically comprises the following steps:
s10, the Host sends a storage operation Command, the Command and the Data block are transmitted to a Data Buffer of the SSD NVMe controller, then the SSD NVMe controller initializes a Command Data Table, the operation state of the Command and the Data block is initialized to a state to be executed, and the effective position is initialized to be effective;
s20, the SSD NVMe controller judges whether an idle eMMC channel exists at the moment, if so, the idle eMMC takes out the storage operation command from the Data Buffer and selects the corresponding Data block thereof, and transmits the storage operation command to the corresponding channel; after the Command and the Data block are transmitted to the eMMC channel, the SSD NVMe controller changes the operation state of the corresponding Command and Data block in the Command Data Table into an execution success state;
s30, assuming that the current eMMC channels 1-n are all in an idle state, wherein n is a natural number; the SSD NVMe controller selects the data blocks 1-n to be respectively transmitted to the corresponding idle eMMC channels;
s40, the n eMMC channels start to store and transmit data, the busy time of different channels is different, and a register in each channel can time data transmission and is compared with a maximum time threshold value; suppose that data is blocked by the eMMC channel 1 due to the busy time exceeding a maximum time threshold; the eMMC channel 2-n does not exceed the maximum time threshold value, and data transmission is completed;
s50, stopping the execution of the current command due to the data blockage of the eMMC channel 1, and returning a failure feedback to the SSD NVMe controller; after the data storage of the eMMC channel 2-n is finished, a successful feedback is returned to the SSD NVMe controller, and then the data can be received again after entering an idle state;
s60, after receiving the feedback of the eMMC channel, the SSD NVMe controller will rollback the Command executed in failure and the operation state of the Data block to the state to be executed again in the Command Data Table because the feedback of the eMMC channel 1 is failed, and wait for being processed by other idle eMMC channels;
s70, the eMMC channel 2-n is successful in feedback, so that the valid bits of the Command and the Data block are marked as invalid in the Command Data Table, and the garbage collection mechanism of the SSD NVMe controller is waited to clear the invalid bits;
s80, since the operation state of the command and data block 1 is reset to the to-be-executed state, it can be processed by the idle eMMC channel; assuming that the SSD NVMe controller hands the data block 1 to the idle eMMC channel 2 for processing, then the processing is continued from S20 until all the data blocks under the command are successfully stored;
s90, when the data block under the current command is subjected to a storage operation, if there are remaining idle channels in the eMMC channel, the SSD NVMe controller continues to receive the next command for execution, and does not need to wait for all data blocks under the current command to be stored completely.
Preferably, the to-be-executed state of the operation states is represented by 0, and the execution success state is represented by 1.
Preferably, the valid bit is represented by a valid 1 and the invalid 0.
The beneficial effects of the invention at least comprise:
the NVMe protocol employs multiple command queues (up to 65536 command queues), each of variable command data length (from 512B to 2MB), supports out-of-order execution between commands, and also supports out-of-order transfer of data blocks within commands, while supporting variable weight processing between command queues. On the basis of an RAIM storage architecture, by utilizing the NVMe deep IO queue capacity, the command out-of-order execution capacity and the data block out-of-order transmission capacity, the invention provides a new data transmission optimization method aiming at the problem of data blocking caused by unpredictable Busy time of eMMC, and the SSD performance and the transmission rate are improved.
The NVMe master designs and maintains a mapping Table Command Data Table written in the Data Buffer, and the Table records the operating states of the commands and the Data in real time.
When the eMMC executes the storage command to transmit data, the internal register times and judges the data processing, once a preset maximum time threshold value is exceeded, the execution of the command is ended, then the operation state of the command and the data block under the command is returned in the mapping table, and the execution is tried again by the rest idle eMMC channels.
Drawings
FIG. 1 is a block diagram of a solid state disk based on RAIM architecture in the prior art;
FIG. 2 is a schematic diagram of write data blocking based on RAIM SSD in the prior art;
fig. 3 is an application schematic diagram of an NVMe eMMC master control system of the data transmission optimization method for an eMMC-based NVMe storage device according to the embodiment of the present invention;
fig. 4 is a schematic diagram of an NVMe master write data flow of the data transmission optimization method for the eMMC-based NVMe storage device according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Referring to fig. 3, a mapping Table Command Data Table is established in the SSD NVMe Controller, the Table is a mapping of commands and Data blocks stored in the Data Buffer from the Host, the Table mainly maintains the relevant states of the commands and the Data blocks in the Data Buffer, and the Table includes five parts, namely, the address of the Command (Command _ Addr), the address of the Data block (Data _ Addr), the operating state (operation _ Status), the Valid bit (Valid), and the reserved bit (Reserve).
Initialization: before the equipment is powered on and initialized, setting a maximum time threshold value for execution of an eMMC Channel allowed command and a data block operation in a configuration file;
when each eMMC acquires a Command and a Data block to be executed from a Data Buffer, a corresponding state of the eMMC needs to be searched in a mapping Table Command Data Table; only command and data blocks with an operation state (operation _ Status) to-be-executed state (indicated by 0) can be read by the eMMC; when the command and data block is read by the eMMC, the status transitions from the to-be-executed status (indicated by 0) to an execution-successful status (indicated by 1).
In the process of transmitting data by an eMMC channel, an internal register of the eMMC is used for timing the operation execution time of a data block under a current command, and then the time is compared with a maximum time threshold value set during initialization; if the execution is successful within the maximum time threshold, the eMMC gives a successful feedback to the SSD NVMe Controller, and then marks the Valid bit (Valid) of the successfully executed Command and Data block as invalid (represented by 0) in the mapping Table Command Data Table, and waits for the garbage collection mechanism to clear; if the maximum time threshold is exceeded, the eMMC stops executing the current Command, returns a failure feedback to the SSD NVMe Controller, and then regresses the operation state (operation _ Status) of the Command and the Data block which are executed in failure into a state to be executed (indicated by 0) in the mapping Table Command Data Table, and waits to be selected by other idle eMMC channels for execution.
The NVMe protocol employs multiple command queues (up to 65536 command queues), each of variable command data length (from 512B to 2MB), supports out-of-order execution between commands, and also supports out-of-order transfer of data blocks within commands, while supporting variable weight processing between command queues. On the basis of an RAIM storage architecture, by utilizing the NVMe deep IO queue capacity, the command out-of-order execution capacity and the data block out-of-order transmission capacity, the invention provides a new data transmission optimization method aiming at the problem of data blocking caused by unpredictable Busy time of eMMC, and the SSD performance and the transmission rate are improved.
Referring to fig. 4, for NVMe SSD of PCIe interface, assuming that a command follows 4 logical data blocks, its data transfer includes the following steps:
s10, the Host sends a storage operation Command, the Command and the Data block are transmitted to a Data Buffer of an SSD NVMe Controller, then the SSD NVMe Controller initializes a mapping Table Command Data Table, the operation state (operation _ Status) of the Command and the Data block is initialized to a state to be executed (represented by 0), and the Valid bit (Valid) is initialized to 1;
and S20, judging whether the idle eMMC channel exists or not by the SSD NVMe Controller, and if so, taking out the storage operation command and selecting the corresponding data block thereof to transmit to the corresponding channel. After the command and data blocks are transmitted to the eMMC channel, the SSD NVMe Controller changes the state of the corresponding command and data blocks in the mapping table to a successful execution state (represented by 1);
s30, because the eMMC channels 1, 2, 3, and 4 are all in an idle state at present, it is assumed that the SSD NVMe Controller selects the data blocks 1, 2, 3, and 4 to be transmitted to the idle eMMC channels respectively;
s40, the four eMMC channels start to store and transmit data, Busy time of different channels is different, and a register in each channel can time data transmission and is compared with a maximum time threshold value; at this time, it is assumed that the data of the eMMC channel 1 is blocked due to the fact that Busy time is too long and exceeds a maximum time threshold; the eMMC channels 2, 3 and 4 do not exceed the maximum time threshold value, and data transmission is normally finished;
s50, the eMMC channel 1 stops the execution of the current command due to the blocking of data, and returns a failure feedback to the SSD NVMe Controller; the data storage of the eMMC channel 2, 3 and 4 is finished, a successful feedback is returned to the SSD NVMe Controller, and then the data can be received again after entering an Idle (Idle) state;
s60, after the SSD NVMe Controller receives the feedback of the eMMC channel, because the feedback of the eMMC channel 1 is failed, the operation state (operation _ Status) of the Command and the Data block that are executed in failure is rewound to the state to be executed (represented by 0) in the mapping Table Command Data Table, and waits to be processed by other idle eMMC channels;
s70, since the eMMC channel 2, 3, 4 feedback is successful, the Valid bit (Valid) of the command and data block is set to 0 in the mapping table, and the garbage collection mechanism of the SSD NVMe Controller is waited to clear it;
s80, since the operation state (operation _ Status) of command and data block 1 is reset to 0, it can be processed by the idle eMMC channel. Suppose that at this time, the SSD NVMe Controller gives the data block 1 to the idle eMMC channel 2 for processing, and then proceeds from S20; and so on until all data blocks under the command are successfully stored;
s90, when the data block under the current command is subjected to a storage operation, if there are remaining idle channels in the eMMC channel, the SSD NVMe Controller continues to receive the next command for execution, and does not need to wait for all data blocks under the current command to be stored completely.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A Data transmission optimization method of NVMe storage equipment based on eMMC is characterized by comprising the steps of establishing a mapping Table Command Data Table in an SSD NVMe controller, wherein the Table is a mapping of a Command and a Data block stored in a Data Buffer from a Host, maintains the state of the Command and the Data block in the Data Buffer, and comprises five parts, namely a Command address, a Data block address, an operation state, an effective bit and a reserved bit;
before power-on initialization, setting a maximum time threshold value for execution of an eMMC channel allowed command and data block operation in a configuration file;
when each eMMC acquires a Command and a Data block to be executed from a Data Buffer, a corresponding state of the eMMC is searched in a Command Data Table; only when the operation state is the state to be executed, the command and the data block can be read by the eMMC; when the command and data block is read by the eMMC, the operation state is changed from the to-be-executed state to an execution success state.
2. The data transmission optimization method of the eMMC-based NVMe storage device according to claim 1, specifically comprising the steps of:
in the process of transmitting data by an eMMC channel, an internal register of the eMMC is used for timing the operation execution time of a data block under a current command, and then the time is compared with a maximum time threshold value set during initialization;
if the execution is successful within the maximum time threshold, the eMMC gives a successful feedback to the SSD NVMe controller;
then marking the successfully executed Command and the valid bit of the Data block as invalid in the Command Data Table, and waiting for the garbage recovery mechanism to clear;
if the maximum time threshold is exceeded, the eMMC stops executing the current command and returns a failure feedback to the SSD NVMe controller;
and then, the operation states of the Command and the Data block which are executed in failure are rewound into a state to be executed in the Command Data Table, and the Command and the Data block are waited to be selected and executed by other idle eMMC channels.
3. The data transmission optimization method of the eMMC-based NVMe storage device according to claim 1, specifically comprising the steps of:
s10, the Host sends a storage operation Command, the Command and the Data block are transmitted to a Data Buffer of the SSD NVMe controller, then the SSD NVMe controller initializes a Command Data Table, the operation state of the Command and the Data block is initialized to a state to be executed, and the effective position is initialized to be effective;
s20, the SSD NVMe controller judges whether an idle eMMC channel exists at the moment, if so, the idle eMMC takes out the storage operation command from the Data Buffer and selects the corresponding Data block thereof, and transmits the storage operation command to the corresponding channel; after the Command and the Data block are transmitted to the eMMC channel, the SSD NVMe controller changes the operation state of the corresponding Command and Data block in the Command Data Table into an execution state;
s30, assuming that the current eMMC channels 1-n are all in an idle state, wherein n is a natural number; the SSD NVMe controller selects the data blocks 1-n to be respectively transmitted to the corresponding idle eMMC channels;
s40, the n eMMC channels start to store and transmit data, the busy time of different channels is different, and a register in each channel can time data transmission and is compared with a maximum time threshold value; suppose that data is blocked by the eMMC channel 1 due to the busy time exceeding a maximum time threshold; the eMMC channel 2-n does not exceed the maximum time threshold value, and data transmission is completed;
s50, stopping the execution of the current command due to the data blockage of the eMMC channel 1, and returning a failure feedback to the SSD NVMe controller; after the data storage of the eMMC channel 2-n is finished, a successful feedback is returned to the SSD NVMe controller, and then the data can be received again after entering an idle state;
s60, after receiving the feedback of the eMMC channel, the SSD NVMe controller will rollback the Command executed in failure and the operation state of the Data block to the state to be executed again in the Command Data Table because the feedback of the eMMC channel 1 is failed, and wait for being processed by other idle eMMC channels;
s70, the eMMC channel 2-n is successful in feedback, so that the valid bits of the Command and the Data block are marked as invalid in the Command Data Table, and the garbage collection mechanism of the SSD NVMe controller is waited to clear the invalid bits;
s80, since the operation state of the command and data block 1 is reset to the to-be-executed state, it can be processed by the idle eMMC channel; assuming that the SSD NVMe controller hands the data block 1 to the idle eMMC channel 2 for processing, then the processing is continued from S20 until all the data blocks under the command are successfully stored;
s90, when the data block under the current command is subjected to a storage operation, if there are remaining idle channels in the eMMC channel, the SSD NVMe controller continues to receive the next command for execution, and does not need to wait for all data blocks under the current command to be stored completely.
4. The method of claim 1, wherein the to-be-executed state of the operational state is represented by 0, and the execution success state is represented by 1.
5. The method for data transfer optimization for an eMMC-based NVMe storage device of claim 1, wherein a valid 1 representation and a not valid 0 representation of the valid bit.
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| CN112256601A (en) * | 2020-10-19 | 2021-01-22 | 凌云光技术股份有限公司 | Data access control method, embedded storage system and embedded equipment |
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