KR101162679B1 - Solid state disk using multi channel cache and method for storing cache data using it - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a solid state disk and a cache data storage method for improving the transmission speed of cache data by configuring a plurality of cache data channels.
In the solid state disk of the present invention for achieving the above object, the solid state disk comprising a control unit, a NAND flash memory, a cache memory, a buffer and a host interface, the buffer is composed of two or more, the two or more The buffer, the NAND flash memory, the cache memory, and the host interface each consist of two or more cache data channels independently connected to each other, and the control unit independently of the host computer through the two or more cache data channels according to a predetermined criterion. Send it.

Description

Solid state disk and cache data storage method using multi-channel cache {SOLID STATE DISK USING MULTI CHANNEL CACHE AND METHOD FOR STORING CACHE DATA USING IT}

The present invention relates to a solid state disk and a cache data storage method using a multi-channel cache, and more particularly, to a solid state disk and cache data to improve the transmission speed of the cache data by configuring a plurality of cache data channels It relates to a storage method.

BACKGROUND In general, electronic devices such as computers, digital cameras, PDAs, and various mobile devices are equipped with memory devices for storing data. Such memory devices include DRAM and SRAM, which are volatile memory, in which data is deleted after the power is cut off, and non-volatile memory in which data remains after the power is cut off. ) FLASH, PRAM and FRAM. Among them, flash memory, unlike other memories, has low power consumption and small size, and thus is widely used as a storage device for small electronic devices such as digital cameras, PDAs, and mobile devices.

Recently, researches on solid state disks (SSDs) using NAND flash memory as a large-capacity data storage device replacing hard disks have been actively conducted.

However, since the NAND flash memory has a characteristic that when a write operation is structurally executed, a block having data already stored cannot be overlaid and written again, the updated data is written to a new block and the block in which the old data is stored is deleted. Requires a delete operation. As a result, the write operation may take a long time, and it may take a long time to access recently performed data or frequently used data.

In order to solve such limitations of data transfer rate, that is, slow access speed of NAND flash memory and long read / erase latency, most solid state disks employ a cache system. have. However, the conventional solid state disk employs a single channel cache system described below with reference to FIG. 1.

When the control unit 10 of the solid state disk receives a data transfer command from the host computer, the control unit 10 extracts the target data from the NAND flash memory 20 or the cache memory 30, which is the main storage, and stores the target data in one buffer 40. Transfer to the host computer via the host interface 50. In such a single channel cache system, when the frequency and timing of access of the host interface 50 are frequent or inconsistent, contention of data flushing and filling operations of the NAND flash memory occurs frequently, thereby causing the host interface 50 to fail. There was a problem that the approach speed of the.

In particular, if the data access area through the host interface 50 occurs randomly instead of continuously, the hit ratio of the cache decreases and data flushing and filling operations of the NAND flash frequently occur, thereby increasing the access speed of the host interface. There is a limit of fast access of data in that it is significantly reduced.

The present invention has been proposed to solve the problems of the conventional solid state disk cache system, and employs a multi-channel cache system and improves the transmission speed of the cache data by determining the priority of data transmission for each channel. The main purpose is to make it possible.

In addition, when storing data in a multi-channel cache, each time data is stored in one slice, it is checked whether there is an empty slice in the cache, and when there is no empty slice, the operation of storing the data and flushing another slice are performed. It is another object to further improve the transmission speed of the cache data by always allowing empty slices in the cache by allowing the operations to occur simultaneously.

In the solid state disk using the multi-channel cache of the present invention for achieving the above object, in the solid state disk comprising a control unit, NAND flash memory, cache memory, a buffer and a host interface, the buffer is composed of two or more The at least two buffers, the NAND flash memory, the cache memory, and the host interface are configured with at least two cache data channels independently connected to each other, and the controller controls the host through the at least two cache data channels according to a predetermined criterion. Transfer data independently of the computer.

According to an embodiment, the controller may transmit data through the two or more cache data channels according to a priority determined for each data input / output event.

In another embodiment, the controller may transmit data according to a round robin scheme using alternately two or more cache data channels.

In another embodiment, the controller may bundle a predetermined number of data and transmit the data as mass data.

The cache data storage method using the multi-channel cache of the present invention for achieving the above object is a method for storing the cache data using a solid state disk using a multi-channel cache, comprising the steps of: receiving a data receiving command from a host computer; Searching whether there is a slice in the cache memory having an address that matches an address of a corresponding data that is a target of a reception command; Determining whether there is an empty slice in the cache memory when a slice having an address that matches the address of the data exists in the cache memory; And if there is no empty slice in the cache memory, storing the data in one slice using the one cache data channel and flushing the specific slice using another cache data channel. It includes.

In addition, when there is an empty slice in the cache memory as a result of the determination, the method may further include storing the corresponding data in the slice having the same address using one cache data channel.

Another cache data storage method using a multi-channel cache of the present invention is a method for storing cache data using a solid state disk using a multi-channel cache, comprising the steps of: receiving a data reception command from a host computer; Searching whether there is a slice in the cache memory having an address that matches an address of a corresponding data that is a target of a reception command; If a slice having an address that matches the address of the corresponding data does not exist in the cache memory, receiving and filling data from a NAND flash memory having the address of the corresponding data in a new empty slice; Determining whether there is an empty slice in the cache memory; And if there is no empty slice in the cache memory, storing the corresponding data in the filled slice using one cache data channel and flushing a specific slice using another cache data channel. do.

In addition, when there is an empty slice in the cache memory as a result of the determination, the method may further include storing corresponding data in the filled slice using one cache data channel.

According to the solid state disk using the multi-channel cache of the present invention configured as described above, since a plurality of data can be transferred independently of the host computer through the multi-channel cache according to a predetermined criterion, it is a slow point of NAND flash memory. Speed up data access.

In addition, according to the cache data storage method using the multi-channel cache of the present invention, an empty slice can always be secured in the cache memory, thereby shortening the data flushing time and further improving the data access speed.

In addition, by configuring the slice unit of the cache to the Zone number, Logical Block number, Section number, it is possible to implement the flushing and filling operation of the NAND flash faster.

1 is a block diagram of a solid state disk using a conventional single channel cache.
2 is a block diagram of a solid state disk using the multichannel cache of the present invention.
3 illustrates an example of data transmission using the multichannel cache of the present invention.
Figure 4 is a flow chart illustrating a cache data storage method using a multi-channel cache of the present invention.
5 is a diagram showing a slice configuration of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a solid state disk using a multi-channel cache according to the present invention.

The solid state disk of the present invention is a conventional solid shown in FIG. 1 in that it consists of a control unit 10, a NAND flash memory 20, a cache memory 30, a buffer 41, 42, and a host interface 50. Same as state disk.

However, in the present invention, the buffer is composed of two of the first buffer 41 and the second buffer 42, the two buffers 41 and 42, the NAND flash memory 20, the cache memory 30 and The host interface 50 is composed of cache data channels connected to each other independently. The controller 10 is configured to transmit data independently of a host computer through the two cache data channels according to predetermined criteria.

Although FIG. 2 illustrates a cache data channel using two buffers 41 and 42, the present invention is not limited thereto, and two or more cache data channels may be configured. This multi-channel cache system means that the cache memory 30 and the buffers 41 and 42 are connected independently, and the data transmission paths for the buffers 41 and 42 are configured independently for each interface.

As described above, in order to configure two or more cache data channels, the NAND flash memory 20 is configured such that a plurality of NAND flash memories are operated by grouping each cache data channel, and the cache memory 30 is an SDRAM. Is connected to each cache data channel using high speed memory such as DDR, DDR2, and FRAM, and the host interface 50 uses each communication data channel using various communication interfaces such as ATA, SATA, SAS, USB, and PCI EXPRESS. Connected with

In order to effectively process data using the multi-channel cache system configured as described above, it is preferable to process an event according to a predetermined criterion as follows.

First, the controller 10 transmits data through two or more cache data channels according to priorities determined for each data input / output event. For example, each channel is controlled to process a refresh event before transmission of general data (for example, refresh event-> data processing in channel 1-> data processing in channel 2).

In addition, the control unit 10 transmits data according to a round robin method using alternately two or more cache data channels. For example, if data needs to be transmitted over two cache data channels within a single bus, control to use both channels alternately (for example, channel 1-> channel 2-> channel 1-> channel 2).

In addition, when transmitting a large amount of data through two or more cache data channels in a single bus, the controller 10 bundles the data of each channel into a certain number of data and transmits the data as mass data. When mass data transmission of the corresponding cache data channel is completed, the next mass data or other event is processed by the above priority, round robin method, and the like.

3 shows an example of processing data according to the above three criteria.

Each of the cache data channels 1 and 2 has three pieces of mass data, and the data transmission order of each channel is determined by a round robin method. If the memory is SDRAM or DDR, the refresh operation must be executed for a certain period, and this refresh event has the highest priority.

First, when a data transmission event of the cache data channel 2 occurs, the control unit 10 transmits the mass data # 1, # 2 of the cache data channel 2 in order. In the process of transmitting the mass data # 2, the data transmission event of the cache data channel 1 and the memory refresh event occurred in sequence. At this time, the controller 10 first performs the refresh event having the highest priority after the transmission operation for the mass data # 2 of the channel 2 is completed. When the refresh event is completed, the mass data # 1 of channel 1 is transmitted according to the round robin method. When the transmission of the mass data # 1 of the channel 1 is completed, the mass data # 3 of the channel 2 is transmitted in a round robin manner. As a result, since all data transfer of channel 2 is completed, the remaining mass data # 2 and # 3 of channel 1 are transmitted in order.

Hereinafter, a method of storing cache data using a solid state disk using a multichannel cache will be described in detail with reference to FIGS. 4 and 5. The cache memory of the present invention is divided into a plurality of slices and used, and is configured to process two or more events at the same time through independent cache data channels.

As shown in FIG. 4, the controller receives a data reception command from the host computer (S100).

The controller searches whether the slice having an address that matches the address of the corresponding data that is the target of the reception command exists in the cache memory. This search process refers to extracting a zone number, a logical block number, and a section number constituting the address of the data by referring to a logical block allocation table (LBA) (S110), a corresponding zone number, a logical block number, In operation S120, it is determined whether the slice A having the same section number exists.

As a result of the determination of S120, when slice A having an address corresponding to the address of the data exists in the cache memory, it is determined again whether there is an empty slice in the cache memory (S130).

As a result of the determination of S130, when there is an empty slice in the cache memory, the operation is completed by transmitting data to slice A having an address that matches the address of the corresponding data using one cache data channel (S140). On the other hand, if there is no empty slice in the cache memory as a result of the determination of S130, the corresponding data is transmitted to the slice A using one cache data channel and the slice B selected according to a predetermined criterion using another cache data channel. Flush (S150).

As described above, according to the present invention, each time data is transferred to the cache memory, it is checked whether there is an extra slice in the cache memory, and when there is no spare slice, the corresponding data is transmitted using two or more independent cache data channels. At the same time, flushing a specific slice is performed simultaneously. As a result, there is always an empty slice in the cache memory, thereby improving the overall data transfer rate.

In the conventional single cache channel system, if there is no empty slice in the cache memory, one slice is flushed prior to transmitting the data to be received and the corresponding data stored in the NAND flash memory is transferred to the flushed slice. Since the data can be stored in the cache memory only until the filling operation is completed, there is a problem that the overall data transfer speed is significantly lowered. The present invention solves the problem of the conventional single cache channel system by storing two or more independent cache data channels and storing the received instruction data and flushing other slices at the same time so that there is always an empty slice in the cache memory.

Another embodiment of a cache data storage method using a multi-channel cache according to the present invention will be described.

First, the controller receives a data receiving command from the host computer (S100).

The controller searches whether the slice having an address that matches the address of the corresponding data that is the target of the reception command exists in the cache memory. This search process refers to extracting a zone number, a logical block number, and a section number constituting the address of the data by referring to a logical block allocation table (LBA) (S110), a corresponding zone number, a logical block number, In operation S120, it is determined whether the slice A having the same section number exists.

As a result of the determination of S120, when slice A having an address that matches the address of the data does not exist in the cache memory, data is received from a NAND flash memory having the address of the data in a new, empty slice B and is filled ( S200).

When the data filling operation is completed, it is determined whether there is an empty slice in the cache memory (S210). As a result of the determination in S210, when there is an empty slice in the cache memory, the operation is completed by storing the corresponding data in the filled slice B using one cache data channel (S220). On the other hand, if there is no empty slice in the cache memory as a result of the determination of S210, the slice is determined according to a predetermined criterion using the other cache data channel while storing the corresponding data in the filled slice using one cache data channel. C is flushed (S230).

In this configuration, since there is always an empty slice flushed in the cache memory, data can be stored only after the filling operation for the data is transmitted when new data is transmitted, and as a result, the data transfer speed can be improved. Same as one.

As another technical configuration for improving the data transfer speed, as shown in FIG. 5, the slice address of the cache memory may be configured with a zone number, a logical block number, and a section number. In the past, one slice address was subdivided into only a zone number and a logical block number. For example, one logical block is composed of 128 pages having a size of 4 Kbytes and has a total size of 512 Kbytes, whereas the Section of the present invention has a total size of 16 Kbytes because it consists of 4 pages having the same size. .

Therefore, in the conventional cache system, flushing and filling operations occur in Logical Block units (512 Kbytes), while flushing and filling operations occur in Section units (16 Kbytes), which is the minimum unit, so that time is shortened and high-speed data transmission is performed. It becomes possible.

Although the present invention has been described in detail using the preferred embodiments, the scope of the present invention is not limited to the specific embodiments, and should be interpreted by the appended claims. It will also be appreciated that many modifications and variations will be apparent to those skilled in the art without departing from the scope of the present invention.

10: control unit 20: NAND flash memory
30: cache memory 40: buffer
41: first buffer 42: second buffer
50: host interface

Claims (10)

A solid state disk comprising a control unit, a NAND flash memory, a cache memory, a buffer, and a host interface,
The buffer consists of two or more,
The two or more buffers, the NAND flash memory, the cache memory, and the host interface are each composed of two or more cache data channels independently connected.
And the control unit transmits data independently from a host computer through the two or more cache data channels according to a predetermined criterion. The method according to claim 1,
And the control unit transmits data through the two or more cache data channels according to a priority determined for each data input / output event. The method according to claim 1,
The control unit transmits data according to a round robin method using alternating two or more cache data channels. The method according to claim 2 or 3,
The control unit is a solid state disk using a multi-channel cache, characterized in that for binding a certain number of data to transmit as mass data (Mass data). A method of storing cache data using a solid state disk using a multichannel cache according to claim 1,
Receiving a data receiving command from a host computer;
Searching whether there is a slice in the cache memory having an address that matches an address of a corresponding data that is a target of a reception command;
Determining whether there is an empty slice in the cache memory when a slice having an address that matches the address of the data exists in the cache memory; And
If there is no empty slice in the cache memory as a result of the determination, storing the corresponding data in one slice using the one cache data channel and flushing the specific slice using the other cache data channel; Cache data storage method using a multi-channel cache comprising a. The method according to claim 5,
If there is an empty slice in the cache memory as a result of the determination, storing the cache data using the multi-channel cache, characterized in that the corresponding data is stored in the slice that matches the address using one cache data channel. Way. The method according to claim 5 or 6,
The address of the slice is a cache data storage method using a multi-channel cache, characterized in that consisting of the Zone number, Logical Block number, Section number. A method of storing cache data using a solid state disk using a multichannel cache according to claim 1,
Receiving a data receiving command from a host computer;
Searching whether there is a slice in the cache memory having an address that matches an address of a corresponding data that is a target of a reception command;
If a slice having an address that matches the address of the corresponding data does not exist in the cache memory, receiving and filling data from a NAND flash memory having the address of the corresponding data in a new empty slice;
Determining whether there is an empty slice in the cache memory; And
If there is no empty slice in the cache memory as a result of the determination, storing the corresponding data in the filled slice using one cache data channel and flushing a specific slice using another cache data channel; Cache data storage method using a multi-channel cache, characterized in that. The method according to claim 8,
If there is an empty slice in the cache memory as a result of the determination, storing the corresponding data in the filled slice using one cache data channel, further comprising: storing the cache data using the multi-channel cache . The method according to claim 8 or 9,
The address of the slice is a cache data storage method using a multi-channel cache, characterized in that consisting of the Zone number, Logical Block number, Section number.

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