CN113573460A - Differential via structure - Google Patents
Differential via structure Download PDFInfo
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- CN113573460A CN113573460A CN202010357840.9A CN202010357840A CN113573460A CN 113573460 A CN113573460 A CN 113573460A CN 202010357840 A CN202010357840 A CN 202010357840A CN 113573460 A CN113573460 A CN 113573460A
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- Prior art keywords
- solid metal
- metal wall
- hole
- differential
- via hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A differential via structure, comprising: the anti-bonding pad is arranged on the reference layer of the dielectric plate; the first through hole is formed in the anti-bonding pad and internally coated with a metal medium; the second through hole is formed in the anti-bonding pad and internally coated with a metal medium; a first solid metal wall disposed outside the first via; and the second solid metal wall is arranged on the outer side of the second via hole, so that the insertion loss is reduced, the impedance matching of the via hole is realized, and the transmission efficiency of high-speed signals is improved.
Description
Technical Field
The invention relates to the technical field of dielectric plate manufacturing, in particular to a differential via hole structure.
Background
Vias are an important factor in high-speed dielectric board design, and the via design becomes one of the key factors that restrict the high-speed dielectric board design, such as the failure of the whole design due to improper handling. The via hole is a conductor for connecting different layers of wiring in the multilayer dielectric plate layer, and when the frequency is low, the via hole does not influence signal transmission, but along with the increase of the frequency, the existence of the via hole can influence the integrity of signals. When the differential via hole is designed in the prior art, at most 6 bilateral symmetry via holes are arranged around the signal via hole to shorten the high-frequency return path and achieve high-frequency loss compensation and via hole impedance matching, but the bilateral symmetry via holes occupy more wiring positions of the dielectric plate, and the high-frequency loss compensation and the via hole impedance matching are poor.
Disclosure of Invention
In view of the above, it is desirable to provide a differential pair via, which reduces insertion loss and achieves via impedance matching, thereby improving high-speed signal transmission efficiency.
The differential via structure provided by an embodiment of the present invention includes:
the anti-bonding pad is arranged on the reference layer of the dielectric plate;
the first through hole is formed in the anti-bonding pad and internally coated with a metal medium;
the second through hole is formed in the anti-bonding pad and internally coated with a metal medium;
a first solid metal wall disposed outside the first via;
and the second solid metal wall is arranged on the outer side of the second through hole.
Preferably, the outer side of the first via hole is the left side of a central connecting line of the first via hole and the second via hole;
the outer side of the second via hole is the right side of a midline connection line of the first via hole and the second via hole.
Preferably, the first via hole penetrates through each reference layer of the dielectric plate;
the second via hole penetrates through each reference layer of the dielectric plate.
Preferably, the first solid metal wall penetrates through each reference layer of the medium plate;
the second solid metal wall penetrates through each reference layer of the medium plate.
Preferably, the first solid metal wall is in conduction with a ground plane of each reference layer of the dielectric slab;
the second solid metal wall is conducted with the ground plane of each reference layer of the dielectric plate.
Preferably, the first solid metal wall is formed by drilling a hollow hole in the dielectric slab and filling the hollow hole with a metal medium;
the second solid metal wall is formed by drilling a hollow hole in the dielectric slab and filling the hollow hole with a metal dielectric.
Preferably, the first solid metal wall and the second solid metal wall are circular arcs with preset radiuses.
Preferably, the first solid metal wall and the second solid metal wall are U-shaped structures with openings of a predetermined size facing the first via hole and the second via hole.
Preferably, the first via is electrically connected to a first signal line;
the second via hole is electrically connected to a second signal line; wherein the content of the first and second substances,
the first signal line and the signal line form a differential pair.
Compared with the prior art, the differential via hole structure provided by the embodiment of the invention has the advantages that the first solid metal wall is arranged on the outer side of the first via hole, the second solid metal wall is arranged on the outer side of the second via hole, the insertion loss is reduced, the impedance matching of the via holes is realized, and the transmission efficiency of high-speed signals is improved.
Drawings
Fig. 1 is a schematic top view of a differential via structure according to an embodiment of the present invention.
FIG. 2 is a schematic side view of a differential via structure according to an embodiment of the present invention.
Fig. 3 is a schematic top view of another embodiment of a differential via structure according to the present invention.
FIG. 4 is a graph comparing S-parameters for the differential via structure of the present invention with the first solid metal wall and the second solid metal wall having thicknesses of 4mil and 1 mil.
FIG. 5 is a graph comparing S-parameters for the differential via structure of the present invention with the first solid metal wall and the second solid metal wall having thicknesses of 4mil and 1 mil.
FIG. 6 is a graph comparing impedances at 4mil and 1mil thicknesses for the first solid metal wall and the second solid metal wall of the differential via structure of the present invention.
FIG. 7 is a schematic diagram of a prior art differential via.
Fig. 8 is a schematic structural diagram of another differential via in the prior art.
FIG. 9 is a comparison of S-parameters for a differential via structure designed in accordance with the present invention and prior art.
FIG. 10 is a comparison of S-parameters for a differential via structure designed in accordance with the present invention and prior art.
FIG. 11 is a graph comparing impedances of prior art and differential via structures designed in accordance with the present invention.
Description of the main elements
Differential via structure 10
Anti-pad 100
First via 101
Second via 102
First solid metal wall 103
Second solid metal wall 104
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic top view of a structure of a differential pair via 10 according to an embodiment of the present invention. In this embodiment, the differential pair via 10 includes an antipad 100, a first via 101, a second via 102, a first solid metal wall 103, and a second solid metal wall 104. The differential via structure 10 is disposed on a dielectric board 1, and the dielectric board 1 is typically a PCB board.
In the present embodiment, the anti-pad 100 is provided on the reference layer of the dielectric board 1. The first via hole 101 is disposed on the anti-pad 100 and internally coated with a metal medium. And the second via hole 102 is arranged on the anti-pad 100 and internally coated with a metal medium. The first solid metal wall 103 is disposed outside the first via hole 101. And a second solid metal wall 104 disposed outside the second via 102. The outer side of the first via hole 101 is the left side of the central connection line of the first via hole 101 and the second via hole 102, and the outer side of the second via hole 102 is the right side of the central connection line of the first via hole 101 and the second via hole 102. The first via 101 may be connected to the first signal line 20, and the second via 102 is electrically connected to the second signal line 30, wherein the first signal line and the signal line form a differential pair. Typically, a differential pair transmits a high-speed signal.
In the present embodiment, the dielectric sheet 1 includes at least two reference layers 11. Referring to fig. 2, fig. 2 is a schematic structural side view of an embodiment of a differential pair via 10 according to the present invention. As shown in fig. 2, the dielectric board 1 includes a plurality of reference layers 11, it is understood that the illustration in fig. 2 is only for better explaining the present invention, and not as a limitation of the present invention, and the number of reference layers 11 of the dielectric board 1 may be determined according to the actual circuit wiring requirement. An anti-pad 100 is disposed on each reference layer 11 of the dielectric board 1. The first via 101 penetrates each reference layer 11 of the dielectric board 1, and similarly, the second via 102 penetrates each reference layer 11 of the dielectric board 1, so that the signal lines connected with the first via 101 and the second via 102 can be routed on any layer as required. The first solid metal wall 103 penetrates each reference layer 11 of the dielectric board 1, and similarly, the second solid metal wall 104 penetrates each reference layer 11 of the dielectric board 1, so that the first solid metal wall 103 and the second solid metal wall 104 can respectively cover the first via hole 101 and the second via hole 102 in each reference layer 11.
In the present embodiment, the first solid metal wall 103 is electrically connected to a ground plane (not shown) of each reference layer 11 of the dielectric plate 1. The second solid metal wall 104 is electrically connected to a ground plane (not shown) of each reference layer 11 of the dielectric board 1.
In the present embodiment, the first solid metal wall 103 is formed by drilling a cavity in the dielectric slab 1 and filling the cavity with a metal dielectric. Similarly, the second solid metal wall 104 is formed by drilling a hollow in the dielectric slab 1 and filling the hollow with a metal dielectric. In the present embodiment, a cavity is drilled in the dielectric plate 1 using a laser drilling technique. In the present embodiment, the first solid metal wall 103 and the second solid metal wall 104 are circular arcs with a predetermined radius, and semi-surround the first via 101 and the second via 102.
As shown in fig. 3, in another embodiment of the invention, the first solid metal wall 103 and the second solid metal wall 104 are U-shaped structures with openings of a predetermined size facing the first via 101 and the second via 102, and semi-surround the first via 101 and the second via 102. In other embodiments of the present invention, the first solid metal wall 103 and the second solid metal wall 104 may have other shapes, which is not limited herein. In one embodiment of the present invention, the thickness of the first solid metal wall 103 and the second solid metal wall 104 is 4mil, but in other embodiments of the present invention, the thickness can be set according to practical applications. Referring to fig. 4-6, fig. 4 and 5 are S parameter comparison graphs for the first solid metal wall 103 and the second solid metal wall 104 with thicknesses of 4mil and 1mil, and fig. 6 is an impedance comparison graph for the first solid metal wall 103 and the second solid metal wall 104 with thicknesses of 4mil and 1mil, which shows that the S parameter and the impedance difference are very small for the first solid metal wall 103 and the second solid metal wall 104 with thicknesses of 4mil and 1 mil.
Referring to fig. 7, fig. 7 is a schematic diagram of a differential via in the prior art. As shown, no vias are disposed around the differential vias.
Referring to fig. 8, fig. 8 is a schematic structural diagram of another differential via in the prior art. As shown in fig. 8, 3 vias are respectively disposed on two sides of the differential via.
Referring to fig. 9-11, fig. 9 and 10 are S-parameter comparison graphs of a prior art differential via structure (shown in fig. 7-8) and a differential via structure designed according to the present invention, and fig. 11 is an impedance comparison graph of a prior art differential via structure (shown in fig. 7-8) and a differential via structure designed according to the present invention. As shown in the figure, the differential via structure designed by the invention is superior to the prior art in Insertion loss (Insertion loss) at high frequency, and is obviously superior to the prior art in reflection loss (Return loss) because the average of the invention is lower than 40 dB. The impedance of the via hole is controlled within +/-2 ohm on the impedance comparison, which is obviously better than the impedance of +/-10 ohm in the prior art.
Compared with the prior art, the differential via hole structure provided by the embodiment of the invention has the advantages that the first solid metal wall is arranged on the outer side of the first via hole, the second solid metal wall is arranged on the outer side of the second via hole, the insertion loss is reduced, the impedance matching of the via holes is realized, and the transmission efficiency of high-speed signals is improved.
It will be appreciated by those skilled in the art that the above embodiments are only for illustrating the present invention and are not to be used as a limitation of the present invention, and that suitable modifications and variations of the above embodiments are within the scope of the present invention as claimed in the appended claims, as long as they fall within the true spirit of the present invention.
Claims (10)
1. The utility model provides a differential via structure sets up on the dielectric plate, its characterized in that includes:
the anti-bonding pad is arranged on the reference layer of the dielectric plate;
the first through hole is formed in the anti-bonding pad and internally coated with a metal medium;
the second through hole is formed in the anti-bonding pad and internally coated with a metal medium;
a first solid metal wall disposed outside the first via;
and the second solid metal wall is arranged on the outer side of the second through hole.
2. The differential via structure of claim 1, wherein:
the outer side of the first via hole is the left side of a central connecting line of the first via hole and the second via hole;
the outer side of the second via hole is the right side of a midline connection line of the first via hole and the second via hole.
3. The differential via structure of claim 1, wherein:
the dielectric plate comprises at least two reference layers;
the anti-welding pad is arranged on each reference layer of the medium plate.
4. The differential via structure of claim 2, wherein:
the first via hole penetrates through each reference layer of the dielectric plate;
the second via hole penetrates through each reference layer of the dielectric plate.
5. The differential via structure of claim 1, wherein:
the first solid metal wall penetrates through each reference layer of the dielectric plate;
the second solid metal wall penetrates through each reference layer of the medium plate.
6. The differential via structure of claim 5, wherein:
the first solid metal wall is conducted with the ground plane of each reference layer of the dielectric plate;
the second solid metal wall is conducted with the ground plane of each reference layer of the dielectric plate.
7. The differential via structure of claim 5, wherein:
the first solid metal wall is formed by drilling a hollow hole in the dielectric slab and filling the hollow hole with a metal medium;
the second solid metal wall is formed by drilling a hollow hole in the dielectric slab and filling the hollow hole with a metal dielectric.
8. The differential via structure of claim 1, wherein:
the first solid metal wall and the second solid metal wall are arc-shaped with a preset radius.
9. The differential via structure of claim 1, wherein:
the first solid metal wall and the second solid metal wall are U-shaped structures with openings of preset sizes facing the first via hole and the second via hole.
10. The differential via structure of claim 1, wherein:
the first via hole is electrically connected to a first signal line;
the second via hole is electrically connected to a second signal line; wherein the content of the first and second substances,
the first signal line and the signal line form a differential pair.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010357840.9A CN113573460A (en) | 2020-04-29 | 2020-04-29 | Differential via structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010357840.9A CN113573460A (en) | 2020-04-29 | 2020-04-29 | Differential via structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113573460A true CN113573460A (en) | 2021-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010357840.9A Pending CN113573460A (en) | 2020-04-29 | 2020-04-29 | Differential via structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020179332A1 (en) * | 2001-05-29 | 2002-12-05 | Mitsubishi Denki Kabushiki Kaisha | Wiring board and a method for manufacturing the wiring board |
| CN107969065A (en) * | 2017-11-02 | 2018-04-27 | 四川九洲电器集团有限责任公司 | A kind of printed circuit board (PCB) |
| CN111050493A (en) * | 2018-10-12 | 2020-04-21 | 中兴通讯股份有限公司 | Method for determining shape of via hole reverse pad and printed circuit board |
-
2020
- 2020-04-29 CN CN202010357840.9A patent/CN113573460A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020179332A1 (en) * | 2001-05-29 | 2002-12-05 | Mitsubishi Denki Kabushiki Kaisha | Wiring board and a method for manufacturing the wiring board |
| CN107969065A (en) * | 2017-11-02 | 2018-04-27 | 四川九洲电器集团有限责任公司 | A kind of printed circuit board (PCB) |
| CN111050493A (en) * | 2018-10-12 | 2020-04-21 | 中兴通讯股份有限公司 | Method for determining shape of via hole reverse pad and printed circuit board |
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| PB01 | Publication | ||
| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 530033 plant B of Foxconn Nanning science and Technology Park, No. 51 Tongle Avenue, Jiangnan District, Nanning City, Guangxi Zhuang Autonomous Region Applicant after: Nanning Fulian Fugui Precision Industry Co.,Ltd. Address before: 530007 the Guangxi Zhuang Autonomous Region Nanning hi tech Zone headquarters road 18, China ASEAN enterprise headquarters three phase 5 factory building Applicant before: NANNING FUGUI PRECISION INDUSTRIAL Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211029 |
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| RJ01 | Rejection of invention patent application after publication |