CN113572435A - C-band low-temperature low-noise amplifier for quantum computation - Google Patents
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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Abstract
The invention discloses a C-band low-temperature low-noise amplifier for quantum computation, which belongs to the technical field of microwave devices and comprises an external input micro-strip matching circuit and a broadband monolithic low-noise amplifier, wherein the external input micro-strip matching circuit and the broadband monolithic low-noise amplifier are cascaded through a gold wire W2, and the broadband monolithic low-noise amplifier adopts a three-level mHEMT (metal high electron mobility transistor) tube core circuit structure. The invention adopts the form of a hybrid microwave integrated circuit, the whole amplifier circuit adopts an external circuit structure except for the first-stage input matching, and other circuits adopt microwave monolithic integrated circuits, thereby reducing the circuit volume and expanding the bandwidth.
Description
Technical Field
The invention relates to the technical field of microwave devices, in particular to a C-band low-temperature low-noise amplifier for quantum computation.
Background
For superconducting quantum computer systems, one of the key components is the low temperature electronics capable of operating at-269 c for qubit readout. Because the qubits emit very weak radio-frequency signals, in order to avoid interference of thermal noise on quantum states, the signals enter a low-temperature low-noise amplifier, and the weak signals can be amplified and enhanced under the condition of introducing extremely low noise, so that the qubits are easier to read. Not only quantum computers benefit from low temperature low noise amplifiers, but also radio astronomical telescopes, deep space communication networks and other systems are using them.
The critical performance noise temperature of the low noise amplifier is mainly determined by the noise impedance matching of the input circuit and the first stage active HEMT device. Usually, the first-stage input matching circuits of the MMIC LNA are integrated on a single chip, and passive devices such as capacitors and inductors on the single chip have low Q values, so that broadband matching can be realized, but the loss is large, and the further reduction of low-noise amplification noise indexes is influenced.
At present, a low-temperature low-noise amplifier basically adopts a discrete device microwave circuit form, except for large volume, parasitic parameters in the circuit are also large, and the low-temperature low-noise amplifier has great influence on the bandwidth and high-frequency performance of the circuit. In addition, the low-temperature amplifier is generally designed by adopting a GaAs HEMT field tube, and the noise performance of the amplifier designed based on the process is poor at low temperature.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a C-band low-temperature low-noise amplifier which is low in noise, small in size and easy to integrate.
In order to achieve the above object, the present invention provides a C-band low-temperature low-noise amplifier for quantum computation, comprising: the external input micro-strip matching circuit and the broadband monolithic low-noise amplifier are cascaded through a gold wire W2, and the broadband monolithic low-noise amplifier adopts a three-level mHEMT tube core circuit structure.
Further, the external input microstrip matching circuit comprises a series matching capacitor C1, a first bias circuit and microstrip lines TL1 and TL 2; the microstrip line TL1 is connected in series with the capacitor C1, the capacitor C1 is connected with the microstrip line TL2 through the gold wire W1 and then connected with the first bias circuit, and the microstrip line TL2 is cascaded with the broadband monolithic low noise amplifier through the gold wire W2.
Further, the first bias circuit comprises a microstrip line TL3, filter capacitors C2, C3 and a resistor R1, the microstrip line TL3 is connected to a connection line of the capacitor C1 and the microstrip line TL2, the resistor R1 is connected in series with the microstrip line TL3, and the filter capacitors C2 and C3 are connected in parallel at two ends of the resistor R1.
Further, the broadband monolithic low noise amplifier includes a first level die T1, a second level die T2, and a third level die T3; the grid electrode of the first-level die T1 is connected to the external input microstrip matching circuit through the gold wire W2, the source electrode is grounded through a microstrip line TL4, and the drain electrode is connected with the grid electrode of the second-level die T2 through a DC blocking capacitor C5; the source electrode of the second-level die T2 is grounded through a microstrip line TL5 and a microstrip line TL6, and the drain electrode of the second-level die T2 is connected with the gate electrode of the third-level die T3 through a blocking capacitor C8; the source of the third-level die T3 is grounded through the microstrip line TL7 and the microstrip line TL8, and the drain is connected to the output PAD through the dc blocking capacitor C11 and the resistor R9.
Further, the broadband monolithic low noise amplifier further comprises a second bias circuit, a third bias circuit, a fourth bias circuit, a fifth bias circuit and a sixth bias circuit, wherein the second bias circuit comprises a resistor R2, an inductor L1 and a capacitor C4, the third bias circuit comprises resistors R3 and R4 and a capacitor C6, the fourth bias circuit comprises a resistor R5 and a capacitor C7, the fifth bias circuit comprises resistors R6 and R7 and a capacitor C9, and the sixth bias circuit comprises a resistor R8, an inductor L2 and a capacitor C10;
the first bias circuit is used for providing a gate voltage Vg1 of the first-level die T1, the second bias circuit is used for providing a drain voltage Vd1 of the first-level die T1, the second bias circuit is connected with an external power supply through a PAD1, the third bias circuit is used for providing a gate voltage Vg2 of the second-level die T2, the third bias circuit is connected with the external power supply through a PAD4, the fourth bias circuit is used for providing a drain voltage Vd2 of the second-level die T2 and is connected with the external power supply through a PAD2, the fifth bias circuit is used for providing a gate voltage Vg3 of the third-level die T3 and is connected with the external power supply through a PAD5, and the sixth bias circuit is used for providing a drain voltage Vd3 of the third-level die T3 and is connected with the external power supply through a PAD 3.
Further, the capacitors C1, C2 and C3 are all chip capacitors, and the resistor R1 is a thin film resistor.
Further, the gate index of the first-level die T1 is 2, and the total gate width is 200 um; the gate indices of the second level and third level die T2 and T3 are both 2, and the total gate width is 100 um.
Furthermore, the broadband monolithic low-noise amplifier is prepared by adopting a 70nm GaAs mHEMT process, and the thickness of the circuit board is 100 um.
Further, an output PAD of the broadband monolithic low noise amplifier is connected with a microstrip line TL9 through a gold wire W3.
Compared with the prior art, the invention has the following technical effects: the invention adopts the form of a hybrid microwave integrated circuit, greatly reduces the volume of an amplifier module, adopts an external circuit structure except for the first-stage input matching of the whole amplifier circuit, adopts microwave monolithic integrated circuits except for the first-stage input matching, reduces the circuit volume and expands the bandwidth; the input matching circuit is placed outside the monolithic low-noise amplifier, and the performance of the input matching circuit in critical indexes such as noise in the working frequency band range is ensured by selecting a high Q value input matching circuit.
Drawings
The following detailed description of embodiments of the invention refers to the accompanying drawings in which:
FIG. 1 is a circuit configuration diagram of a C-band low-temperature low-noise amplifier for quantum computation;
FIG. 2 is a schematic diagram of a measured noise temperature curve of a low temperature low noise amplifier;
fig. 3 is a schematic diagram of the measured gain curve of the low temperature low noise amplifier.
Detailed Description
To further illustrate the features of the present invention, refer to the following detailed description of the invention and the accompanying drawings. The drawings are for reference and illustration purposes only and are not intended to limit the scope of the present disclosure.
As shown in fig. 1, the present embodiment discloses a C-band low-temperature low-noise amplifier for quantum computation, including: the external input micro-strip matching circuit and the broadband monolithic low-noise amplifier are cascaded through a gold wire W2, and the broadband monolithic low-noise amplifier adopts a three-level mHEMT tube core circuit structure.
It should be noted that, in this embodiment, a Hybrid Microwave Integrated Circuit (HMIC) form is adopted, and the whole amplifier circuit except for the first-stage input matching adopts an external circuit structure, and all other forms adopt a Microwave Monolithic Integrated Circuit (MMIC) form, so that the size is reduced, and the bandwidth is expanded.
As a further preferable technical solution, the external input microstrip matching circuit includes a series matching capacitor C1, a first bias circuit, and microstrip lines TL1, TL 2; the microstrip line TL1 is connected in series with the capacitor C1, the capacitor C1 is connected with the microstrip line TL2 through the gold wire W1 and then connected with the first bias circuit, and the microstrip line TL2 is cascaded with the broadband monolithic low noise amplifier through the gold wire W2.
As a further preferable technical solution, the first bias circuit includes a microstrip line TL3, filter capacitors C2, C3 and a resistor R1, the microstrip line TL3 is connected to a connection line between the capacitor C1 and the microstrip line TL2, the resistor R1 is connected in series with the microstrip line TL3, and the filter capacitors C2 and C3 are connected in parallel at two ends of the resistor R1.
It should be noted that, in the embodiment, the serial matching capacitor C1 is a chip capacitor with a size of 0.5 × 0.5 × 0.1mm, and a capacitance value is 100 pF; the parallel filter capacitors C2 and C3 are chip capacitors with the size of 0.5 multiplied by 0.1mm, and the capacitance values are 22pF and 330pF respectively; the resistor R1 is a thin film resistor with 0402 packaging size, and the resistance value is 10 omega; the impedance of the microstrip line TL1 is 50 omega, and the length of the line is about 2 mm; the impedance of the microstrip line TL2 is 120 omega, and the length of the line is about 6 mm; the impedance of the microstrip line TL3 is 120 omega, and the length of the line is about 4 mm; the microstrip substrate is a high-frequency microwave board with the thickness of 0.254mm and the dielectric constant of 2.2; the gold wire W1 connected with the micro-strip TL2 by the capacitor C1 is 1mil in diameter and about 200um in length.
In this embodiment, the working frequency of the broadband monolithic low-noise amplifier can cover 1-18 GHz, the input end matching circuit is cascaded with the broadband monolithic low-noise amplifier through a gold wire, matching optimization is performed on a first-stage tube core of the broadband monolithic low-noise amplifier through micro-strips TL1, TL2 and TL3, capacitors C1, C2, C3 and a resistor R1 in the circuit, and indexes such as frequency bandwidth, noise, echo loss and the like of the low-noise amplifier can be optimized by adjusting the impedance and the length of the micro-strip lines TL2 and TL3, so that optimization can be performed on key indexes such as noise in a specific frequency range.
It should be noted that the external input microstrip matching circuit designed in this embodiment includes microstrip lines TL1, TL2, and TL3 fabricated by using a high-frequency microwave substrate, where TL1 and TL2 match the optimal noise impedance of the monolithic chip to 50 ohms of the system through high-low impedance transformation, TL3 may be equivalent to inductance, so as to avoid leakage of high-frequency signals into the bias circuit; one end of a series chip capacitor C1 is bonded on the microstrip TL1, and the other end is bonded on the TL2 through a gold wire, so that radio frequency matching is realized while direct-current voltage is isolated. The whole input matching circuit realizes the optimal noise matching aiming at the first-stage mHEMT tube core in the C wave band by adopting the high-Q-value microwave device circuit, and simultaneously provides grid bias voltage for the first-stage tube core.
As a further preferred technical solution, the broadband monolithic low noise amplifier includes a first-level die T1, a second-level die T2, and a third-level die T3; the grid electrode of the first-level die T1 is connected to the external input microstrip matching circuit through the gold wire W2, the source electrode is grounded through a microstrip line TL4, and the drain electrode is connected with the grid electrode of the second-level die T2 through a DC blocking capacitor C5; the source electrode of the second-level die T2 is grounded through a microstrip line TL5 and a microstrip line TL6, and the drain electrode of the second-level die T2 is connected with the gate electrode of the third-level die T3 through a blocking capacitor C8; the source of the third-level die T3 is grounded through the microstrip line TL7 and the microstrip line TL8, and the drain is connected to the output PAD through the dc blocking capacitor C11 and the resistor R9.
As a further preferable technical solution, the wideband monolithic low noise amplifier further includes a second bias circuit, a third bias circuit, a fourth bias circuit, a fifth bias circuit and a sixth bias circuit, the second bias circuit includes a resistor R2, an inductor L1 and a capacitor C4, the third bias circuit includes resistors R3, R4 and a capacitor C6, the fourth bias circuit includes a resistor R5 and a capacitor C7, the fifth bias circuit includes resistors R6, R7 and a capacitor C9, and the sixth bias circuit includes a resistor R8, an inductor L2 and a capacitor C10;
the first bias circuit is used for providing a gate voltage Vg1 of the first-level die T1, the second bias circuit provides a drain voltage Vd1 of the first-level die T1 and the second bias circuit is connected with an external power supply through a PAD1, the third bias circuit provides a gate voltage Vg2 of the second-level die T2 and the third bias circuit is connected with the external power supply through a PAD4, the fourth bias circuit provides a drain voltage Vd2 of the second-level die T2 and is connected with the external power supply through a PAD2, the fifth bias circuit provides a gate voltage Vg3 of the third-level die T3 and is connected with the external power supply through a PAD5, and the sixth bias circuit provides a drain voltage Vd3 of the third-level die T3 and is connected with the external power supply through a PAD 3; the output PAD of the broadband monolithic low noise amplifier is connected with a microstrip line TL9 through a gold wire W3.
It should be noted that the gate width of the level one die T1 in this embodiment is 2 × 100um, and the gate widths of the level two die T2 and the level three die T3 are both 2 × 50 um. The gate of the first level die T1 is connected to an external input microstrip matching circuit through an input PAD and gold wire W2. The amplifier circuit uses a source negative feedback circuit, wherein the source of the first-level die T1 is grounded through a microstrip TL4, the source of the second-level die T2 is grounded through microstrips TL5 and TL6, and the source of the third-level die T3 is grounded through microstrips TL7 and TL 8. The single-chip internal bias circuit comprises a first-level die T1 drain bias circuit, a second-level die T2 grid and drain bias circuit, and a third-level die T3 grid and drain bias circuit, wherein the third-level die bias circuit adopts an RLC circuit to provide proper bias voltage for the die and is connected with an external power supply board through PAD 1-PAD 5 and a gold wire; the amplifier stages are isolated through capacitors C5, C8 and C11, and the third stage output is added with a small resistor R9 behind the capacitor C11, so that the stability of the monolithic amplifier at low temperature can be improved.
As a further preferable technical scheme, the broadband monolithic low-noise amplifier is prepared by adopting a 70nm GaAs mHEMT process, and the thickness of the circuit board is 100 um.
It should be noted that, for the problem of inherent insufficient performance at low temperature of the conventional GaAs HEMT process, the MMIC LNA tape-out process In this embodiment uses a 70nm GaAs HEMT process line, where a relatively thick InAlAs layer is grown between the channel layer and the GaAs substrate, and the In composition of the InAlAs layer gradually changes from a certain value x to 0, so as to alleviate lattice mismatch. After the gradual change composition buffer layer is used, the composition x of In the channel layer can be almost randomly selected within 30-60 percent, and the performance of the device is optimized with great freedom degree. mhhemt is considered to be an InP HEMT technology on GaAs substrates that exhibits similar performance to the InP HEMT in terms of low noise, with the absolute high performance of InP being obtained at relatively low cost for GaAs. The GaAs-based mHEMT device has the advantages of high electron mobility, high gain, low noise and low power consumption.
The broadband monolithic low-noise amplifier adopts a three-level mHEMT tube core circuit structure, selects a proper working point at low temperature, realizes the optimal noise and simultaneously meets the requirement that the gain is more than 30 dB. The size of the grid width of the tube core is verified to be capable of stably working at extremely low temperature, and the equivalent noise temperature is superior to 6K at the temperature of C wave band-269 ℃.
As a further preferable technical solution, the signal input and output ports of the low-temperature low-noise amplifier may be connected to SMA, 3.5mm and 2.92K type coaxial connectors, or may be integrated with other low-temperature microwave devices through microstrip lines to form an ultra-low temperature microwave assembly.
The working frequency range of the design of the C-band low-temperature low-noise amplifier for quantum computation is 4-8 GHz, the amplifier is installed in a low-temperature Dewar after an instrument is calibrated during testing, the amplifier is refrigerated after sealed evacuation, the temperature is kept for 1 hour after the working temperature of the device is reduced to be below 269 ℃, a high-precision noise test platform is used for testing the noise temperature of the device, an actual measurement curve is shown as a graph 2, a vector network analyzer is used for testing the gain of the device, the actual measurement curve is shown as a graph 3, and the noise temperature of the device is smaller than 6K and the gain is larger than 30dB as can be seen from the graphs in the graphs 2 and 3.
The broadband monolithic low-noise amplifier in the embodiment has the following beneficial effects:
(1) the high-temperature-resistant high-voltage power supply is manufactured by adopting a 70nm GaAs mHEMT process line, has good low-temperature characteristics compared with a GaAs HEMT process, and has the characteristics of low cost and high reliability compared with an InP HEMT.
(2) The broadband monolithic low-noise amplifier mainly comprises a three-stage high-electron-mobility transistor, an interstage matching circuit and a biasing circuit, wherein the external input microstrip matching circuit comprises a high-frequency microwave circuit board, a chip capacitor, a resistor and the like. The designed low-noise amplifier can stably work at the temperature of-269 ℃ (4K), the gain is greater than 30dB in the frequency band range of a C wave band (4-8 GHz), and the equivalent noise temperature is less than 6K.
(3) The designed low-temperature low-noise amplifier has the characteristics of low noise, small volume, easy input matching and the like, can be applied to a superconducting quantum computer, and can also be applied to the fields with extremely high requirements on noise performance, such as deep space exploration, radio astronomy and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A C-band low-temperature low-noise amplifier for quantum computation is characterized by comprising: the external input micro-strip matching circuit and the broadband monolithic low-noise amplifier are cascaded through a gold wire W2, and the broadband monolithic low-noise amplifier adopts a three-level mHEMT tube core circuit structure.
2. The C-band low-temperature low-noise amplifier for quantum computation of claim 1, wherein the external input microstrip matching circuit comprises a series matching capacitor C1, a first bias circuit, and microstrip lines TL1, TL 2; the microstrip line TL1 is connected in series with the capacitor C1, the capacitor C1 is connected with the microstrip line TL2 through the gold wire W1 and then connected with the first bias circuit, and the microstrip line TL2 is cascaded with the broadband monolithic low noise amplifier through the gold wire W2.
3. The C-band low-temperature low-noise amplifier for quantum computation of claim 2, wherein the first bias circuit comprises a microstrip line TL3, filter capacitors C2 and C3 and a resistor R1, the microstrip line TL3 is connected to a connecting line of the capacitor C1 and the microstrip line TL2, the resistor R1 is connected in series with the microstrip line TL3, and the filter capacitors C2 and C3 are connected in parallel at two ends of the resistor R1.
4. The C-band low temperature low noise amplifier for quantum computing of claim 2, wherein the broadband monolithic low noise amplifier comprises a first level die T1, a second level die T2, and a third level die T3; the grid electrode of the first-level die T1 is connected to the external input microstrip matching circuit through the gold wire W2, the source electrode is grounded through a microstrip line TL4, and the drain electrode is connected with the grid electrode of the second-level die T2 through a DC blocking capacitor C5; the source electrode of the second-level die T2 is grounded through a microstrip line TL5 and a microstrip line TL6, and the drain electrode of the second-level die T2 is connected with the gate electrode of the third-level die T3 through a blocking capacitor C8; the source of the third-level die T3 is grounded through the microstrip line TL7 and the microstrip line TL8, and the drain is connected to the output PAD through the dc blocking capacitor C11 and the resistor R9.
5. The C-band low-temperature low-noise amplifier for quantum computation of claim 4, wherein the broadband monolithic low-noise amplifier further comprises a second bias circuit, a third bias circuit, a fourth bias circuit, a fifth bias circuit and a sixth bias circuit, the second bias circuit comprises a resistor R2, an inductor L1 and a capacitor C4, the third bias circuit comprises resistors R3 and R4 and a capacitor C6, the fourth bias circuit comprises a resistor R5 and a capacitor C7, the fifth bias circuit comprises resistors R6 and R7 and a capacitor C9, and the sixth bias circuit comprises a resistor R8, an inductor L2 and a capacitor C10;
the first bias circuit is used for providing a gate voltage Vg1 of the first-level die T1, the second bias circuit is used for providing a drain voltage Vd1 of the first-level die T1, the second bias circuit is connected with an external power supply through a PAD1, the third bias circuit is used for providing a gate voltage Vg2 of the second-level die T2, the third bias circuit is connected with the external power supply through a PAD4, the fourth bias circuit is used for providing a drain voltage Vd2 of the second-level die T2 and is connected with the external power supply through a PAD2, the fifth bias circuit is used for providing a gate voltage Vg3 of the third-level die T3 and is connected with the external power supply through a PAD5, and the sixth bias circuit is used for providing a drain voltage Vd3 of the third-level die T3 and is connected with the external power supply through a PAD 3.
6. The C-band low-temperature low-noise amplifier for quantum computing as claimed in claim 3, wherein the capacitors C1, C2 and C3 are all chip capacitors, and the resistor R1 is a thin film resistor.
7. The C-band low-temperature low-noise amplifier for quantum computation of claim 4, wherein the gate index of the first-stage die T1 is 2, and the total gate width is 200 um; the gate indices of the second level and third level die T2 and T3 are both 2, and the total gate width is 100 um.
8. The C-band low-temperature low-noise amplifier for quantum computation of any one of claims 1 to 7, wherein the broadband monolithic low-noise amplifier is prepared by using a 70nm GaAs mHEMT process, and the thickness of the circuit board is 100 um.
9. The C-band low-temperature low-noise amplifier for quantum computation of any one of claims 1 to 7, wherein an output PAD of the broadband monolithic low-noise amplifier is connected with a microstrip line TL9 through a gold wire W3.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114070208A (en) * | 2022-01-14 | 2022-02-18 | 华南理工大学 | High-gain millimeter wave broadband ultra-low noise amplifier based on gallium nitride process |
| CN114513171A (en) * | 2022-02-15 | 2022-05-17 | 电子科技大学 | Low noise amplifier of S wave band based on HEMT |
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2021
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114070208A (en) * | 2022-01-14 | 2022-02-18 | 华南理工大学 | High-gain millimeter wave broadband ultra-low noise amplifier based on gallium nitride process |
| CN114513171A (en) * | 2022-02-15 | 2022-05-17 | 电子科技大学 | Low noise amplifier of S wave band based on HEMT |
| CN114513171B (en) * | 2022-02-15 | 2023-05-23 | 电子科技大学 | S-band low-noise amplifier based on HEMT |
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