CN113571567B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113571567B CN113571567B CN202110844972.9A CN202110844972A CN113571567B CN 113571567 B CN113571567 B CN 113571567B CN 202110844972 A CN202110844972 A CN 202110844972A CN 113571567 B CN113571567 B CN 113571567B
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- 238000010586 diagram Methods 0.000 description 18
- 101150037603 cst-1 gene Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel includes: a hole region and a display region surrounding the hole region; a plurality of first signal lines extending in a first direction; a plurality of second signal lines extending in a second direction and bypassing the hole regions; the first direction and the second direction intersect; wherein, different parts of each second signal line are arranged in different wiring layers, and the first signal line is arranged in a wiring layer different from the second signal line. Compared with the prior art, the embodiment of the invention improves the problem of uneven display brightness of the display panel and improves the display effect of the display panel.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, the performance requirements of display panels are higher and higher, and particularly, the display performance of the display panels is always one of the targets continuously pursued by consumers and panel manufacturers. However, the hole area wiring method of the conventional display panel is prone to have a problem of uneven display brightness, which affects the display effect of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for improving the problem of uneven display brightness of the display panel and improving the display effect of the display panel.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a display panel, comprising: a hole region and a display region surrounding the hole region;
a plurality of first signal lines extending in a first direction;
a plurality of second signal lines extending in a second direction and bypassing the hole regions; the first direction and the second direction intersect;
wherein, different parts of each second signal line are arranged in different wiring layers, and the first signal line is arranged in a wiring layer different from the second signal line.
Optionally, each second signal line includes at least one first portion and at least one second portion;
wherein a first portion of any of the second signal lines and a first portion of an adjacent second signal line are disposed on different wiring layers; the second portion of any of the second signal lines is disposed on a different wiring layer than the second portion of the adjacent second signal line.
Preferably, the first portion of any of the second signal lines and the second portion of the adjacent second signal line are arranged on the same wiring layer; the second portion of any of the second signal lines is disposed on the same wiring layer as the first portion of the adjacent second signal line.
Optionally, each second signal line includes at least one first portion and at least one second portion, and the first portion and the second portion in one second signal line are distributed in different wiring layers;
wherein, the total length of the first part in each second signal line is equal to the total length of the second part.
Optionally, a perpendicular bisector of the aperture region extending along the first direction coincides with a perpendicular bisector of the display region extending along the first direction;
the number of the first parts is one, and the number of the second parts is one; the first portion is located on one side of the aperture region and the second portion is located on the other side of the aperture region.
Optionally, each of the second signal lines includes at least one first portion and at least one second portion;
the first part and the second part of each second signal line are alternately arranged in two adjacent wiring layers;
preferably, the wiring layer includes: a first metal layer, a second metal layer and a third metal layer which are stacked;
the first part and the second part of each second signal line are alternately arranged on the first metal layer and the second metal layer; the first signal line is arranged on the third metal layer.
Optionally, the second signal line is replaced by a third metal layer, where the third metal layer includes a bridge, a first end of the bridge is connected with a portion of the second signal line disposed in the first metal layer, and a second end of the bridge is connected with a portion of the second signal line disposed in the second metal layer.
Optionally, the first signal line is a data line, and the second signal line is a scan line or a light emission control signal line.
Optionally, the method further comprises:
a plurality of third signal lines, each of which is a scanning line or a light emission control signal line, and extends along the second direction; the third signal lines are arranged on two sides of the second signal line along the first direction;
preferably, a plurality of third signal lines are uniformly distributed in the same wiring layer;
alternatively, each of the third signal lines includes a first portion and a second portion, and the first portion and the second portion of each of the third signal lines are disposed in different wiring layers.
Optionally, the number of holes in the hole area is at least one;
preferably, the number of holes in the hole area is two, and the two holes are arranged along the second direction.
Correspondingly, the invention also provides a display device comprising the display panel according to any embodiment of the invention.
According to the embodiment of the invention, different parts of each second signal line surrounding the hole area are arranged in different wiring layers, so that the parasitic capacitance between each second signal line and the first signal line comprises the parasitic capacitance generated by different wiring layers. By this arrangement, it is possible to avoid that the parasitic capacitance between the second signal line and the first signal line includes only the parasitic capacitance generated by one wiring layer, and the parasitic capacitance between the second signal line and the first signal line includes only the parasitic capacitance generated by the other wiring layer. Therefore, the embodiment of the invention can lead the parasitic capacitance of the different second signal lines to be the same as that of the first signal line, is beneficial to the data writing of each second signal line to be more balanced, improves the problem of uneven display brightness of the display panel, and improves the display effect of the display panel.
Drawings
FIG. 1 is a schematic diagram of a display panel in the prior art;
FIG. 2 is a schematic diagram of parasitic capacitance between scan lines and data lines in the display panel shown in FIG. 1;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention;
FIG. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
FIG. 6 is a schematic diagram of parasitic capacitance between a first signal line and a second signal line in the display panel shown in FIG. 3;
fig. 7 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
As described in the background art, the hole area wiring mode of the existing display panel is easy to generate the problem of uneven display brightness, and the display effect of the display panel is affected. The inventors found that the above problems occur for the following reasons:
fig. 1 is a schematic structural diagram of a display panel in the prior art. Referring to fig. 1, a hole area 20 ' is provided in a display area 10 ' of the display panel, and the hole area 20 ' is used for providing a camera, a receiver, an inductor, and the like. Since the signal lines cannot be routed in the hole region 20 ', the signal lines such as the data line 30 ' and the scan line 40 ' need to bypass the hole region 20 ', so that the density of the signal lines around the hole region 20 ' is high. In order to meet the high density requirement of the signal lines, the scanning lines 40 ' around the hole area 20 ' are typically wired in a two-layer wiring manner, and adjacent scanning lines 40 ' are respectively located in different wiring layers. The wiring layer may be made of a metal material, and in general, the wiring layer may be also referred to as a metal layer. Only two data lines 30 ' and four scan lines 40 ' around the hole region 20 ' are shown in fig. 1, wherein the first row scan line 40 ' is disposed on the second metal layer M2 ', the second row scan line 40 ' is disposed on the first metal layer M1 ', the third row scan line 40 ' is disposed on the second metal layer M2 ', the fourth row scan line 40 ' is disposed on the first metal layer M1 ', and both data lines 30 ' are disposed on the third metal layer M3 '.
Fig. 2 is a schematic diagram of parasitic capacitance between a scan line and a data line in the display panel shown in fig. 1. Referring to fig. 1 and 2, there is an overlap between the longitudinal data line 30 'and the transverse scan line 40', and parasitic capacitance is generated at the overlap. Since the vertical distance between the first metal layer M1 ' and the third metal layer M3 ' is large, the parasitic capacitance between the scan line 40 ' and the data line 30 ' of the first metal layer M1 ' is small; in contrast, since the vertical distance between the second metal layer M2 ' and the third metal layer M3 ' is smaller, the parasitic capacitance between the scan line 40 ' and the data line 30 ' located in the second metal layer M2 ' is larger. Illustratively, with the perpendicular bisector of the aperture region 20 ' as a boundary, the parasitic capacitance between one side of the first row scan line 40 ' along the perpendicular bisector and the data line 30 ' is Cst1, and the parasitic capacitance between the other side of the first row scan line 40 ' along the perpendicular bisector and the data line 30 ' is Cst1, thus the parasitic capacitance between the first row scan line 40 ' and the data line 30 ' is Cst1 twice; the parasitic capacitance between one side of the second row scan line 40 'along the perpendicular bisector and the data line 30' is Cst2, and the parasitic capacitance between the other side of the second row scan line 40 'along the perpendicular bisector and the data line 30' is Cst2, and thus, the parasitic capacitance between the second row scan line 40 'and the data line 30' is Cst2 twice. Since Cst1 < Cst2, the parasitic capacitances of the scan lines 40 'and the data lines 30' of the adjacent rows are greatly different, resulting in a large difference in data writing of the adjacent rows, causing uneven display brightness of the display panel, and affecting the display effect of the display panel.
In view of the foregoing, embodiments of the present invention provide a display panel. Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 4 is a schematic cross-sectional structure of a display panel according to an embodiment of the present invention, and may specifically be a cross-sectional view of the display panel shown in fig. 3 along a section line AA'. Fig. 5 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and specifically may be a cross-sectional view of the display panel shown in fig. 3 along a section line BB'. Referring to fig. 3 to 5, the display panel includes an aperture region 20 and a display region 10 surrounding the aperture region; the display panel further includes a plurality of first signal lines 30 and a plurality of second signal lines 40, and fig. 3 only exemplarily shows two first signal lines 30 and four second signal lines 40 around the hole region 20. The first signal line 30 extends in the first direction Y around the via area 20; the second signal line 40 extends in the second direction X around the via area 20; the first direction Y and the second direction X intersect. Wherein, different parts of each second signal line 40 are arranged in different wiring layers, and the first signal line 30 is arranged in a wiring layer different from the second signal line 40.
The first signal line 30 and the second signal line 40 are signal lines, for example, data lines, scan lines, and the like, which extend through the entire display area 10. Since the hole region 20 is provided in the display region 10, the signal line cannot directly pass through the hole region 20, and it is necessary to perform a wiring around the hole region 20. The first signal line 30 is disposed not only around the hole region but also in a region distant from the hole region 20. For the signal lines arranged around the hole region 20, it is necessary to bypass the hole region 20. For example, a coordinate system in which the first signal line 30 located on the left side of the hole region 20 bypasses the hole region 20 from the left side of the hole region 20 along the first direction Y and the second direction X is established, and the first signal line 30 located on the right side of the hole region 20 bypasses the hole region 20 on the right side of the hole region 20.
Unlike the first signal lines 30, the second signal lines 40 in the embodiment of the present invention are defined only as signal lines around the hole region 20, and thus, each of the second signal lines 40 is disposed to bypass the hole region 20, for example, in the second direction X, the first second signal lines 40 and the second signal lines 40 located at the upper portion of the hole region 20 each bypass the hole region 20 at the upper portion of the hole region 20; the third and fourth second signal lines 40 and 40 located at the lower portion of the hole region 20 bypass the hole region 20 from the lower portion of the hole region 20. The different portions of each of the second signal lines 40 being disposed in different wiring layers means that one second signal line 40 is not disposed in one wiring layer. Different wiring layers are represented with different fills, and each second signal line 40 illustratively includes two portions, a first portion 41 on the left side and a second portion 42 on the right side, respectively. In the above-mentioned established coordinate system, the first portion 41 of the first second signal line 40 is disposed on the second metal layer M2, and the second portion 42 is disposed on the first metal layer M1; the first portion 41 of the second signal line 40 is disposed on the first metal layer M1, and the second portion 42 is disposed on the second metal layer M2; the first portion 41 of the third second signal line 40 is disposed on the second metal layer M2, and the second portion 42 is disposed on the first metal layer M1; the first portion 41 of the fourth second signal line 40 is disposed on the first metal layer M1, and the second portion 42 is disposed on the second metal layer M2. The first signal line 30 being disposed in a wiring layer different from the second signal line 40 means that the first signal line 30 is disposed in a wiring layer different from the first portion 41 of the second signal line 40, and the first signal line 30 is disposed in a wiring layer different from the second portion 42 of the second signal line 40, for example, the first signal line 30 is disposed in the third metal layer M3.
Wherein the parasitic capacitance between each of the second signal lines 40 and the first signal line 30 includes both parasitic capacitance generated by the overlapping of the first metal layer M1 and the third metal layer M3 and parasitic capacitance generated by the overlapping of the second metal layer M2 and the third metal layer M3. In this way, it is possible to avoid that the parasitic capacitance between the second signal line 40 and the first signal line 30 includes only the parasitic capacitance generated by the first metal layer M1, and the parasitic capacitance between the second signal line and the first signal line 30 includes only the parasitic capacitance generated by the second metal layer M2. Therefore, the parasitic capacitance of the second signal lines 40 and the parasitic capacitance of the first signal lines 30 are the same, so that the data writing of the second signal lines 40 are balanced, the problem of uneven display brightness of the display panel is solved, and the display effect of the display panel is improved.
With continued reference to fig. 3-5, in addition to the above embodiments, optionally, the first portion 41 of any second signal line 40 and the first portion 41 of an adjacent second signal line 40 are disposed on different wiring layers; the second portion 42 of any second signal line 40 is arranged at a different wiring layer than the second portion 42 of an adjacent second signal line 40. Illustratively, the first second signal line 40 is disposed adjacent to the second signal line 40. Then, the first portion 41 of the first second signal line 40 and the first portion 41 of the second signal line are disposed adjacent, and the second portion 42 of the second signal line 40 and the second portion 42 of the first second signal line are disposed adjacent. The first portion 41 of the first second signal line 40 is disposed on the second metal layer M2, and the second portion 42 is disposed on the first metal layer M1; the first portion 41 of the second signal line 40 is disposed on the first metal layer M1, and the second portion 42 is disposed on the second metal layer M2.
Fig. 6 is a schematic diagram of parasitic capacitance between a first signal line and a second signal line in the display panel shown in fig. 3. Illustratively, the parasitic capacitance between the first portion 41 of the first second signal line 40 and the first signal line 30 is Cst1, and the parasitic capacitance between the second portion 42 of the first second signal line 40 and the first signal line 30 is Cst2; the parasitic capacitance between the first portion 41 of the second signal line 40 and the first signal line 30 is Cst2, and the parasitic capacitance between the second portion 42 of the second signal line 40 and the first signal line 30 is Cst1. Therefore, the parasitic capacitance between the whole of the first second signal line 40 and the first signal line 30 is the sum of Cst1 and Cst2. It can be seen that the first portions 41 of the two adjacent second signal lines 40 are disposed in different wiring layers; and, the second portions 42 of two adjacent second signal lines 40 are disposed in different wiring layers, which is beneficial to making parasitic capacitances between the two second signal lines 40 and the first signal line 30 equal, thereby improving uniformity of data writing. In addition, since the first portions 41 (or the second portions 42) of the adjacent two second signal lines 40 are respectively located in different wiring layers, compact wiring of the second signal lines 40 is facilitated.
With continued reference to fig. 5 and 6, in the above embodiments, the second signal line 40 is disposed on the first metal layer M1 and the second metal layer M2, and the first signal line 30 is disposed on the third metal layer M3 for explanation. The metal layers are specifically described below. Optionally, the wiring layer includes: the first metal layer M1, the second metal layer M2, and the third metal layer M3 are stacked. The first metal layer M1 is located on a side of the buffer layer 2 away from the substrate 1, where the first metal layer M1 is typically configured with signal lines such as a scan line and a light emission control signal line, and optionally, the second signal line 40 is a scan line or a light emission control signal line. The second metal layer M2 is located at a side of the first metal layer M1 away from the substrate 1, and the second metal layer M2 is generally provided with signal lines such as a scan line and an initialization voltage signal line; the third metal layer M3 is located on the side of the second metal layer M2 away from the substrate 1, and the third metal layer M3 is typically disposed with signal lines such as data lines and power lines.
In the above embodiments, the first signal line 30 is disposed in the third metal layer M3 and the second signal line 40 is disposed in the first metal layer M1 and the second metal layer M2, but the present invention is not limited thereto, and may be set as needed in practical applications. For example, the display panel may further include a fourth metal layer, and the first signal line 30 may be further disposed in the fourth metal layer.
In the above embodiments, the first portion 41 and the second portion 42 of the second signal line 40 need to be replaced, and there are various wire replacing manners, and several of them will be described below, but the present invention is not limited thereto.
In one embodiment of the present invention, alternatively, the first portion 41 and the second portion 42 of the second signal line 40 are directly perforated by an insulating layer between the first metal layer M1 and the second metal layer M2 to realize line replacement. By the arrangement, the wiring mode of the display panel is concise, but based on the existing manufacturing process of the display panel, no process for punching an insulating layer between the first metal layer M1 and the second metal layer M2 is performed in the process of forming the first metal layer M1 and the second metal layer M2, so that a process flow is added by directly punching the insulating layer between the first metal layer M1 and the second metal layer M2.
Fig. 7 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and specifically may be a cross-sectional view of the display panel shown in fig. 3 along a section line CC'. Referring to fig. 7, in one embodiment of the present invention, the second signal line 40 is optionally swapped through the third metal layer M3. Illustratively, the second portion 42 of the first second signal line 40 is disposed on the second metal layer M2, the first portion 41 is disposed on the first metal layer M1, and the second portion 42 is in line with the first portion 41 through the third metal layer M3. The third metal layer M3 includes a bridge, a first end of the bridge is connected to a portion of the second signal line 40 disposed in the first metal layer M1, and a second end of the bridge is connected to a portion of the second signal line 40 disposed in the second metal layer M2. Based on the existing manufacturing process of the display panel, a punching process is performed before forming the third metal layer M3 so that signal lines located at different metal layers are connected through the third metal layer M3. The first portion 41 and the second portion 42 of the second signal line 40 are connected through the third metal layer M3, which can be matched with the existing preparation process without adding a process flow.
In each of the above embodiments, the first portion 41 and the second portion 42 are at least one, and the specific number of the first portion 41 and the second portion 42 is described below, but the present invention is not limited thereto.
With continued reference to fig. 3, in an embodiment of the present invention, each second signal line 40 may optionally include only one first portion 41 and one second portion 42, so that each second signal line 40 needs only one line change, which is simple in structure and easy to implement.
Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 8, in another embodiment of the present invention, the first second signal line 40 may optionally include two first portions 41 and one second portion 42, and the second signal line 40 may include two first portions 41 and one second portion 42. The first portion 41 and the second portion 42 are disposed on different wiring layers, and the first portion 41 and the second portion 42 can be replaced by a metal layer where the first signal line 30 is located. The arrangement of the second signal line 40 is flexible, so that the adjustment is facilitated according to the needs in practical application.
Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 9, in still another embodiment of the present invention, optionally, the first and second signal lines 40 and 40 each include two first portions 41 and two second portions 42. The more the first portion 41 and the second portion 42 are disposed in the second signal line 40, the more uniform the parasitic capacitance is distributed, but the more the number of line changes are required, the number of the first portion 41 and the second portion 42 may be set as required in practical applications.
In each of the above embodiments, optionally, the total length of the first portion 41 and the total length of the second portion 42 of each of the second signal lines 40 are equal; and the number of first portions 41 is equal or unequal to the number of second portions 42. This arrangement is advantageous in that the total parasitic capacitances generated by the different second signal lines 40 are equal, so that the display luminance uniformity of the display panel can be further enhanced.
With continued reference to fig. 3, 8 and 9, in one embodiment of the present invention, the first portion 41 and the second portion 42 of each second signal line 40 may alternatively be alternately arranged in adjacent two wiring layers. Preferably, for the scan lines and the light emission control signal lines, two adjacent wiring layers are the first metal layer M1 and the second metal layer M2. Illustratively, the first portion 41 of the first second signal line 40 is disposed on the second metal layer M2, and the second portion 42 is disposed on the first metal layer M1; the first portion 41 of the second signal line 40 is disposed on the first metal layer M1, and the second portion 42 is disposed on the second metal layer M2. By the arrangement, the first part 41 and the second part 42 of the second signal line 40 only need to complete wiring in two adjacent wiring layers, and the wiring mode is simple and easy to realize.
The embodiment of the present invention is not limited to the arrangement manner of the hole area 20, and is applicable to any case where the hole area 20 is arranged in the display area 10, and will be described in detail below.
With continued reference to fig. 3, 8 and 9, in one embodiment of the present invention, the number of holes in the hole area 20 is optionally two, with the two holes 21 aligned along the second direction X. Specifically, the two cutouts 21 are aligned in the same direction as the extending direction of the second signal line 40, and a distance is provided between the two cutouts 21. Wherein, two hole 21 digs can realize the scheme of two cameras in the screen to promote display panel's effect of making a video recording. Illustratively, one of the hollows 21 is used for providing an infrared camera, and the other hollows 21 is used for providing a normal camera; alternatively, one of the hollows 21 is used for setting a tele lens camera, and the other hollows 21 is used for setting a wide-angle lens camera. Since the hole area 20 is provided with two cutouts 21, the area of the display area 10 is large, and uneven display such as mura is more likely to occur. The embodiment of the invention can obviously improve the phenomenon of uneven display such as mura in the double cameras and the like, and improve the display effect of the display panel.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 10, in another embodiment of the present invention, optionally, the number of holes in the hole area 20 is one, and the arrangement manner of the first signal line 30 and the second signal line 40 around the hole area 20 may still be the arrangement manner provided in the above embodiments, which is not described herein.
In the above embodiments, the types of the first signal line 30 and the second signal line 40 are various, and the description is given below with respect to the first signal line 30 being a data line and the second signal line 40 being a scanning line or a light emission control signal line, but the present invention is not limited thereto.
Fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 11, in an embodiment of the present invention, optionally, the display panel further includes a plurality of third signal lines 50, the third signal lines 50 being scan lines or light emission control signal lines, extending in the second direction X; the third signal lines 50 are disposed on both sides of the second signal line 40 along the first direction Y. Specifically, the second signal line 40 and the third signal line 50 are both scan lines, the scan lines extend along the second direction X, and the distance between the third signal line 50 and the hole area 20 is greater than the distance between the second signal line 40 and the hole area 20, i.e. the third signal line 50 does not need to be wound from the hole area 20. In one embodiment of the present invention, optionally, the plurality of third signal lines 50 are uniformly distributed in the same wiring layer, and may specifically be the first metal layer M1 or the second metal layer M2. The arrangement is simple in wiring mode and easy to realize.
Fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 12, in another embodiment of the present invention, optionally, the third signal lines 50 include a first portion 51 and a second portion 52, where the first portion 51 and the second portion 52 of each third signal line 50 are disposed in different wiring layers, and the specific arrangement manner is the same as that of the second signal lines 40 around the hole area 20, and will not be repeated here.
The embodiment of the invention also provides a display device which comprises the display panel according to any embodiment of the invention, wherein the display device can be a mobile phone, a computer, a tablet personal computer, intelligent wearing equipment or other electronic equipment with a display function. The display device provided by the embodiment of the invention comprises the display panel provided by any of the embodiments of the invention, so that the display device has the corresponding structure and beneficial effects of the display panel, and the description is omitted.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (11)
1. A display panel, comprising: a hole region and a display region surrounding the hole region;
a plurality of first signal lines extending in a first direction;
a plurality of second signal lines extending in a second direction and bypassing the hole regions; the first direction and the second direction intersect;
wherein different parts of each second signal line are arranged in different wiring layers, and the first signal line is arranged in a wiring layer different from the second signal line;
each of the second signal lines includes at least one first portion and at least one second portion;
the first part and the second part of each second signal line are alternately arranged in two adjacent wiring layers;
the wiring layer includes: a first metal layer, a second metal layer and a third metal layer which are stacked;
the first part and the second part of each second signal line are alternately arranged on the first metal layer and the second metal layer; the first signal wire is arranged on the third metal layer;
the second signal line is subjected to line replacement through the third metal layer, wherein the third metal layer comprises a bridge, a first end of the bridge is connected with a part of the second signal line, which is arranged in the first metal layer, and a second end of the bridge is connected with a part of the second signal line, which is arranged in the second metal layer;
the parasitic capacitance between each of the second signal lines and the first signal line includes a parasitic capacitance generated by overlapping the first metal layer and the third metal layer, and a parasitic capacitance generated by overlapping the second metal layer and the third metal layer.
2. The display panel of claim 1, wherein each of the second signal lines includes at least one first portion and at least one second portion;
wherein a first portion of any of the second signal lines and a first portion of an adjacent second signal line are disposed on different wiring layers; the second portion of any of the second signal lines is disposed on a different wiring layer than the second portion of the adjacent second signal line.
3. The display panel according to claim 2, wherein a first portion of any of the second signal lines is laid out in the same wiring layer as a second portion of an adjacent second signal line; the second portion of any of the second signal lines is disposed on the same wiring layer as the first portion of the adjacent second signal line.
4. The display panel according to claim 1, wherein each of the second signal lines includes at least one first portion and at least one second portion, the first portion and the second portion in each of the second signal lines being disposed in different wiring layers;
wherein the total length of the first portion in each of the second signal lines is equal to the total length of the second portion.
5. The display panel of claim 4, wherein a perpendicular bisector of the aperture region extending along the first direction coincides with a perpendicular bisector of the display region extending along the first direction;
the number of the first parts is one, and the number of the second parts is one; the first portion is located on one side of the aperture region and the second portion is located on the other side of the aperture region.
6. The display panel according to claim 1, wherein the first signal line is a data line and the second signal line is a scan line or a light emission control signal line.
7. The display panel of claim 6, further comprising:
a plurality of third signal lines, wherein the third signal lines are scanning lines or light-emitting control signal lines and extend along the second direction; along the first direction, the third signal lines are arranged on two sides of the second signal lines.
8. The display panel according to claim 7, wherein the plurality of third signal lines are uniformly arranged in the same wiring layer;
alternatively, each of the third signal lines includes a first portion and a second portion, and the first portion and the second portion of each of the third signal lines are disposed in different wiring layers.
9. The display panel of claim 1, wherein the number of cutouts in the aperture area is at least one.
10. The display panel of claim 9, wherein the number of cutouts in the aperture area is two, and two of the cutouts are aligned in the second direction.
11. A display device, comprising: the display panel of any one of claims 1-10.
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