CN113571512B - Fully depleted silicon-on-insulator ESD protection device and preparation method thereof - Google Patents
Fully depleted silicon-on-insulator ESD protection device and preparation method thereof Download PDFInfo
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- CN113571512B CN113571512B CN202111110454.0A CN202111110454A CN113571512B CN 113571512 B CN113571512 B CN 113571512B CN 202111110454 A CN202111110454 A CN 202111110454A CN 113571512 B CN113571512 B CN 113571512B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
The invention provides a fully depleted silicon-on-insulator ESD protection device and a preparation method thereof, wherein the preparation method comprises the following steps: bottom silicon with P-type low doping; the buried oxide layer is formed on the bottom silicon; the top layer silicon is formed on the buried oxide layer and has P-type low doping; the first N-type heavily doped region is formed in the top silicon layer; the second N-type heavily doped region is formed in the top silicon layer; the P-type heavily doped region is formed on the top silicon between the first N-type heavily doped region and the second N-type heavily doped region; the first base electrode is electrically connected with the first N-type heavily doped region; the second base electrode is electrically connected with the second N-type heavily doped region; the emitter electrode is electrically connected with the P-type heavily doped region; a gate electrode electrically connected to the underlying silicon. The fully depleted silicon-on-insulator ESD protection device utilizes the single-junction transistor to form a voltage stabilizing structure, realizes high-voltage ESD protection, and is suitable for the fully depleted silicon-on-insulator device.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a fully depleted silicon-on-insulator ESD protection device and a preparation method thereof.
Background
As microelectronic devices are scaled down in size and functionally integrated, Electrostatic discharge (ESD) protection of chips is becoming increasingly important. First, the gate dielectric and isolation of small-sized devices are thinner, resulting in a weaker ability of the device to withstand static electricity, and thus a narrower window for ESD device design. Secondly, more and more modules are integrated on the same silicon substrate, resulting in more and more risk of the chip being exposed to ESD. In addition, silicon-on-insulator (SOI) devices, especially fully depleted silicon-on-insulator (FDSOI) devices, have a thin top layer scale and are difficult to fabricate high voltage tolerant ESD protection devices.
Therefore, how to improve the electrostatic protection capability of the fully depleted soi device has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a fully depleted silicon-on-insulator ESD protection device and a method for manufacturing the same, which are used to solve the problem that it is difficult to implement high voltage-tolerant ESD protection in the fully depleted silicon-on-insulator device in the prior art.
To achieve the above and other related objects, the present invention provides a fully depleted silicon-on-insulator ESD protection device, comprising at least:
bottom silicon with P-type low doping;
the buried oxide layer is formed on the bottom silicon;
the top layer silicon is formed on the buried oxide layer and has P-type low doping;
the first N-type heavily doped region is formed in the top silicon layer;
the second N-type heavily doped region is formed in the top silicon layer;
the P-type heavily doped region is formed on the top silicon between the first N-type heavily doped region and the second N-type heavily doped region;
the first base electrode is electrically connected with the first N-type heavily doped region;
the second base electrode is electrically connected with the second N-type heavily doped region;
the emitter electrode is electrically connected with the P-type heavily doped region;
a gate electrode electrically connected to the underlying silicon.
Optionally, the thickness of the top layer silicon is smaller than the thickness of the buried oxide layer.
More optionally, the thickness of the buried oxide layer is set to be 100nm to 200 nm.
More optionally, the thickness of the top layer silicon is set to be 28nm to 100 nm.
Optionally, the gate electrode is disposed below the underlying silicon.
More optionally, the first base electrode is grounded, the second base electrode is connected to a first voltage signal, the emitter electrode is connected to a pulse signal, and the gate electrode is connected to a second voltage signal; the first voltage signal is greater than 0V, and the second voltage signal is not less than 0V.
More optionally, a distance between the P-type heavily doped region and the first N-type heavily doped region is smaller than a distance between the P-type heavily doped region and the second N-type heavily doped region.
To achieve the above and other related objects, the present invention provides a method for manufacturing a fully depleted silicon-on-insulator ESD protection device, the method at least comprising:
s1: providing a P-type SOI structure, wherein the SOI structure comprises bottom silicon, a buried oxide layer and top silicon which are sequentially stacked;
s2: coating photoresist on the top silicon layer, exposing the top silicon layer in the areas where the first base electrode and the second base electrode are located through photoetching, and performing ion implantation on the exposed top silicon layer to form a first N-type heavily doped region and a second N-type heavily doped region;
s3: etching the first N-type heavily doped region, the second N-type heavily doped region and the top silicon layer, and forming a P-type heavily doped region on the top silicon layer between the first N-type heavily doped region and the second N-type heavily doped region;
s4: and forming a first base electrode electrically connected with the first N-type heavily doped region, a second base electrode electrically connected with the second N-type heavily doped region, an emitter electrode electrically connected with the P-type heavily doped region and a gate electrode electrically connected with the bottom layer silicon.
Optionally, step S2 is preceded by removing the oxide layer on the top silicon surface with tetramethylammonium hydroxide.
More optionally, a distance between the P-type heavily doped region and the first N-type heavily doped region is smaller than a distance between the P-type heavily doped region and the second N-type heavily doped region.
As described above, the fully depleted silicon-on-insulator ESD protection device and the preparation method thereof of the present invention have the following beneficial effects:
the fully depleted silicon-on-insulator ESD protection device utilizes the single-junction transistor to form a voltage stabilizing structure, realizes high-voltage ESD protection, and is suitable for the fully depleted silicon-on-insulator device.
Drawings
Fig. 1 shows a schematic structural diagram of a fully depleted silicon-on-insulator ESD protection device of the present invention.
Fig. 2 shows a schematic diagram of the operation principle of the fully depleted silicon-on-insulator ESD protection device of the present invention with Vbg = 20V.
Fig. 3 shows a schematic diagram of the operation principle of the fully depleted silicon-on-insulator ESD protection device of the present invention with Vbg = 15V.
Fig. 4 shows a schematic diagram of the operation principle of the fully depleted silicon-on-insulator ESD protection device of the present invention with Vbg = 10V.
Fig. 5 shows a schematic diagram of the operation principle of the fully depleted silicon-on-insulator ESD protection device of the present invention with Vbg = 0V.
Fig. 6 shows a schematic diagram of providing an SOI substrate for a method of fabricating a fully depleted silicon-on-insulator ESD protection device of the present invention.
Fig. 7 is a schematic diagram showing the formation of a first heavily doped N-type region and a second heavily doped N-type region by the method for manufacturing a fully depleted silicon-on-insulator ESD protection device of the present invention.
Fig. 8 is a schematic diagram showing the formation of a P-type heavily doped region for the method of manufacturing a fully depleted silicon-on-insulator ESD protection device of the present invention.
Description of the element reference numerals
1-fully depleted silicon-on-insulator ESD protection device; 11-bottom silicon; 12-buried oxide layer; 13-top layer silicon; 14-a first heavily N-doped region; 15-a second N type heavily doped region; a 16-P type heavily doped region; 17-photoresist.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides a fully depleted silicon-on-insulator ESD protection device 1, the fully depleted silicon-on-insulator ESD protection device 1 comprising: the silicon substrate comprises bottom layer silicon 11, a buried oxide layer 12, top layer silicon 13, a first N-type heavily doped region 14, a second N-type heavily doped region 15, a P-type heavily doped region 16, a first base electrode B1, a second base electrode B2, an emitter electrode E and a gate electrode G.
As shown in fig. 1, the bottom layer silicon 11 is located at the bottom layer of the fully depleted silicon-on-insulator ESD protection device 1.
Specifically, in the present embodiment, the bottom silicon 11 has P-type low doping, the doping ion is boron, and the doping concentration is 1015cm-3(ii) a In practical use, the dopant ions and the dopant concentration can be selected according to practical requirements, and are not limited to this embodiment.
As shown in fig. 1, the buried oxide layer 12 is formed on the bottom silicon 11.
Specifically, in the present embodiment, the thickness of the Buried Oxide layer 12 (BOX) is set to be 100nm to 200 nm; as an example, the thickness of the buried oxide layer 12 is set to 145 nm.
As shown in fig. 1, the top layer silicon 13 is formed on the buried oxide layer 12.
Specifically, in the present embodiment, the top layer silicon 13 has P-type low doping, the doping ion is boron, and the doping concentration is 1015cm-3(ii) a In practical use, the dopant ions and the dopant concentration can be selected according to practical requirements, and are not limited to this embodiment. The doping type (P type) of the top layer silicon 13 is the same as that of the bottom layer silicon 11, and the doping ions and the doping concentration can be respectively set according to the requirement.
Specifically, in the present embodiment, the thickness of the top silicon 13 is smaller than that of the buried oxide layer 12, and the thickness of the top silicon 13 is set to be 28nm to 100nm as an example.
As shown in fig. 1, the first and second heavily doped N- type regions 14 and 15 are formed in the top silicon 13.
Specifically, a P-type low-doped region of the top silicon 13 is disposed between the first N-type heavily doped region 14 and the second N-type heavily doped region 15, and as an example, the width of the P-type low-doped region between the first N-type heavily doped region 14 and the second N-type heavily doped region 15 is set to be 5 μm.
Specifically, the first heavily doped N-type region 14 and the second heavily doped N-type region 15 have a heavily doped N-type, the dopant ions are arsenic, and the dopant concentration is 1020cm-3(ii) a In practical use, the dopant ions and the dopant concentration can be selected according to practical requirements, and are not limited to this embodiment.
As shown in fig. 1, the heavily P-doped region 16 is formed on the top silicon 13 between the first heavily N-doped region 14 and the second heavily N-doped region 15.
Specifically, the P-type heavily doped region 16 has P-type heavily doped, the doping ions are boron, and the doping concentration is 1020cm-3(ii) a In practical use, the dopant ions and the dopant concentration can be selected according to practical requirements, and are not limited to this embodiment.
Specifically, in the present embodiment, the width of the P-type heavily doped region 16 is set to 500 nm.
As shown in fig. 1, the first base electrode B1 is electrically connected to the first heavily N-doped region 14 for leading out a first base.
As shown in fig. 1, the second base electrode B2 is electrically connected to the second heavily N-doped region 15 for leading out a second base.
As shown in fig. 1, the emitter electrode E is electrically connected to the heavily P-doped region 16 for extracting an emitter.
Specifically, in the present embodiment, the top silicon 13, the first heavily doped N-type region 14, the second heavily doped N-type region 15 and the heavily doped P-type region 16 are provided with an insulating layer (not shown), and the first base electrode B1, the second base electrode B2 and the emitter electrode E are all located above the insulating layer and are insulated from each other.
As shown in fig. 1, the gate electrode G is electrically connected to the underlying silicon 11 for extracting a gate.
Specifically, in the present embodiment, the gate electrode G is disposed below the underlying silicon 11, forming a back gate structure.
As shown in fig. 1, in the present embodiment, the first base electrode B1 is grounded. The second base electrode B2 is connected with a first voltage signal, the first voltage signal is high voltage, and the voltage value is greater than 0V; by way of example, the voltage values of the first voltage signal include, but are not limited to, 5V, 6V, 8V, and 10V, and the specific values are determined based on the application environment of the fully depleted silicon-on-insulator ESD protection device 1. The emitter electrode E is connected to a pulse signal, for example, the low level of the pulse signal is 0V, and the high level of the pulse signal is 3V, and the amplitude and the pulse width of the pulse signal can be set according to needs in practical use. The grid electrode G is connected with a second voltage signal, and the voltage value of the second voltage signal is not less than 0V; by way of example, the voltage values of the second voltage signal include, but are not limited to, 0V, 10V, 15V, and 20V.
As shown in fig. 1, in the present embodiment, the distance between the P-type heavily doped region 16 and the first N-type heavily doped region 14 is smaller than the distance between the P-type heavily doped region 16 and the second N-type heavily doped region 15. In practical use, when the second N-type heavily doped region 15 is grounded and the first N-type heavily doped region 14 is connected to a high voltage, the P-type heavily doped region 16 is close to the second N-type heavily doped region 15 and is far from the first N-type heavily doped region 14.
2-5, in one embodiment, the first base electrode B1 is grounded and the second base electrode B2 is connected to a voltage of 6V (V)B2= 6V), the emitter electrode E is connected with a 0-3-0V pulse signal VEThe gate electrode G is connected to different back gate voltages 0V, 10V, 15V and 20V (Vbg =0V, Vbg)=10V, Vbg =15V, Vbg = 20V), a back gate voltage is used for forming an inversion layer, a transverse electric field is formed between the first N-type heavily doped region 14 and the second N-type heavily doped region 15, the carrier transverse transport of the inversion layer is controlled, and the emitter injects minority carriers by opening a PN junction, so that the device performs positive feedback. Taking Vbg =20V as an example, in the pulse signal VECurrent I at the second base electrode B2 in the process of changing from 0V to 3VB2Slowly increases from 0.14mA and is in the pulse signal VEAbrupt change from 0.17mA to 0.3mA at 2.4V and then continued slow increase to 0.35 mA; at the pulse signal VECurrent I at the second base electrode B2 in the process of changing from 3V to 0VB2Slowly decreases from 0.35mA and is in the pulse signal VEAbrupt change from 0.28mA to 0.16mA when reaching 1.2V, then continuous slow decrease to 0.14 mA; the two curves form the hysteresis.
The fully depleted silicon-on-insulator ESD protection device utilizes the single-junction transistor to form a voltage stabilizing structure, realizes high-voltage ESD protection, and is suitable for the fully depleted silicon-on-insulator device.
Example two
As shown in fig. 6 to 8, this embodiment provides a method for manufacturing a fully depleted silicon-on-insulator ESD protection device, and as an example, the structure of the fully depleted silicon-on-insulator ESD protection device is the same as that of the first embodiment. The preparation method of the fully depleted silicon-on-insulator ESD protection device comprises the following steps:
s1: providing a P-type SOI structure, wherein the SOI structure comprises a bottom silicon layer, a buried oxide layer and a top silicon layer which are sequentially stacked.
Specifically, as shown in fig. 6, the present embodiment is based on a fully depleted silicon-on-insulator process, and first provides an SOI substrate structure comprising a bottom layer silicon 11, a buried oxide layer 12 and a top layer silicon 13 stacked in sequence. The preparation method of the SOI substrate structure is not limited, and any method capable of obtaining the SOI substrate structure is applicable to the present invention, which is not described herein again.
S2: and coating photoresist on the top silicon layer, exposing the top silicon layer in the areas where the first base electrode and the second base electrode are positioned by photoetching, and performing ion implantation on the exposed top silicon layer to form a first N-type heavily doped region and a second N-type heavily doped region.
Specifically, as another implementation manner of the present invention, a diluted tetramethylammonium hydroxide solution is used to remove the oxide layer on the surface of the top silicon 13 before performing photolithography. In practical use, in the case that no oxide layer exists on the surface of the top silicon 13, the surface of the top silicon 13 does not need to be cleaned by using a diluted tetramethylammonium hydroxide solution.
Specifically, as shown in fig. 7, a photoresist 17 is coated on the upper surface of the top layer silicon 13, the top layer silicon in the regions where the first base and the second base are located is exposed through exposure and development, and the exposed top layer silicon 13 is subjected to ion implantation to form a first N-type heavily doped region 14 and a second N-type heavily doped region 15.
S3: and etching the first N-type heavily doped region, the second N-type heavily doped region and the top silicon, and forming a P-type heavily doped region on the top silicon between the first N-type heavily doped region and the second N-type heavily doped region.
Specifically, as shown in fig. 8, photoresist is coated on the upper surfaces of the first N-type heavily doped region 14, the second N-type heavily doped region 15 and the top layer silicon 13, the top layer silicon 13 outside the region where the emitter is located is exposed through exposure and development, the exposed first N-type heavily doped region 14, the second N-type heavily doped region 15 and the top layer silicon 13 are etched, and a raised emitter region (16) is formed on the top layer silicon between the first N-type heavily doped region 14 and the second N-type heavily doped region 15; and performing ion implantation on the emitter region to form a P-type heavily doped region 16.
It should be noted that the P-type heavily doped region 16 is close to the grounded side of the first N-type heavily doped region 14 or the second N-type heavily doped region 15, in this embodiment, the first N-type heavily doped region 14 is grounded, and therefore, the distance between the P-type heavily doped region 16 and the first N-type heavily doped region 14 is less than the distance between the P-type heavily doped region 16 and the second N-type heavily doped region 15.
Specifically, as another implementation manner of the present invention, after the P-type heavily doped region 16 is formed, a high temperature annealing step is further included. As an example, the structure formed in step S3) is subjected to high temperature annealing with a high temperature of 950 ℃ to activate the impurities.
S4: and forming a first base electrode electrically connected with the first N-type heavily doped region, a second base electrode electrically connected with the second N-type heavily doped region, an emitter electrode electrically connected with the P-type heavily doped region and a gate electrode electrically connected with the bottom layer silicon.
Specifically, in the present embodiment, each electrode is formed by metal deposition, which is not described herein.
In summary, the present invention provides a fully depleted silicon-on-insulator ESD protection device and a method for manufacturing the same, including: bottom silicon with P-type low doping; the buried oxide layer is formed on the bottom silicon; the top layer silicon is formed on the buried oxide layer and has P-type low doping; the first N-type heavily doped region is formed in the top silicon layer; the second N-type heavily doped region is formed in the top silicon layer; the P-type heavily doped region is formed on the top silicon between the first N-type heavily doped region and the second N-type heavily doped region; the first base electrode is electrically connected with the first N-type heavily doped region; the second base electrode is electrically connected with the second N-type heavily doped region; the emitter electrode is electrically connected with the P-type heavily doped region; a gate electrode electrically connected to the underlying silicon. The fully depleted silicon-on-insulator ESD protection device utilizes the single-junction transistor to form a voltage stabilizing structure, realizes high-voltage ESD protection, and is suitable for the fully depleted silicon-on-insulator device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A fully depleted silicon-on-insulator ESD protection device, characterized in that it comprises at least:
bottom silicon with P-type low doping;
the buried oxide layer is formed on the bottom silicon;
the top layer silicon is formed on the buried oxide layer and has P-type low doping;
the first N-type heavily doped region is formed in the top silicon layer;
the second N-type heavily doped region is formed in the top silicon layer;
the P-type heavily doped region is formed on the top silicon between the first N-type heavily doped region and the second N-type heavily doped region;
the first base electrode is electrically connected with the first N-type heavily doped region;
the second base electrode is electrically connected with the second N-type heavily doped region;
the emitter electrode is electrically connected with the P-type heavily doped region;
a gate electrode electrically connected to the underlying silicon.
2. The fully depleted silicon-on-insulator ESD protection device of claim 1, wherein: the thickness of the top layer silicon is smaller than that of the buried oxide layer.
3. The fully depleted silicon-on-insulator ESD protection device of claim 2, wherein: the thickness of the buried oxide layer is set to be 100 nm-200 nm.
4. The fully depleted silicon-on-insulator ESD protection device of claim 2, wherein: the thickness of the top layer silicon is set to be 28 nm-100 nm.
5. The fully depleted silicon-on-insulator ESD protection device of claim 1, wherein: the gate electrode is disposed below the bottom silicon.
6. The fully depleted silicon-on-insulator ESD protection device of any of claims 1-5, wherein: the first base electrode is grounded, the second base electrode is connected with a first voltage signal, the emitter electrode is connected with a pulse signal, and the grid electrode is connected with a second voltage signal; the first voltage signal is greater than 0V, and the second voltage signal is not less than 0V.
7. The fully depleted silicon-on-insulator ESD protection device of claim 6, wherein: the distance between the P-type heavily doped region and the first N-type heavily doped region is smaller than the distance between the P-type heavily doped region and the second N-type heavily doped region.
8. A method of fabricating a fully depleted silicon-on-insulator ESD protection device as claimed in any of claims 1 to 7, wherein the method of fabricating the fully depleted silicon-on-insulator ESD protection device comprises at least:
s1: providing a P-type SOI structure, wherein the SOI structure comprises bottom silicon, a buried oxide layer and top silicon which are sequentially stacked;
s2: coating photoresist on the top silicon layer, exposing the top silicon layer in the areas where the first base electrode and the second base electrode are located through photoetching, and performing ion implantation on the exposed top silicon layer to form a first N-type heavily doped region and a second N-type heavily doped region;
s3: etching the first N-type heavily doped region, the second N-type heavily doped region and the top silicon layer, and forming a P-type heavily doped region on the top silicon layer between the first N-type heavily doped region and the second N-type heavily doped region;
s4: and forming a first base electrode electrically connected with the first N-type heavily doped region, a second base electrode electrically connected with the second N-type heavily doped region, an emitter electrode electrically connected with the P-type heavily doped region and a gate electrode electrically connected with the bottom layer silicon.
9. The method of manufacturing a fully depleted silicon-on-insulator ESD protection device of claim 8, wherein: step S2 is preceded by removing the oxide layer on the top silicon surface with tetramethylammonium hydroxide.
10. The method of manufacturing a fully depleted silicon-on-insulator ESD protection device according to claim 8 or 9, wherein: the distance between the P-type heavily doped region and the first N-type heavily doped region is smaller than the distance between the P-type heavily doped region and the second N-type heavily doped region.
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| US8586439B1 (en) * | 2012-07-11 | 2013-11-19 | International Business Machines Corporation | Inversion mode varactor |
| US9954356B2 (en) * | 2015-05-15 | 2018-04-24 | Analog Devices, Inc. | Electrostatic discharge protection circuits for radio frequency communication systems |
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| CN113571512A (en) | 2021-10-29 |
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