CN113568206A

CN113568206A - Display device and assembling method thereof

Info

Publication number: CN113568206A
Application number: CN202110868310.5A
Authority: CN
Inventors: 黄俊隆; 吕佩颖; 董继尧
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-21
Filing date: 2021-07-30
Publication date: 2021-10-29
Anticipated expiration: 2041-07-30
Also published as: CN113568206B

Abstract

The invention discloses a display device and an assembling method thereof, wherein the display device comprises: the display device comprises a first substrate, a second substrate, frame glue, a display medium layer, a hydrophobic film and a plurality of electrode groups. The second substrate is opposite to the first substrate. The frame glue is positioned between the first substrate and the second substrate. The display medium layer is positioned among the first substrate, the second substrate and the frame glue. The hydrophobic film is positioned between the display medium layer and the first substrate and is adjacent to the frame glue. The plurality of electrode groups are positioned between the hydrophobic film and the display medium layer, and each electrode group comprises a plurality of electrode pairs. In addition, an assembling method of the display device is also provided.

Description

Display device and assembling method thereof

Technical Field

The present invention relates to a display device, and more particularly, to a display device having improved reliability.

Background

In the design of display products, narrow frames have become a trend, the visual range of a picture can be maximized under the same resolution, and the visual interference of the frames can be reduced when the large-size panels are spliced.

However, due to the design of the narrow frame, in the process of the substrate pair (e.g., the component array substrate and the filter substrate pair), the liquid crystal may contact the sealant to cause contamination or puncture, which causes light leakage of the display product and results in poor reliability of the display product.

Disclosure of Invention

The invention provides a display device with improved reliability.

One embodiment of the present invention provides a display device including: a first substrate; a second substrate opposite to the first substrate; the frame glue is positioned between the first substrate and the second substrate; the display medium layer is positioned among the first substrate, the second substrate and the frame glue; the hydrophobic film is positioned between the display medium layer and the first substrate and is adjacent to the frame glue; and a plurality of electrode groups located between the hydrophobic film and the display medium layer, and each electrode group comprises a plurality of electrode pairs.

In an embodiment of the invention, the hydrophobic film has a rectangular loop shape.

In an embodiment of the invention, the plurality of electrode sets includes 2 to 10 electrode sets.

In an embodiment of the invention, a width of each of the electrode sets is less than 100 μm.

In an embodiment of the invention, the plurality of electrode pairs includes 2 to 10 electrode pairs.

In an embodiment of the invention, the electrode pairs include a transparent conductive material.

In an embodiment of the invention, each of the electrode pairs includes two parallel conductive lines.

In an embodiment of the invention, a line width of each of the parallel conductive lines is between 2 μm and 5 μm.

In an embodiment of the invention, a pitch of the two parallel conductive lines is between 10 μm and 16 μm.

In an embodiment of the invention, a ratio of a line width to a space of the two parallel conductive lines is between 1:2 and 1: 8.

In an embodiment of the invention, each of the parallel conductive lines has a bent shape.

In an embodiment of the invention, each of the parallel conductive lines has a bending angle, and the bending angle is between 10 degrees and 50 degrees.

In an embodiment of the invention, each of the electrode sets further includes two electrode ends, and the two electrode ends are respectively electrically connected to the two parallel wires.

In an embodiment of the invention, two electrode ends of the plurality of electrode groups are electrically connected to each other, respectively.

In an embodiment of the invention, the display device further includes a pixel electrode, and the plurality of electrode pairs and the pixel electrode belong to the same film layer.

One embodiment of the present invention provides an assembly method of a display device, including: providing an element array substrate, wherein the element array substrate comprises a first substrate, a hydrophobic film and a plurality of electrode groups, the hydrophobic film is positioned between the electrode groups and the first substrate and is adjacent to the periphery of the first substrate, and the electrode groups are positioned on the hydrophobic film and respectively comprise a plurality of electrode pairs; providing a light filtering substrate, wherein the light filtering substrate comprises a second substrate and frame glue, and the frame glue is adjacent to the periphery of the second substrate; dripping display medium on the element array substrate; and applying a voltage to the plurality of electrode groups while assembling the element array substrate and the filter substrate so that the sealant adheres the element array substrate and the filter substrate, the plurality of electrode groups are adjacent to the inner side of the sealant, and the display medium is positioned among the element array substrate, the filter substrate and the sealant.

In an embodiment of the invention, the applying the voltage to the plurality of electrode groups is sequentially applying the voltage to each electrode group from the outer side to the inner side.

In an embodiment of the invention, a voltage difference between the electrode pairs ranges from 10 volts to 100 volts.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1A is a schematic top view of a display device 10 according to an embodiment of the invention;

FIG. 1B is a schematic cross-sectional view taken along section line A-A' of FIG. 1A;

FIG. 1C is an enlarged schematic view of region I of the electrode set ES1 of the display device 10 of FIG. 1A;

FIG. 1D is an enlarged schematic view of region II of the electrode set ES1 of the display device 10 of FIG. 1A;

FIG. 1E is an enlarged schematic view of region III of electrode pair EP1 of FIG. 1C;

fig. 2A to 2D are schematic cross-sectional views illustrating a process flow of an assembly method of the display device 10 shown in fig. 1A to 1E;

FIG. 3A is a timing diagram illustrating the application of voltages to a plurality of electrode sets 160 according to one embodiment of the present invention;

FIG. 3B is a timing diagram illustrating the application of voltages to the plurality of electrode sets 160 according to one embodiment of the present invention;

fig. 4 is a schematic top view of an element array substrate AS' according to an embodiment of the invention.

Description of the symbols

10: display device

100: mother substrate

110: first substrate

120: second substrate

122: color filter layer

124: alignment film

130: frame glue

140: display medium layer

150: hydrophobic film

160: multiple electrode groups

A-A': section line

AS, AS': element array substrate

CH: semiconductor layer

CL: center line

D1: width of

D2: line width

DE: drain electrode

DM: display medium

E11, E12: electrode terminal

EA. EF: peripheral edge

EP1, EP2, EP3, EP 4: electrode pair

ES1, ES2, ES3, ES4, ES5, ES 6: electrode group

FS: light filtering substrate

GE: grid electrode

GI: gate insulating layer

I. II, III: region(s)

IS: inner side

P1, P2: common electrode

PE: pixel electrode

PL: planarization layer

And SE: source electrode

SL: cutting wire

SP: distance between each other

t1, t2, t3, t4, t5, t 6: time of day

TH: through hole

TS: thin film transistor

V1, V2, V3, V4, V5, V6: voltage of

VS1, VS 2: voltage source

W1, W2: conducting wire

W11, W12, W13, W14, W21, W22, W23, W24: conducting wire

θ: bending angle

Detailed Description

Fig. 1A is a schematic top view of a display device 10 according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view taken along section line A-A' of FIG. 1A. Fig. 1C is an enlarged schematic view of a region I of the electrode group ES1 of the display device 10 of fig. 1A. Fig. 1D is an enlarged schematic view of a region II of the electrode group ES1 of the display device 10 of fig. 1A. Fig. 1E is an enlarged schematic view of region III of the electrode pair EP1 of fig. 1C. In order to make the representation of the drawings simpler, the components of fig. 1A except the first substrate 110, the sealant 130, the hydrophobic film 150 and the electrode assembly 160 in fig. 1B are omitted. Hereinafter, please refer to fig. 1A to fig. 1E together to clearly understand the overall structure of the display device 10.

Referring to fig. 1A to fig. 1E, the display device 10 includes: the display device includes a first substrate 110, a second substrate 120, a sealant 130, a display medium layer 140, a hydrophobic film 150, and a plurality of electrode sets 160. The second substrate 120 is opposite to the first substrate 110. The sealant 130 is located between the first substrate 110 and the second substrate 120. The display medium layer 140 is located between the first substrate 110, the second substrate 120 and the sealant 130. The hydrophobic film 150 is located between the display medium layer 140 and the first substrate 110, and is adjacent to the sealant 130. The plurality of electrode assemblies 160 are disposed between the hydrophobic film 150 and the display medium layer 140, and each electrode assembly 160 includes a plurality of electrode pairs.

As mentioned above, in the display device 10 according to an embodiment of the present invention, the plurality of electrode groups 160 are arranged to change the contact angle of the display medium in the display medium layer 140 to the hydrophobic film 150, so that the phenomenon of contamination or puncture caused by the display medium contacting the sealant 130 during the process of assembling the first substrate 110 and the second substrate 120 can be avoided, and the reliability of the display device 10 can be further improved.

The following description will be made of embodiments of the elements and the film layers of the display device 10 with reference to fig. 1A to 1E, but the invention is not limited thereto.

Referring to fig. 1A and fig. 1B, the first substrate 110 of the display device 10 may be a transparent substrate, and the material thereof includes a quartz substrate, a glass substrate, a polymer substrate, and the like, but the invention is not limited thereto.

Various film layers for forming switching elements, signal lines, driving elements, storage capacitors, etc. may be disposed on the first substrate 110. For example, in the present embodiment, the display device 10 further includes a thin film transistor TS and a pixel electrode PE, wherein the thin film transistor TS includes a gate electrode GE, a semiconductor layer CH, a source electrode SE and a drain electrode DE, and the pixel electrode PE is electrically connected to the drain electrode DE of the thin film transistor TS through a through hole TH in the planarization layer PL. Gate electrode GE of thin film transistor TS overlaps semiconductor layer CH, and a region where semiconductor layer CH overlaps gate electrode GE can be regarded as a channel region of thin film transistor TS. A gate insulating layer GI is disposed between gate electrode GE and semiconductor layer CH. The source electrode SE and the drain electrode DE of the thin film transistor TS are separated from each other, and the source electrode SE and the drain electrode DE contact the semiconductor layer CH, respectively. In addition, the gate electrode GE may be electrically connected to a scan line (not shown) of the display device 10, and the source electrode SE may be electrically connected to a data line (not shown) of the display device 10. In this way, the thin film transistor TS can be turned on or off by the signal transmitted by the scan line, and the thin film transistor TS can transmit the signal transmitted by the data line to the pixel electrode PE when turned on, and the pixel electrode PE can further drive the display medium in the display medium layer 140 to rotate.

The second substrate 120 of the display device 10 is opposite to the first substrate 110, and the second substrate 120 may be a transparent substrate, such as a quartz substrate, a glass substrate, a polymer substrate, and the like. The display medium layer 140 is located between the first substrate 110 and the second substrate 120, and the display medium layer 140 may include a display material such as a liquid crystal material, an electrophoretic material, or an electrowetting material.

Various films for forming color filter elements and alignment layers may be disposed on the second substrate 120. For example, in the embodiment, the display device 10 further includes a color filter layer 122 and an alignment film 124, the color filter layer 122 is located between the alignment film 124 and the second substrate 120, and the alignment film 124 is located between the display medium layer 140 and the color filter layer 122. The color filter layer 122 may further include a red filter device, a green filter device, and a blue filter device to achieve a full-color display effect. The alignment film 124 may define an initial deflection angle of the display medium (e.g., liquid crystal molecules) in the display medium layer 140. In the present embodiment, the second substrate 120, the color filter layer 122 disposed thereon, and the alignment film 124 may form a filter substrate FS of the display device 10.

The sealant 130 of the display device 10 is sandwiched between the peripheral regions of the first substrate 110 and the second substrate 120 to seal the space between the first substrate 110 and the second substrate 120, so that the display medium can be sealed in the enclosed space formed by the first substrate 110, the second substrate 120 and the sealant 130 to form the display medium layer 140. The sealant 130 may be made of a light-curable adhesive, a heat-curable adhesive, or a combination thereof, but the invention is not limited thereto.

The hydrophobic film 150 may be located on the first substrate 110 in a region adjacent to the sealant 130. For example, in the embodiment, the hydrophobic film 150 may be disposed on the flat layer PL in a region adjacent to the sealant 130, and the hydrophobic film 150 may have a rectangular loop shape, but the invention is not limited thereto. In some embodiments, the hydrophobic film 150 may also be partially located between the sealant 130 and the planarization layer PL. The material of the hydrophobic film 150 may include a dielectric material such as Liquid Crystal Polymer (Liquid Crystal Polymer), but the present invention is not limited thereto.

A plurality of electrode groups 160 may be disposed on the hydrophobic film 150. When a voltage is applied to the plurality of electrode groups 160, a charge distribution is generated on the hydrophobic film 150, thereby changing a contact angle of the display medium in the display medium layer 140 to the hydrophobic film 150. In addition, in the present embodiment, the first substrate 110, the hydrophobic thin film 150, the plurality of electrode groups 160, the thin film transistors TS, the pixel electrodes PE, the planarization layer PL, the gate insulating layer GI, the scanning lines, the data lines, and the like, which are disposed thereon, may constitute the element array substrate AS of the display device 10.

The number of electrode groups in the plurality of electrode groups 160 is not particularly limited. In some embodiments, the plurality of electrode sets 160 may include 2 to 10 electrode sets. For example, in the present embodiment, the plurality of electrode groups 160 may include 6 electrode groups ES1, ES2, ES3, ES4, ES5, and ES 6. In some embodiments, the plurality of electrode sets 160 may include 2, 3, 4, 5, 7, 8, 9, or 10 electrode sets.

In the present embodiment, the 6 electrode groups ES1, ES2, ES3, ES4, ES5, and ES6 of the plurality of electrode groups 160 may be sequentially disposed on the hydrophobic film 150 from the outer side to the inner side of the first substrate 110, and each electrode group is disposed on both sides of the center line CL of the first substrate 110 in a mirror symmetry manner, but the invention is not limited thereto.

The electrode groups ES1, ES2, ES3, ES4, ES5, and ES6 may have the same or similar structures, and the electrode group ES1 is described as an example below.

Referring to fig. 1C and fig. 1D, the width D1 of the electrode group ES1 may be less than 100 μm. For example, in the embodiment, the width D1 of the electrode group ES1 may be about 80 μm, but the invention is not limited thereto.

In the present embodiment, the electrode group ES1 may include 4 pairs of electrode pairs EP1, EP2, EP3, and EP4, but the present invention is not limited thereto. In some embodiments, electrode set ES1 may include 2 to 10 pairs of electrode pairs. The electrode pairs EP1, EP2, EP3 and EP4 may belong to the same film layer as the pixel electrode PE, but the invention is not limited thereto. The electrode pairs EP1, EP2, EP3, EP4 may comprise a transparent conductive material, such as a nitride of a metallic material, an oxide of a metallic material, an oxynitride of a metallic material or other suitable material, or a stack of layers of the above-mentioned conductive materials. In some embodiments, electrode pairs EP1, EP2, EP3, EP4 may include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxide, or a stacked layer of at least two of the foregoing.

For example, in the present embodiment, the electrode pair EP1 may include parallel wires W11 and W21, the electrode pair EP2 may include parallel wires W12 and W22, the electrode pair EP3 may include parallel wires W13 and W23, and the electrode pair EP4 may include parallel wires W14 and W24.

In the present embodiment, the electrode set ES1 may further include two electrode terminals E11 and E12, wherein the electrode terminal E11 may be electrically connected to the wires W11, W12, W13, W14, and the electrode terminal E12 may be electrically connected to the wires W21, W22, W23, W24. In some embodiments, the electrode terminals E11 and E12 may belong to the same layer as the drain electrode DE or the gate electrode GE of the thin film transistor TS. In addition, the electrode terminal E11 may be electrically connected to the common electrode P1, and an electrode terminal of the electrode groups ES2, ES3, ES4, ES5, ES6 on the same side as the electrode terminal E11 may also be electrically connected to the common electrode P1, so that the electrode terminal E11 and an electrode terminal of the electrode groups ES2, ES3, ES4, ES5, ES6 on the same side as the electrode terminal E11 may be electrically connected to each other via the common electrode P1. Similarly, the electrode terminal E12 and the electrode terminals of the electrode groups ES2, ES3, ES4, ES5, ES6 on the same side as the electrode terminal E12 may be electrically connected to each other via a common electrode P2.

Referring to fig. 1E, the spacing SP between the wires W11 and W21 of the electrode pair EP1 may be between 9 μm and 18 μm. For example, in the embodiment, the pitch SP between the conductive wires W11 and W21 may be about 14 μm, but the invention is not limited thereto.

The line widths of the wires W11, W12, W13, W14, W21, W22, W23, W24 may be between 2 μm and 6 μm. For example, in the embodiment, the line width D2 of the conductive line W11 may be about 4 μm, but the invention is not limited thereto.

The ratio of the line width D2 of the wires W11, W21 of the electrode pair EP1 to the pitch SP may be between 1:2 and 1: 8. For example, in the present embodiment, the ratio of the line width D2 to the pitch SP is about 1: 3.5, but the invention is not limited thereto.

In the present embodiment, the wires W11, W12, W13, W14, W21, W22, W23, W24 may have a bent shape, and the wires W11, W12, W13, W14, W21, W22, W23, W24 may have a bent angle θ. The bend angle θ may be between 10 degrees and 50 degrees. For example, in the present embodiment, the bending angle θ may be 30 degrees, but the invention is not limited thereto.

Fig. 2A to 2D are schematic cross-sectional views illustrating a process flow of the assembly method of the display device 10 shown in fig. 1A to 1E. Hereinafter, an assembling method of the display device 10 will be described with reference to fig. 2A to 2D.

Referring to fig. 2A, first, an element array substrate AS is provided. In this embodiment, the element array substrate AS may include the first substrate 110, the thin film transistor TS, the pixel electrode PE, the planarization layer PL, the gate insulating layer GI, the hydrophobic film 150, the plurality of electrode groups 160, and other elements and layers AS described above, wherein the thin film transistor TS includes the gate electrode GE, the semiconductor layer CH, the source electrode SE, and the drain electrode DE, and the pixel electrode PE is electrically connected to the drain electrode DE of the thin film transistor TS. The hydrophobic film 150 is located between the plurality of electrode sets 160 and the first substrate 110, and the hydrophobic film 150 may be adjacent to the periphery EA of the first substrate 110, for example, the hydrophobic film 150 may have a rectangular loop shape. The plurality of electrode groups 160 are disposed on the hydrophobic film 150, and the plurality of electrode groups 160 may include 6 electrode groups ES1, ES2, ES3, ES4, ES5, and ES 6. The electrode groups ES1, ES2, ES3, ES4, ES5, ES6 all include 4 pairs of electrode pairs EP1, EP2, EP3, EP4 and two electrode terminals E11, E12 as shown in fig. 1C to 1D, wherein the electrode pair EP1 may include parallel wires W11, W21, the electrode pair EP2 may include parallel wires W12, W22, the electrode pair EP3 may include parallel wires W13, W23, the electrode pair EP4 may include parallel wires W14, W24, and the electrode terminal E11 may electrically connect the wires W11, W12, W13, W14, the electrode terminal E12 may electrically connect the wires W21, W22, W23, W24.

Next, referring to fig. 2B, a filter substrate FS is provided, and the filter substrate FS may include the second substrate 120, the color filter layer 122, and the alignment film 124 as described above. In the embodiment, the filter substrate FS further includes a sealant 130, and the sealant 130 is disposed adjacent to the periphery EF of the second substrate 120.

Next, referring to fig. 2C, the display medium DM is dropped on the device array substrate AS. In the present embodiment, the display medium DM may include liquid crystal molecules, but the present invention is not limited thereto.

Next, referring to fig. 2D, the filter substrate FS shown in fig. 2B IS inverted by 180 degrees and IS aligned over the device array substrate AS shown in fig. 2C, wherein the orthogonal projection of the plurality of electrode sets 160 on the second substrate 120 IS adjacent to the inner side IS of the orthogonal projection of the sealant 130 on the second substrate 120 through the alignment. Then, a voltage is applied to the plurality of electrode sets 160 to move the display medium DM on the hydrophobic film 150 toward a direction away from the periphery EA, and the element array substrate AS and the filter substrate FS are paired to bond the sealant 130 to the element array substrate AS and the filter substrate FS, and the sealant 130 is cured immediately, so that the display medium DM can be sealed and stored among the element array substrate AS, the filter substrate FS, and the sealant 130. In this way, in the process of pairing the element array substrate AS and the filter substrate FS, the display medium DM may not contact the uncured sealant 130 at all. After the group alignment is completed, the application of the voltage to the plurality of electrode groups 160 may be stopped, and the display medium DM may be moved in the direction of the peripheral edge EA, thereby obtaining the display device 10 shown in fig. 1B.

FIG. 3A is a timing diagram illustrating the application of voltages to a plurality of electrode sets 160 according to one embodiment of the present invention. In the present embodiment, the voltages applied to the plurality of electrode groups 160 are applied to the respective electrode groups in order from the outside to the inside. For example, referring to fig. 3A, in the present embodiment, applying the voltage to the plurality of electrode groups 160 may sequentially start applying the voltage V1 to the electrode group ES1 at time t1, start applying the voltage V2 to the electrode group ES2 at time t2, start applying the voltage V3 to the electrode group ES3 at time t3, start applying the voltage V4 to the electrode group ES4 at time t4, start applying the voltage V5 to the electrode group ES5 at time t5, and start applying the voltage V6 to the electrode group ES6 at time t 6. The above-mentioned "applying the voltage V1 to the electrode group ES 1" means that the voltage difference between the two electrode terminals E11 and E12 of the electrode group ES1 is about V1, that is, the voltage difference between the wire W11 and the wire W21 of the electrode pair EP1 is about V1, and the "applying the voltage V2 to the electrode group ES 2", "applying the voltage V3 to the electrode group ES 3", "applying the voltage V4 to the electrode group ES 4", "applying the voltage V5 to the electrode group ES 5", and "applying the voltage V6 to the electrode group ES 6" have similar meanings, and are not described herein again.

In the present embodiment, the element array substrate AS and the filter substrate FS may be paired during the time period t1 to t 6. In addition, the voltages V1, V2, V3, V4, V5, V6 may be the same, but the present invention is not limited thereto. In addition, the voltages V1, V2, V3, V4, V5, V6 may be between 10 volts and 100 volts. In the present embodiment, the voltages V1, V2, V3, V4, V5, and V6 are about 15 volts, but the present invention is not limited thereto.

FIG. 3B is a timing diagram illustrating the application of voltages to the plurality of electrode sets 160 according to one embodiment of the present invention. In the present embodiment, referring to fig. 3B, the voltage V1 may start to be applied to the electrode group ES1 at time t1, and the voltage V1 may stop being applied to the electrode group ES1 after the voltage V2 starts to be applied to the electrode group ES2 at time t 2. Likewise, the application of the voltage V2 to the electrode group ES2 may be started at time t2, and the application of the voltage V2 to the electrode group ES2 may be stopped after the application of the voltage V3 to the electrode group ES3 is started at time t 3. Likewise, the application of the voltage V3 to the electrode group ES3 may be started at time t3, and the application of the voltage V3 to the electrode group ES3 may be stopped after the application of the voltage V4 to the electrode group ES4 is started at time t 4. Likewise, the application of the voltage V4 to the electrode group ES4 may be started at time t4, and the application of the voltage V4 to the electrode group ES4 may be stopped after the application of the voltage V5 to the electrode group ES5 is started at time t 5. Likewise, the application of the voltage V5 to the electrode group ES5 may be started at time t5, and the application of the voltage V5 to the electrode group ES5 may be stopped after the application of the voltage V6 to the electrode group ES6 is started at time t 6.

In the embodiment shown in fig. 3B, the duration of application of the voltage V1 to the electrode group ES1, the duration of application of the voltage V2 to the electrode group ES2, the duration of application of the voltage V3 to the electrode group ES3, the duration of application of the voltage V4 to the electrode group ES4, the duration of application of the voltage V5 to the electrode group ES5, and the duration of application of the voltage V6 to the electrode group ES6 may be the same, but not limited thereto. Similarly, the element array substrate AS and the filter substrate FS may be paired during the time t1 to the time t 6.

Fig. 4 is a schematic top view of an element array substrate AS' according to an embodiment of the invention. Referring to fig. 4, the device array substrate AS' may include a plurality of device array substrates AS shown in fig. 2A. That is, the element array substrate AS 'may be cut to form a plurality of element array substrates AS, and the mother substrate 100 of the element array substrate AS' may be cut to form a plurality of the first substrates 110. AS described above, each of the element array substrates AS may include a plurality of electrode groups 160, and two electrode terminals of the plurality of electrode groups 160 are electrically connected to the common electrodes P1 and P2, respectively. In the present embodiment, the common electrode P1 of each element array substrate AS can be electrically connected to the voltage source VS1 via the conductive line W1, and the common electrode P2 of each element array substrate AS can be electrically connected to the voltage source VS2 via the conductive line W2. In this way, when the step flow of the assembly method shown in fig. 2A to 2D is performed on the device array substrate AS', a bias voltage can be simultaneously applied to the common electrodes P1 and P2 of each device array substrate AS by the voltage sources VS1 and VS2 during the process of applying the voltages to the plurality of electrode groups 160. In addition, after the steps of the assembling method shown in fig. 2A to 2D are completed, the display devices 10 shown in fig. 1A to 1E can be manufactured in a plurality at a time by performing cutting along the cutting lines SL.

In summary, the invention changes the contact angle of the display medium to the hydrophobic thin film by arranging the plurality of electrode groups, so that the display medium can be prevented from contacting the sealant in the process of substrate pairing, and the reliability of the display device is further improved.

Although the present invention has been described in connection with the above embodiments, it is not intended to limit the present invention, and those skilled in the art may make modifications and alterations without departing from the spirit and scope of the present invention.

Claims

1. A display device, comprising:

a first substrate;

a second substrate opposite to the first substrate;

the frame glue is positioned between the first substrate and the second substrate;

a display medium layer located among the first substrate, the second substrate and the frame glue;

the hydrophobic film is positioned between the display medium layer and the first substrate and is adjacent to the frame glue; and

and the electrode groups are positioned between the hydrophobic film and the display medium layer, and each electrode group comprises a plurality of electrode pairs.

2. The display device of claim 1, wherein the hydrophobic film has a rectangular loop shape.

3. The display device of claim 1, wherein the plurality of electrode sets comprises 2 to 10 electrode sets.

4. The display device of claim 1, wherein the width of each of the electrode sets is less than 100 μm.

5. The display device of claim 1, wherein the plurality of electrode pairs comprises 2 to 10 electrode pairs.

6. The display device of claim 1, wherein the plurality of electrode pairs comprise a transparent conductive material.

7. The display device of claim 1, wherein each of the electrode pairs comprises two parallel conductive lines.

8. The display device according to claim 7, wherein the line width of each of the parallel conductive lines is between 2 μm and 5 μm.

9. The display device of claim 7, wherein the two parallel conductive lines have a pitch between 10 μm and 16 μm.

10. The display device according to claim 7, wherein the ratio of the line width to the space of the two parallel conductive lines is between 1:2 and 1: 8.

11. The display device according to claim 7, wherein each of the parallel conductive lines has a bent shape.

12. The display device according to claim 11, wherein each of the parallel conductive lines has a bending angle between 10 degrees and 50 degrees.

13. The display device of claim 7, wherein each of the electrode sets further comprises two electrode terminals electrically connected to the two parallel conductive lines, respectively.

14. The display device according to claim 13, wherein the two electrode terminals of the plurality of electrode groups are electrically connected to each other, respectively.

15. The display device of claim 1, further comprising a pixel electrode, and the plurality of electrode pairs and the pixel electrode belong to the same film layer.

16. A method of assembling a display device, comprising:

providing an element array substrate, wherein the element array substrate comprises a first substrate, a hydrophobic film and a plurality of electrode groups, the hydrophobic film is positioned between the electrode groups and the first substrate and is adjacent to the periphery of the first substrate, and the electrode groups are positioned on the hydrophobic film and respectively comprise a plurality of electrode pairs;

providing a light filtering substrate, wherein the light filtering substrate comprises a second substrate and frame glue, and the frame glue is adjacent to the periphery of the second substrate;

dripping display medium on the element array substrate; and

the element array substrate and the filter substrate are assembled while voltage is applied to the plurality of electrode groups, so that the frame glue is bonded with the element array substrate and the filter substrate, the plurality of electrode groups are adjacent to the inner side of the frame glue, and the display medium is positioned among the element array substrate, the filter substrate and the frame glue.

17. The method of claim 16, wherein the applying the voltages to the plurality of electrode sets is performed sequentially from outside to inside.

18. The method according to claim 17, wherein the voltage difference between each pair of electrodes is between 10 v and 100 v.