CN113557497A - 指令排序 - Google Patents
指令排序 Download PDFInfo
- Publication number
- CN113557497A CN113557497A CN201980093825.3A CN201980093825A CN113557497A CN 113557497 A CN113557497 A CN 113557497A CN 201980093825 A CN201980093825 A CN 201980093825A CN 113557497 A CN113557497 A CN 113557497A
- Authority
- CN
- China
- Prior art keywords
- instruction
- barrier
- instructions
- data processing
- processing apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 claims abstract description 342
- 238000012545 processing Methods 0.000 claims abstract description 81
- 230000001629 suppression Effects 0.000 claims abstract description 62
- 230000002085 persistent effect Effects 0.000 claims description 35
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 11
- 238000004590 computer program Methods 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 8
- 238000003672 processing method Methods 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 4
- 238000005201 scrubbing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 39
- 230000008569 process Effects 0.000 description 28
- 239000000872 buffer Substances 0.000 description 13
- 238000010791 quenching Methods 0.000 description 11
- 230000001419 dependent effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000003112 inhibitor Substances 0.000 description 3
- 238000013403 standard screening design Methods 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/522—Barrier synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims (27)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/296,507 US10956166B2 (en) | 2019-03-08 | 2019-03-08 | Instruction ordering |
US16/296,507 | 2019-03-08 | ||
PCT/GB2019/053330 WO2020183119A1 (en) | 2019-03-08 | 2019-11-26 | Instruction ordering |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113557497A true CN113557497A (zh) | 2021-10-26 |
Family
ID=68699482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980093825.3A Pending CN113557497A (zh) | 2019-03-08 | 2019-11-26 | 指令排序 |
Country Status (6)
Country | Link |
---|---|
US (2) | US10956166B2 (zh) |
EP (1) | EP3935491B1 (zh) |
JP (1) | JP7474779B2 (zh) |
KR (1) | KR20210134370A (zh) |
CN (1) | CN113557497A (zh) |
WO (1) | WO2020183119A1 (zh) |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6691220B1 (en) * | 2000-06-06 | 2004-02-10 | International Business Machines Corporation | Multiprocessor speculation mechanism via a barrier speculation flag |
US7555607B2 (en) * | 2005-11-10 | 2009-06-30 | Hewlett-Packard Development Company, L.P. | Program thread syncronization for instruction cachelines |
US7587555B2 (en) * | 2005-11-10 | 2009-09-08 | Hewlett-Packard Development Company, L.P. | Program thread synchronization |
US8099582B2 (en) | 2009-03-24 | 2012-01-17 | International Business Machines Corporation | Tracking deallocated load instructions using a dependence matrix |
US8880819B2 (en) | 2011-12-13 | 2014-11-04 | Micron Technology, Inc. | Memory apparatuses, computer systems and methods for ordering memory responses |
US20140032854A1 (en) * | 2012-07-30 | 2014-01-30 | Futurewei Technologies, Inc. | Coherence Management Using a Coherent Domain Table |
US9430166B2 (en) * | 2012-08-10 | 2016-08-30 | International Business Machines Corporation | Interaction of transactional storage accesses with other atomic semantics |
US9304940B2 (en) | 2013-03-15 | 2016-04-05 | Intel Corporation | Processors, methods, and systems to relax synchronization of accesses to shared memory |
US9336097B2 (en) | 2014-02-27 | 2016-05-10 | International Business Machines Corporation | Salvaging hardware transactions |
US20170083338A1 (en) * | 2015-09-19 | 2017-03-23 | Microsoft Technology Licensing, Llc | Prefetching associated with predicated load instructions |
US20170083339A1 (en) * | 2015-09-19 | 2017-03-23 | Microsoft Technology Licensing, Llc | Prefetching associated with predicated store instructions |
US9946492B2 (en) * | 2015-10-30 | 2018-04-17 | Arm Limited | Controlling persistent writes to non-volatile memory based on persist buffer data and a persist barrier within a sequence of program instructions |
US20180032344A1 (en) * | 2016-07-31 | 2018-02-01 | Microsoft Technology Licensing, Llc | Out-of-order block-based processor |
US10474469B2 (en) * | 2017-04-12 | 2019-11-12 | Arm Limited | Apparatus and method for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow |
US11175924B2 (en) * | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
US10606590B2 (en) * | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
-
2019
- 2019-03-08 US US16/296,507 patent/US10956166B2/en active Active
- 2019-11-26 EP EP19809910.3A patent/EP3935491B1/en active Active
- 2019-11-26 CN CN201980093825.3A patent/CN113557497A/zh active Pending
- 2019-11-26 KR KR1020217031696A patent/KR20210134370A/ko active IP Right Grant
- 2019-11-26 WO PCT/GB2019/053330 patent/WO2020183119A1/en active Application Filing
- 2019-11-26 US US17/593,018 patent/US20220004390A1/en active Pending
- 2019-11-26 JP JP2021553333A patent/JP7474779B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2022524127A (ja) | 2022-04-27 |
JP7474779B2 (ja) | 2024-04-25 |
WO2020183119A1 (en) | 2020-09-17 |
US20200285479A1 (en) | 2020-09-10 |
KR20210134370A (ko) | 2021-11-09 |
EP3935491B1 (en) | 2023-08-30 |
US10956166B2 (en) | 2021-03-23 |
EP3935491A1 (en) | 2022-01-12 |
US20220004390A1 (en) | 2022-01-06 |
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Address after: Cambridge County, England Applicant after: Arm Ltd. Applicant after: University of Michigan Council Address before: Cambridge County, England Applicant before: Arm Ltd. Applicant before: University of Michigan board |
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