CN113555282B - Manufacturing method of MOS control thyristor and MOS control thyristor - Google Patents
Manufacturing method of MOS control thyristor and MOS control thyristor Download PDFInfo
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- CN113555282B CN113555282B CN202110659745.9A CN202110659745A CN113555282B CN 113555282 B CN113555282 B CN 113555282B CN 202110659745 A CN202110659745 A CN 202110659745A CN 113555282 B CN113555282 B CN 113555282B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66371—Thyristors structurally associated with another device, e.g. built-in diode
- H01L29/66378—Thyristors structurally associated with another device, e.g. built-in diode the other device being a controlling field-effect device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
Abstract
The invention discloses a manufacturing method of a MOS control thyristor and the MOS control thyristor, wherein the manufacturing method specifically comprises the following steps: s100: forming a first JFET region on a substrate by adopting an ion implantation process; s200: growing an EPI layer on a substrate; s300: forming a second JFET region on the EPI layer by adopting an ion implantation process; s400: communicating the second JFET region with the first JFET region by a diffusion process; s500: performing a grid electrode, a heavily doped N-type region, a heavily doped P-type region and a well region process, and completing a front process; s600: and performing back buffer layer, back heavily doped layer and drain electrode processes, and completing the back process. According to the manufacturing method of the technical scheme, the process flow is simplified, the process window is increased, and the consistency of devices is improved. And meanwhile, the transverse size of the JFET region can be reduced, and the performance of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a method for manufacturing a MOS controlled thyristor and a MOS controlled thyristor.
Background
The MOS controlled thyristor MCT (MOS-Controlled Thyristor) is a field controlled bipolar semiconductor power device, has the characteristic of being capable of controlling the on and off of the device through one grid electrode, has extremely low on voltage drop and high surge current bearing capacity, and also has the limitation of high input impedance, low driving control and high switching speed of the MOS field effect transistor. MCTs are considered to be very promising semiconductor power devices, and have received extensive attention from researchers.
The existing manufacturing process of the MCT device forms an N-type well region, a P-type well region and a JFET region on a substrate through multiple pushing and diffusion processes to form NPN and PNP structures, the process difficulty is high, and the consistency of the manufactured device is difficult to improve. And the JFET region has larger transverse size, so that the number of primary cells in a unit area is limited, the performance of the device is difficult to improve, and the manufacturing cost is difficult to reduce.
Disclosure of Invention
The invention aims to: the invention aims to provide a manufacturing method of a MOS control thyristor, which simplifies the process flow, can reduce the transverse size of a JFET region, reduces the manufacturing cost, improves the consistency of devices and provides space for improving the performance of the devices.
Another object of the present invention is to provide a MOS controlled thyristor manufactured by the above method for manufacturing a MOS controlled thyristor, which has low manufacturing cost and high uniformity.
The technical scheme is as follows: the invention relates to a manufacturing method of a MOS control thyristor, which specifically comprises the following steps:
s100: forming a first JFET region on a substrate by adopting an ion implantation process;
s200: growing an EPI layer on a substrate;
s300: forming a second JFET region on the EPI layer by adopting an ion implantation process;
s400: communicating the second JFET region with the first JFET region by a diffusion process;
s500: performing a grid electrode, a heavily doped N-type region, a heavily doped P-type region and a well region process, and completing a front process;
s600: and performing back buffer layer, back heavily doped layer and drain electrode processes, and completing the back process.
The MOS control thyristor is manufactured by the manufacturing method of the MOS control thyristor, and comprises a substrate, wherein an EPI layer and a JFET region are arranged above the substrate, the lower end of the JFET region extends to a certain depth in the substrate, the JFET region isolates the EPI layer into a left part and a right part, a front heavily doped region and a well region are arranged at the upper part of the EPI layer, a source electrode is arranged above the front heavily doped region, a grid electrode is arranged between the two source electrodes, and a buffer layer, a back heavily doped layer and a drain electrode are sequentially arranged below the substrate.
Further, the JFET region has a lateral dimension in the range of 4 to 5um.
Further, the substrate is an N-type substrate.
Further, the JFET region is formed by phosphorus ion implantation.
Further, the EPI layer is a P-type EPI layer.
Further, the well region is an N-type well region.
Further, the front heavily doped region comprises a heavily doped N-type region and a heavily doped P-type region, the well region is arranged on the inner side of the heavily doped N-type region, and the heavily doped P-type region is arranged between the well region and the heavily doped N-type region.
Further, the buffer layer is an N-type buffer layer.
Further, the back surface heavily doped layer is a P-type heavily doped layer.
The beneficial effects are that: compared with the prior art, the invention has the following advantages:
1. by growing the EPI layer on the substrate instead of forming the well region by multiple injection pushing and diffusion on the substrate, the process flow is simplified, the process window is increased, and the uniformity of the device is improved.
2. The JFET region for isolating the EPI layer from the ground is realized by growing the EPI layer and performing ion implantation twice before and after the EPI layer, so that the transverse size of the JFET region is greatly reduced, the number of cells in a unit area is increased, the device performance is improved, and the manufacturing cost is reduced.
Drawings
Fig. 1 is a flow chart of a manufacturing process of a MOS controlled thyristor of the invention;
fig. 2 is a schematic diagram illustrating a JFET region formation process according to the present invention;
fig. 3 is a schematic cross-sectional structure of a MOS-controlled thyristor according to an embodiment of the invention.
Detailed Description
The technical scheme of the invention is further described below with reference to the accompanying drawings.
Referring to fig. 1 and 2, the method for manufacturing a MOS controlled thyristor according to the present invention includes the following steps S100: forming a first JFET region 210 on the substrate 100 using an ion implantation process;
s200: growing an EPI layer 300 on a substrate 100;
s300: forming a second JFET region 220 on the EPI layer 300 using an ion implantation process;
s400: a diffusion process is used to connect the second JFET region 220 to the first JFET region 210;
s500: performing the processes of the gate 700, the heavily doped N-type region 400, the heavily doped P-type region 410 and the well region 500, and completing the front side process;
s600: the back buffer layer 800, the back heavily doped layer 900 and the drain 1000 processes are performed, and the back process is completed.
According to the method for manufacturing the MOS control thyristor in the technical scheme, the process of repeatedly injecting ions, pushing and diffusing to form the well region 500, the doped region and the JFET region 200 on the substrate 100 is replaced by growing an EPI (epitaxial) layer on the substrate 100 and doping trivalent boron, gallium and aluminum atoms on the EPI layer 300 to form a PN junction, so that the production flow is simplified, the process window is increased, and the consistency of manufactured devices is optimized. Referring to fig. 2, in addition, by performing ion implantation twice before and after growing the EPI layer 300, forming the first JFET region 210 and the second JFET region 220 on the EPI layer 300, respectively, and then isolating the two JFET regions by a diffusion process, the lateral dimensions of the JFET regions can be greatly reduced, thereby improving the number of cells per unit area and improving the performance of the device.
It is understood that EPI layer 300 may be formed by vapor phase epitaxy, liquid phase epitaxy, solid phase epitaxy, molecular beam epitaxy, and the like. The front side process and the back side process comprise metallization, oxidation, surface passivation and the like. The specific steps of the doping region, the well region 500, the buffer layer 800, the source electrode 600, the gate electrode 700, the drain electrode 1000, the ion implantation, the epitaxial growth, and the front and back surface processes of the device mentioned in the above method are common knowledge of those skilled in the art, and they are not described herein in detail.
Referring to fig. 2, before ion implantation is performed twice, a photoresist 110 needs to be coated on the substrate 100 and EPI layer 300, respectively, to control the lateral dimensions of the JFET region 200.
Referring to fig. 3, the MOS controlled thyristor manufactured by the above-described method of manufacturing a MOS controlled thyristor includes a substrate 100, an EPI layer 300 and a JFET region 200 disposed over the substrate 100. The segment of the JFET region 200 extends to a depth within the substrate 100, the JFET region 200 divides the EPI layer 300 into left and right portions, and a front heavily doped region and a well region 500 are disposed on the EPI layer 300, and the front heavily doped region includes a heavily doped N-type region 400 and a heavily doped P-type region 410. A source 600 is disposed above the front heavily doped region, a gate 700 is disposed between the two sources 600, and the gate 700, the front heavily doped region, the well region 500, the EPI layer 300, and the JFET region 200 form NMOS and PMOS that control the device to be turned on and off. The underside of the substrate 100 is provided with a buffer layer 800, a back heavily doped layer 900 and a drain 1000 in this order from top to bottom.
In some embodiments, the lateral dimensions of JFET region 200 range between 4 and 5um.
In this embodiment, the substrate 100 is an N-type substrate, and accordingly, the JFET region 200 is formed by phosphorus ion implantation, the EPI layer 300 is a P-type EPI layer 300, the well region 500 is an N-type well region, the buffer layer 800 is an N-type buffer layer 800, and the back heavily doped layer 900 is a P-type heavily doped layer. The well region 500 is disposed inside the heavily doped N-type region 400, and the heavily doped P-type region 410 is disposed between the well region 500 and the heavily doped N-type region 400.
It is understood that the substrate 100 may also be a P-type substrate 100, and the positions of the jfet region 200, EPI layer 300, well region 500, buffer layer 800, and back heavily doped layer 900, and the heavily doped P-type region 410, the heavily doped N-type region 400, and the well region 500 may be adaptively adjusted to form a PN junction.
Claims (10)
1. A method of manufacturing a MOS controlled thyristor, comprising the steps of:
s100: forming a first JFET region (210) on a substrate (100) using an ion implantation process;
s200: growing an EPI layer (300) on a substrate (100);
s300: forming a second JFET region (220) on the EPI layer (300) using an ion implantation process;
s400: communicating the second JFET region (220) with the first JFET region (210) using a diffusion process;
s500: performing a gate (700), heavily doped N-type region (400), heavily doped P-type region (410) and well region (500) process, and completing a front side process;
s600: and performing a back buffer layer (800), a back heavily doped layer (900) and a drain electrode (1000) process, and completing the back process.
2. The MOS controlled thyristor manufactured by the method of claim 1, comprising a substrate (100), wherein an EPI layer (300) and a JFET region (200) are disposed above the substrate (100), the lower end of the JFET region (200) extends to a certain depth into the substrate (100), the JFET region (200) isolates the EPI layer (300) into left and right parts, a front heavily doped region and a well region (500) are disposed at the upper part of the EPI layer (300), a source electrode (600) is disposed above the front heavily doped region, a gate electrode (700) is disposed between the two source electrodes (600), and a buffer layer (800), a back heavily doped layer (900) and a drain electrode (1000) are sequentially disposed below the substrate (100).
3. The MOS controlled thyristor of claim 2, characterized in that the JFET region (200) has a lateral dimension in the range of 4 to 5um.
4. A MOS controlled thyristor according to claim 2, characterized in that the substrate (100) is an N-type substrate.
5. The MOS controlled thyristor of claim 4, wherein the JFET region (200) is formed by phosphorus ion implantation.
6. The MOS controlled thyristor of claim 4, wherein the EPI layer (300) is a P-type EPI layer.
7. The MOS controlled thyristor of claim 4, wherein the well region (500) is an N-type well region.
8. The MOS controlled thyristor of claim 4, wherein the front heavily doped region comprises a heavily doped N-type region (400) and a heavily doped P-type region (410), the well region (500) is disposed inside the heavily doped N-type region (400), and the heavily doped P-type region (410) is disposed between the well region (500) and the heavily doped N-type region (400).
9. The MOS controlled thyristor of claim 4, wherein the buffer layer (800) is an N-type buffer layer (800).
10. A MOS controlled thyristor according to claim 4, characterized in that the back heavily doped layer (900) is a P-type heavily doped layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110659745.9A CN113555282B (en) | 2021-06-15 | 2021-06-15 | Manufacturing method of MOS control thyristor and MOS control thyristor |
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| CN202110659745.9A CN113555282B (en) | 2021-06-15 | 2021-06-15 | Manufacturing method of MOS control thyristor and MOS control thyristor |
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| CN113555282A CN113555282A (en) | 2021-10-26 |
| CN113555282B true CN113555282B (en) | 2023-08-08 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991010265A1 (en) * | 1989-12-22 | 1991-07-11 | Daimler-Benz Aktiengesellschaft | Field-effect-controlled semiconductor component |
| US5874751A (en) * | 1995-04-05 | 1999-02-23 | Fuji Electric Co., Ltd. | Insulated gate thyristor |
| US6107649A (en) * | 1998-06-10 | 2000-08-22 | Rutgers, The State University | Field-controlled high-power semiconductor devices |
| CN102782845A (en) * | 2010-04-15 | 2012-11-14 | 菅原良孝 | Semiconductor device |
| CN109155329A (en) * | 2016-05-23 | 2019-01-04 | 通用电气公司 | Electric field shielding in silicone carbide metal oxide semiconductor (MOS) device with optimization layer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8866150B2 (en) * | 2007-05-31 | 2014-10-21 | Cree, Inc. | Silicon carbide power devices including P-type epitaxial layers and direct ohmic contacts |
| US7687825B2 (en) * | 2007-09-18 | 2010-03-30 | Cree, Inc. | Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication |
-
2021
- 2021-06-15 CN CN202110659745.9A patent/CN113555282B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991010265A1 (en) * | 1989-12-22 | 1991-07-11 | Daimler-Benz Aktiengesellschaft | Field-effect-controlled semiconductor component |
| US5874751A (en) * | 1995-04-05 | 1999-02-23 | Fuji Electric Co., Ltd. | Insulated gate thyristor |
| US6107649A (en) * | 1998-06-10 | 2000-08-22 | Rutgers, The State University | Field-controlled high-power semiconductor devices |
| CN102782845A (en) * | 2010-04-15 | 2012-11-14 | 菅原良孝 | Semiconductor device |
| CN109155329A (en) * | 2016-05-23 | 2019-01-04 | 通用电气公司 | Electric field shielding in silicone carbide metal oxide semiconductor (MOS) device with optimization layer |
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| CN113555282A (en) | 2021-10-26 |
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