CN113541484B

CN113541484B - Power converter

Info

Publication number: CN113541484B
Application number: CN202011022211.7A
Authority: CN
Inventors: 刘国基; 白忠龙
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2020-04-20
Filing date: 2020-09-25
Publication date: 2022-11-22
Anticipated expiration: 2040-09-25
Also published as: CN113541484A; TWI742851B; TW202141911A

Abstract

A power converter, comprising: a plurality of capacitors; the switches are correspondingly coupled with the capacitors and respectively switch the electrical connection relation of the corresponding capacitors according to the corresponding operating signals; at least one charging inductor which is correspondingly connected in series with at least one of the plurality of capacitors; and at least one discharge inductor which is correspondingly connected in series with at least one of the plurality of capacitors. In the charging process, the plurality of capacitors and the at least one charging inductor are connected in series between an input voltage and an output voltage through the switching of the plurality of switches to form a charging path; in the discharging process, each capacitor and the corresponding discharging inductor are connected in series between the output voltage and the ground potential through the switching of the switches to form a plurality of discharging paths; the charging process and the discharging process are repeatedly staggered.

Description

Power converter

Technical Field

The present invention relates to a power converter, and more particularly, to a power converter that converts an input voltage into an output voltage by switching an electrical connection relationship between a capacitor and an inductor.

Background

Fig. 1 shows a known power converter. In the charging operation, the switches Q1, Q3, Q5, Q8, Q9 are turned on, and the switches Q2, Q4, Q6, Q7, Q10 are turned off, such that the capacitor C1 is connected in series with the inductor L1 between the input voltage VIN and the output voltage VOUT, and the capacitor C2 is connected in series with the capacitor C3 and the inductor L2 between the ground potential and the output voltage VOUT. In the discharging operation, the switches Q2, Q4, Q6, Q7, Q10 are turned on, and the switches Q1, Q3, Q5, Q8, Q9 are turned off, so that the inductor L1 is connected in series with the capacitor C1 and the capacitor C2 between the ground potential and the output voltage VOUT, and the inductor L2 is connected in series with the capacitor C3 between the ground potential and the output voltage VOUT. The capacitor of the conventional power converter needs to withstand a higher rated voltage, for example, the dc bias of the capacitor C1 is 3 times Vc1=3VOUT of the output voltage, the dc bias of the capacitor C2 is 2 times Vc2=2VOUT of the output voltage, and the dc bias of the capacitor C3 is equal to Vc3= VOUT of the output voltage. In addition, the capacitance of the capacitor usually decreases with the increase of the dc bias voltage, and when the input voltage ranges between 36V and 76V, the dc bias voltage of the capacitor C1 ranges between 27V and 57V. This results in large switching power losses and requires complex controls to change the power conversion efficiency. Moreover, the voltage conversion ratio of the input voltage VIN to the output voltage VOUT of the conventional power converter can only be 4.

Fig. 2 shows another conventional power converter, which is an interleaved power converter of the conventional power converter. In the first charging operation, the switches Q1, Q3, Q5, Q8, Q9 are turned on, and the switches Q2, Q4, Q6, Q7, Q10 are turned off, so that the capacitor C1 is connected in series with the inductor L1 between the input voltage Vin and the output voltage Vout, and the capacitor C2 is connected in series with the capacitor C3 and the inductor L2 between the ground potential and the output voltage Vout. In the first discharging operation, the switches Q2, Q4, Q6, Q7, Q10 are turned on, and the switches Q1, Q3, Q5, Q8, Q9 are turned off, so that the inductor L1 is connected in series with the capacitor C1 and the capacitor C2 between the ground potential and the output voltage Vout, and the inductor L2 is connected in series with the capacitor C3 between the ground potential and the output voltage Vout. In the second charging operation, the switches Q11, Q13, Q15, Q18, Q19 are turned on, and the switches Q12, Q14, Q16, Q17, Q20 are turned off, such that the capacitor C4 is connected in series with the inductor L3 between the input voltage Vin and the output voltage Vout, and the capacitor C5 is connected in series with the capacitor C6 and the inductor L4 between the ground potential and the output voltage Vout. In the second discharging operation, the switches Q12, Q14, Q16, Q17, Q20 are turned on, the switches Q11, Q13, Q15, Q18, Q19 are turned off, so that the inductor L3 is connected in series with the capacitor C4 and the capacitor C5 between the ground potential and the output voltage Vout, and the inductor L4 is connected in series with the capacitor C6 between the ground potential and the output voltage Vout. The first charging operation and the second discharging operation are performed simultaneously, and the first discharging operation and the second charging operation are performed simultaneously. As with the power converter shown in fig. 1, the capacitor of the conventional power converter has a larger dc bias, and therefore requires a higher rated voltage and a larger capacitor size. In addition, the capacitance variation causes the resonant frequency to change and results in higher switching power loss. Therefore, the known power converter requires complicated control to change the power conversion efficiency.

In view of the above, the present invention provides an innovative power converter to overcome the above-mentioned shortcomings in the prior art.

Disclosure of Invention

In one aspect, the present invention provides a power converter for converting an input voltage into an output voltage, the power converter comprising: a plurality of first capacitors; a plurality of first switches, coupled to the plurality of first capacitors, for switching the electrical connection relationship of the corresponding first capacitors according to a corresponding first operation signal; at least one charging inductor which is correspondingly connected in series with at least one of the first capacitors; and at least one discharge inductor correspondingly connected in series with at least one of the first capacitors; in a first charging procedure, the plurality of first capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage through the switching of the plurality of first switches to form a first charging path; in a first discharging procedure, each first capacitor and the corresponding discharging inductor are connected in series between the output voltage and a grounding potential through the switching of the plurality of first switches to form a plurality of first discharging paths; the first charging process and the first discharging process are repeatedly and alternately sequenced to convert the input voltage into the output voltage.

In an embodiment, the at least one charging inductor is a plurality of charging inductors respectively connected in series with the plurality of first capacitors, and in the first charging process, the plurality of first capacitors and the plurality of charging inductors are connected in series between the input voltage and the output voltage by switching the plurality of first switches to form the first charging path; in the first discharging procedure, the plurality of charging inductors are used as the plurality of discharging inductors, and the plurality of discharging inductors and the plurality of first capacitors are respectively connected in series between the output voltage and the grounding potential correspondingly through the switching of the plurality of first switches so as to form the plurality of first discharging paths, wherein the plurality of first discharging paths are connected in parallel with each other.

In an embodiment, the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor, and in the first discharging procedure, the plurality of first capacitors are connected in parallel with each other and then connected in series with the single discharging inductor through switching of the plurality of first switches.

In one embodiment, the power converter further includes: a plurality of second capacitors; and a plurality of second switches, which are correspondingly coupled with the plurality of second capacitors and respectively switch the electrical connection relation of the corresponding second capacitors according to a corresponding second operation signal; wherein, the at least one charging inductor is correspondingly connected in series with at least one of the plurality of second capacitors; wherein, the at least one discharge inductor is correspondingly connected in series with at least one of the plurality of second capacitors; wherein, in a second charging procedure, the plurality of second capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage by switching the plurality of second switches to form a second charging path; in a second discharging procedure, each second capacitor and the corresponding discharging inductor are connected in series between the output voltage and a ground potential through the switching of the plurality of second switches to form a plurality of second discharging paths; wherein the second charging process and the second discharging process are repeatedly interleaved to convert the input voltage into the output voltage; wherein, the power converter executes the second discharging procedure during the first charging procedure; the power converter executes the second charging procedure during the first discharging procedure.

In one embodiment, the power converter further comprises a front-end converter, wherein the front-end converter has a front-end inductor as the charging inductor.

In one embodiment, the front-end converter includes a buck converter, a boost converter, or a buck-boost converter.

In one embodiment, the first charging process has a first charging resonant frequency, and the first discharging process has a first discharging resonant frequency, and the first charging resonant frequency is the same as the first discharging resonant frequency.

In one embodiment, the second charging process has a second charging resonant frequency, and the second discharging process has a second discharging resonant frequency, and the second charging resonant frequency is the same as the second discharging resonant frequency.

In one embodiment, the duration of the first charging process is equal to the duration of the first discharging process, so as to achieve zero current switching of soft switching (soft switching).

In one embodiment, the second charging process is equal to the second discharging process, so as to achieve zero current switching of the soft switching.

In one embodiment, the duration of the second discharge process is adjusted to achieve zero-voltage switching for soft switching.

In one embodiment, the power converter is a bi-directional power converter.

In one embodiment, a voltage conversion ratio of the input voltage to the output voltage of the power converter is 4.

In one embodiment, the duration of the first charging process and the duration of the first discharging process do not overlap with each other.

In an embodiment, the duration of the second charging process and the duration of the second discharging process do not overlap each other.

In one embodiment, the power converter may further include a controller coupled to the plurality of first switches or the plurality of second switches for generating the first operation signal or the second operation signal.

One advantage of the present invention is that the present invention reduces the number of inductors and achieves a resonant capacitance using a smaller capacitor size.

Another advantage of the present invention is that the present invention can reduce voltage stress, have better dynamic load transient response, have better current-voltage balance, and have stable resonant frequency.

Still another advantage of the present invention is that the present invention is easier to control to achieve flexible switching with Zero Current Switching (ZCS) or Zero Voltage Switching (ZVS), and can more flexibly modulate the voltage conversion ratio, and has a wider input voltage application range, and can control the output voltage within a more precise range than the prior art.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1 shows a known power converter.

Fig. 2 is another known power converter.

Fig. 3 is a circuit diagram of a power converter according to an embodiment of the invention.

Fig. 4A and 4B are signal waveforms illustrating circuits and related signals of a power converter according to another embodiment of the invention.

Fig. 5 is a circuit diagram of a power converter according to yet another embodiment of the invention.

Fig. 6 is a circuit diagram of a power converter according to yet another embodiment of the invention.

FIG. 7 is a circuit diagram of a power converter according to yet another embodiment of the invention.

FIG. 8 is a circuit diagram of a power converter according to yet another embodiment of the invention.

FIG. 9 is a circuit diagram of a power converter according to yet another embodiment of the invention.

Fig. 10 is a circuit diagram of a power converter according to yet another embodiment of the invention.

Fig. 11A, 11B and 11C are signal waveform diagrams illustrating corresponding operation signals and corresponding inductor currents of a charging process and a discharging process according to an embodiment of the invention.

Fig. 11D is a signal waveform diagram illustrating corresponding operation signals and corresponding capacitor currents of a charging process and a discharging process according to an embodiment of the invention.

Fig. 12A-12J show a buck converter, a boost converter, a back-pressure converter, a buck-boost converter, and a boost-back-pressure converter.

FIG. 13 is a diagram illustrating a controller in a power converter according to an embodiment of the invention.

Description of the symbols in the drawings

30 40, 50, 60, 70, 80, 90, 100 power converter

501 701, 1001 front-end converter

1301, controller

C1-C3 first capacitor

C4-C6 second capacitor

C1 (CR), C2 (CF), C3 (CR), C4 (CR), C5 (CF), C6 (CR) capacitance

Co output capacitance

G1-G10 operation signals

Ic1 first capacitor C1 Current

IL1 charging inductor current

IL2 discharge inductance current

Io output current

IS7 first switch Q7 Current

IS9 first switch Q9 Current

L1-L3 charging inductor (discharging inductor)

L1 (LR), L2 (LR), L3 (LR), L4 (LR), inductance

Q1 to Q10 first switch

Q11 to Q20 second switch

Q1 (S1A), Q2 (S2A), Q3 (S1B), Q4 (S2B), Q5 (S1A), Q6 (S2A), Q7 (S2A), Q8 (S1B), Q9 (S1B), Q10 (S2B), Q11 (S2C), Q12 (S1C), Q13 (S2D), Q14 (S1D), Q15 (S2C), Q16 (S1C), Q17 (S1C), Q18 (S2D), Q19 (S2D), Q20 (S1D), qb, qb1, qb2: switch

RL load resistance

T1, T2, T3 period

Td delay time

V1 voltage

Vc1 first capacitor C1 DC bias

Vc2 DC bias of a second capacitor C2

Vc3 third capacitor C3 DC bias

Vin is input voltage

Vout output voltage

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Fig. 3 is a circuit diagram of a power converter according to an embodiment of the invention. As shown in fig. 3, the power converter 30 of the present invention includes a first capacitor C1, a first capacitor C2, a first capacitor C3, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a first switch Q8, a first switch Q9, a first switch Q10, a charging inductor L1, a charging inductor L2, and a charging inductor L3. The first switches Q1-Q3 are respectively connected in series with corresponding first capacitors C1-C3, and the first capacitors C1-C3 are respectively connected in series with corresponding charging inductors L1-L3. It should be noted that the number of capacitors in the power converter of the present invention is not limited to three, and may also be two or more than four, and the number of inductors is not limited to three, and may also be two or more than four.

As shown in fig. 3, one end of the first switch Q5 is coupled to a node between the first switch Q1 and the first capacitor C1, one end of the first switch Q6 is coupled to a node between the first switch Q2 and the first capacitor C2, and one end of the first switch Q7 is coupled to a node between the first switch Q3 and the first capacitor C3. One terminal of the first switch Q8 is coupled to the node between the charging inductor L1 and the first switch Q2, one terminal of the first switch Q9 is coupled to the node between the charging inductor L2 and the first switch Q3, and one terminal of the first switch Q10 is coupled to the node between the charging inductor L3 and the first switch Q4. As shown in FIG. 3, the other terminals of the first switches Q5-Q7 are commonly coupled to the output voltage Vout. The other terminals of the first switches Q8-Q10 are commonly coupled to ground potential. The first switch Q4 is coupled between the charging inductor L3 and the output voltage Vout, and one end of the first switch Q1 is coupled to the input voltage Vin.

The first switches Q1 to Q10 can switch the electrical connection relationship between the corresponding first capacitors C1 to C3 and the charging inductors L1 to L3 according to the corresponding operation signals. In a first charging process, the first switches Q1-Q4 are turned on and the first switches Q5-Q10 are turned off, such that the first capacitors C1-C3 and the charging inductors L1-L3 are connected in series between the input voltage Vin and the output voltage Vout to form a first charging path. In a first discharging procedure, the charging inductors L1-L3 can be used as the discharging inductors L1-L3, the first switches Q5-Q10 are turned on, the first switches Q1-Q4 are turned off, so that the first capacitor C1 and the corresponding discharging inductor L1 are connected in series between the output voltage Vout and the ground potential, the first capacitor C2 and the corresponding discharging inductor L2 are connected in series between the output voltage Vout and the ground potential, and the first capacitor C3 and the corresponding discharging inductor L3 are connected in series between the output voltage Vout and the ground potential, thereby forming a plurality of first discharging paths. It should be noted that the first charging process and the first discharging process are performed alternately, not simultaneously, in different time periods. The first charging process and the first discharging process are repeatedly and alternately ordered to convert the input voltage Vin into the output voltage Vout. In the present embodiment, the dc bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in the present embodiment need to withstand a lower rated voltage, and thus a capacitor with a smaller volume can be used.

In one embodiment, the duration of the first charging process is substantially a duty cycle (duty cycle) of a specific ratio, such as but not limited to substantially a fifty percent duty cycle; therefore, the first switch can be switched at the time point when the current flowing through the first switch is at a relatively low level of the positive half wave, so as to realize flexible switching. In a preferred embodiment, zero Current Switching (ZCS) is achieved.

Further, it should be noted that: since the parasitic effect of the circuit components or the matching between the components is not necessarily ideal, although the duration of the first charging process is equal to the duration of the first discharging process (i.e. the duration of the first charging process is fifty percent of the duty cycle), the zero-current switching of soft switching (soft switching) is achieved. However, it may not be exactly fifty percent duty cycle, but only close to fifty percent duty cycle, that is, it is acceptable according to the present invention that the duration of the first charging process has a certain degree of error from the duration of the fifty percent duty cycle due to the non-ideality of the circuit, i.e., the aforementioned discharge to the "substantial" fifty percent duty cycle is meant, as is the case with the other reference to "substantial" herein.

In one embodiment, the specific ratio is related to the resonant frequency. In an embodiment, the first charging process has a first charging resonant frequency, and the first discharging process has a first discharging resonant frequency. In a preferred embodiment, the first charging resonant frequency is the same as the first discharging resonant frequency.

In one embodiment, the power converter 30 may be a bidirectional power converter. By bi-directional power converter, it is meant that the roles of the input terminal (providing the input voltage Vin) and the output terminal (providing the output voltage Vout) are reversed, i.e. the power converter 30 can convert the output voltage Vout into the input voltage Vin in the embodiment shown in fig. 3. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the power converter 30 may be 4. It should be noted that the power converter of the present embodiment is 4, however, the power converter of the present embodiment can be changed to the power converter of 3. In one embodiment, the resonant frequency of the first capacitor C1 and the first inductor L1 is

The resonant frequency of the first capacitor C2 and the first inductor L2 is

The resonant frequency of the first capacitor C3 and the first inductor L3 is

Assuming that C1= C2= C3= Cr and L1= L2= L3= Lr, the first charging resonant frequency and the first discharging resonant frequency of the power converter 30 shown in fig. 3 are set to be equal to

In one embodiment, the capacitance values of C1, C2, and C3 may be different from each other, and the inductance values of L1, L2, and L3 may be different from each other, as long as L1C1= L2C2= L3C 3.

FIG. 4A is a circuit diagram of a power converter according to another embodiment of the invention; fig. 4B is a schematic diagram illustrating signal waveforms of related signals in the power converter shown in fig. 4A. The difference between this embodiment and the previous embodiment is that the plurality of capacitors share a charging inductor or a discharging inductor, so that only one charging inductor and one discharging inductor are needed no matter how many capacitors are, and the number of inductors can be further reduced. As shown in fig. 4A, the power converter 40 of the present invention includes a first capacitor C1, a first capacitor C2, a first capacitor C3, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a first switch Q8, a first switch Q9, a first switch Q10, a charging inductor L1, and a discharging inductor L2. The first switches Q1-Q3 are respectively connected in series with the corresponding first capacitors C1-C3, and the first switch Q4 is connected in series with the charging inductor L1. It should be noted that the number of capacitors in the power converter of the present invention is not limited to three in the present embodiment, and may be two or more than four.

As shown in fig. 4A, one end of the first switch Q5 is coupled to a node between the first switch Q1 and the first capacitor C1, one end of the first switch Q6 is coupled to a node between the first switch Q2 and the first capacitor C2, and one end of the first switch Q7 is coupled to a node between the first switch Q3 and the first capacitor C3. One terminal of the first switch Q8 is coupled to a node between the first capacitor C1 and the first switch Q2, one terminal of the first switch Q9 is coupled to a node between the first capacitor C2 and the first switch Q3, and one terminal of the first switch Q10 is coupled to a node between the first capacitor C3 and the first switch Q4. As shown in fig. 4A, the other ends of the first switches Q5 to Q7 are electrically connected to a node in common and then connected to the discharge inductor L2 in series. The other terminals of the first switches Q8-Q10 are commonly coupled to ground potential. The other ends of the charging inductor L1 and the discharging inductor L2 are coupled to the output voltage Vout together, and the other end of the first switch Q1 is coupled to the input voltage Vin.

The first switches Q1 to Q10 can switch the electrical connection relationship between the corresponding first capacitors C1 to C3 and the charging inductor L1 and the discharging inductor L2 according to the corresponding operation signals. In a first charging process, the first switches Q1-Q4 are turned on, and the first switches Q5-Q10 are turned off, so that the first capacitors C1-C3 are connected in series with the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a first charging path. In a first discharging procedure, the first switches Q5-Q10 are turned on, and the first switches Q1-Q4 are turned off, so that the first capacitor C1, the first capacitor C2 and the first capacitor C3 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of first discharging paths. It should be noted that the first charging process and the first discharging process are performed alternately, not simultaneously, in different time periods. In the present embodiment, the dc bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in the present embodiment need to withstand a lower rated voltage, and thus a capacitor with a smaller volume can be used.

In one embodiment, the duration of the first charging process is substantially a duty cycle (duty cycle) of a specific ratio, such as but not limited to substantially a fifty percent duty cycle; therefore, the first switch can be switched at the time point when the current flowing through the first switch is relatively low in the positive half wave, so that flexible switching is realized. In a preferred embodiment, zero Current Switching (ZCS) is achieved.

In one embodiment, the duration of the first charging process is less than a specific percentage of the duty cycle for a first predetermined period, such as but not limited to less than fifty percent of the duty cycle for the first predetermined period; therefore, after the first switches Q1 to Q4 are turned off in advance, a small current is still maintained and flows through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the first switch Q10 can be taken away through the parasitic diode of the first switch Q4, thereby reducing the voltage across the first switch Q10 and achieving flexible switching. In a preferred embodiment, the first predetermined period is adjusted to achieve zero-voltage switching.

In one embodiment, the duration of the first discharging procedure is greater than a specific percentage of the duty cycle for a second predetermined period, such as but not limited to greater than fifty percent of the duty cycle for the second predetermined period; therefore, after the first switches Q5 to Q10 are delayed to be turned off, the negative current of the discharging inductor L2 charges the parasitic capacitor of the first switch Q1 through the parasitic diode of the first switch Q5, and the voltage across the first switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the second predetermined period is adjusted to achieve zero-voltage switching. In other embodiments, the time point of the non-conducting switch can be advanced or delayed according to actual requirements, so as to realize the zero-voltage switching of the flexible switching.

In one embodiment, the specific ratio is related to the resonant frequency. In one embodiment, the first charging process has a first charging resonant frequency, and the first discharging process has a first discharging resonant frequency. In a preferred embodiment, the first charging resonant frequency is the same as the first discharging resonant frequency.

In one embodiment, the power converter 40 may be a bidirectional power converter. In one embodiment, the voltage conversion ratio between the input voltage Vin and the output voltage Vout of the power converter 40 can be 4. In one embodiment, the first charging resonant frequency is

The first discharge resonant frequency is

If fr4= fr5 is desired and C1= C2= C3 is assumed, then the inductance values of L1 and L2 are setNeed to meet

In an embodiment, the duration of the first charging process and the duration of the first discharging process do not overlap each other. In an embodiment, the duration of the second charging process and the duration of the second discharging process do not overlap with each other.

Fig. 4B is a schematic diagram illustrating signal waveforms of related signals in the power converter shown in fig. 4A. Fig. 4B shows the output voltage Vout, the output current Io, the charging inductor current IL1, the discharging inductor current IL2, the dc bias Vc1 of the first capacitor C1, the current Ic1 of the first capacitor C1, the current IS7 of the first switch Q7, and the current IS9 of the first switch Q9. In the present embodiment, the first charging resonant frequency is equal to the first discharging resonant frequency and the duration of the first charging process is substantially fifty percent of the duty cycle.

FIG. 5 is a circuit diagram of a power converter according to yet another embodiment of the invention. The difference between the present embodiment and the embodiment shown in fig. 4 is that the charging inductor of the present embodiment can be shifted between the input voltage Vin and the first capacitor C1, and the front-end inductor in the front-end converter 501 is used as the charging inductor L1, so as to further reduce the number of inductors. Further, since the front-end converter 501 has a switch therein, the switch in the front-end converter 501 may also be used as the first switch Q1. As shown in fig. 5, the power converter 50 of the present invention includes a first capacitor C1, a first capacitor C2, a first capacitor C3, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a first switch Q8, a first switch Q9, a first switch Q10, a charging inductor L1, and a discharging inductor L2. The first capacitors C1-C3 are respectively connected in series with the corresponding first switches Q2-Q4, and the first switch Q1 is connected in series with the charging inductor L1. It should be noted that the number of capacitors in the power converter of the present invention is not limited to three in the present embodiment, and may be two or more than four.

As shown in fig. 5, one end of the first switch Q5 is coupled to a node between the charging inductor L1 and the first capacitor C1, one end of the first switch Q6 is coupled to a node between the first switch Q2 and the first capacitor C2, and one end of the first switch Q7 is coupled to a node between the first switch Q3 and the first capacitor C3. One terminal of the first switch Q8 is coupled to a node between the first capacitor C1 and the first switch Q2, one terminal of the first switch Q9 is coupled to a node between the first capacitor C2 and the first switch Q3, and one terminal of the first switch Q10 is coupled to a node between the first capacitor C3 and the first switch Q4. As shown in FIG. 5, the other terminals of the first switches Q5-Q7 are connected in series to the discharge inductor L2, and the other terminals of the first switches Q8-Q10 are commonly coupled to the ground potential. The other end of the discharging inductor L2 is coupled to the output voltage Vout, the other end of the first switch Q1 is coupled to the input voltage Vin, and the other end of the charging inductor L1 is coupled to the first capacitor C1.

In one embodiment, the power converter 50 may be a bidirectional power converter. In one embodiment, the voltage conversion ratio between the input voltage Vin and the output voltage Vout of the power converter 50 can be 4. In one embodiment, the front-end converter 501 is used for converting the input voltage Vin to a voltage V1, and includes, but is not limited to, a buck converter, a boost converter, a buck-boost converter, and a buck-boost converter as shown in fig. 12A-12J.

Fig. 6 is a circuit diagram of a power converter according to yet another embodiment of the invention. The power converter of the present embodiment is an interleaved power converter. As shown in fig. 6, the power converter 60 of the present invention includes a first capacitor C1, a first capacitor C2, a first capacitor C3, a second capacitor C4, a second capacitor C5, a second capacitor C6, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a first switch Q8, a first switch Q9, a first switch Q10, a second switch Q11, a second switch Q12, a second switch Q13, a second switch Q14, a second switch Q15, a second switch Q16, a second switch Q17, a second switch Q18, a second switch Q19, a second switch Q20, a charging inductor L1, and a discharging inductor L2. The first switches Q1-Q3 are respectively connected in series with the corresponding first capacitors C1-C3, while the first switch Q4 is coupled to the charging inductor L1, the second switches Q11-Q13 are respectively connected in series with the corresponding second capacitors C4-C6, and the second switch Q14 is coupled to the charging inductor L1. It should be noted that the number of capacitors in the power converter of the present invention is not limited to six in the present embodiment, and may be four or more than six.

As shown in fig. 6, one end of the first switch Q5 is coupled to a node between the first switch Q1 and the first capacitor C1, one end of the first switch Q6 is coupled to a node between the first switch Q2 and the first capacitor C2, and one end of the first switch Q7 is coupled to a node between the first switch Q3 and the first capacitor C3. One terminal of the first switch Q8 is coupled to a node between the first capacitor C1 and the first switch Q2, one terminal of the first switch Q9 is coupled to a node between the first capacitor C2 and the first switch Q3, and one terminal of the first switch Q10 is coupled to a node between the first capacitor C3 and the first switch Q4. As shown in FIG. 6, the other terminals of the first switches Q5-Q7 are electrically connected to a node and then connected to the discharge inductor L2 in series, and the other terminals of the first switches Q8-Q10 are coupled to the ground potential. The other terminals of the charging inductor L1 and the discharging inductor L2 are coupled to the output voltage Vout together, and the other terminal of the first switch Q1 is coupled to the input voltage Vin.

Referring to fig. 6, a terminal 5 of the second switch Q1 is coupled to a node between the second switch Q11 and the second capacitor C4, a terminal of the second switch Q16 is coupled to a node between the second switch Q12 and the second capacitor C5, and a terminal of the second switch Q17 is coupled to a node between the second switch Q13 and the second capacitor C6. One terminal of the second switch Q18 is coupled to the node between the second capacitor C4 and the second switch Q12, one terminal of the second switch Q19 is coupled to the node between the second capacitor C5 and the second switch Q13, and one terminal of the second switch Q20 is coupled to the node between the second capacitor C6 and the second switch Q14. The other ends of the second switches Q15-Q17 are connected to a node in series and then connected to the discharge inductor L2. The other terminals of the second switches Q18-Q20 are commonly coupled to ground potential. The other end of the second switch Q11 is coupled to the input voltage Vin.

The first switches Q1-Q10 and the second switches Q11-Q20 can switch the electrical connection relationship between the corresponding first capacitors C1-C3 and second capacitors C4-C6 and the charging inductor L1 and the discharging inductor L2 according to the corresponding operation signals. In a first charging process, the first switches Q1-Q4 are turned on, and the first switches Q5-Q10 are turned off, so that the first capacitors C1-C3 are connected in series with the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a first charging path. In a first discharging procedure, the first switches Q5-Q10 are turned on, and the first switches Q1-Q4 are turned off, so that the first capacitor C1, the first capacitor C2 and the first capacitor C3 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of first discharging paths. Referring to fig. 6, in a second charging process, the second switches Q11-Q14 are turned on, and the second switches Q15-Q20 are turned off, so that the second capacitors C4-C6 are serially connected to the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a second charging path. In a second discharging process, the second switches Q15-Q20 are turned on, and the second switches Q11-Q14 are turned off, so that the second capacitor C4, the second capacitor C5, and the second capacitor C6 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of second discharging paths. It should be noted that the first charging process and the second discharging process are performed simultaneously, the first discharging process and the second charging process are performed simultaneously, the first charging process and the first discharging process are performed in different time periods, and the second charging process and the second discharging process are performed in different time periods. In the present embodiment, the dc bias voltages of each of the first capacitors C1-C3 and each of the second capacitors C4-C6 are Vo, so that the first capacitors C1-C3 and the second capacitors C4-C6 in the present embodiment need to withstand a lower rated voltage, and thus a smaller capacitor can be used.

In one embodiment, the duration of the first charging process is substantially a duty cycle (duty cycle) of a specific ratio, such as but not limited to substantially fifty percent duty cycle; therefore, the first switch can be switched at the time point when the current flowing through the first switch is relatively low in the positive half wave, so that flexible switching is realized. In a preferred embodiment, zero Current Switching (ZCS) is achieved.

In one embodiment, the duration of the first charging process is less than a specific percentage of the duty cycle for a first predetermined period, such as but not limited to less than fifty percent of the duty cycle for the first predetermined period; therefore, after the first switches Q1 to Q4 are turned off in advance, a small current is still maintained and flows through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the first switch Q10 can be carried away by the parasitic diode of the first switch Q4, and the voltage across the first switch Q10 is reduced, thereby achieving flexible switching. In a preferred embodiment, the first predetermined period is adjusted to achieve zero voltage switching.

In one embodiment, the duration of the first discharging procedure is greater than a specific percentage of the duty cycle for a second predetermined period, such as but not limited to greater than fifty percent of the duty cycle for the second predetermined period; therefore, after the first switches Q5 to Q10 are delayed to be turned off, the negative current of the discharging inductor L2 charges the parasitic capacitor of the first switch Q1 through the parasitic diode of the first switch Q5, and the voltage across the first switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the second predetermined period is adjusted to achieve zero voltage switching.

In one embodiment, the duration of the second charging process is substantially a specific percentage of the duty cycle, such as but not limited to substantially fifty percent of the duty cycle; therefore, the second switch can be switched at the time point when the current flowing through the second switch is relatively low in the positive half wave, so that flexible switching is realized. In a preferred embodiment, zero current switching is achieved.

In an embodiment, the duration of the second charging process is less than a specific proportion of the duty cycle for a first predetermined period, for example, but not limited to less than fifty percent of the duty cycle for the first predetermined period, so that a slight current is maintained after the second switches Q11-Q14 are turned off in advance, and flows through the charging inductor L1, and therefore, the accumulated charges stored in the parasitic capacitors of the second switch Q20 can be carried away by the parasitic diodes of the second switch Q14, and the voltage across the second switch Q20 is reduced, so as to achieve flexible switching. In a preferred embodiment, the first predetermined period is adjusted to achieve zero-voltage switching.

In one embodiment, the duration of the second discharging process is greater than a specific percentage of the duty cycle for a second predetermined period, such as but not limited to greater than fifty percent of the duty cycle for the second predetermined period; therefore, after the second switches Q15-Q20 are turned off, the negative current of the discharge inductor L2 charges the parasitic capacitance of the second switch Q11 through the parasitic diode of the second switch Q15, and the voltage across the second switch Q11 is reduced, so as to achieve flexible switching. In a preferred embodiment, the second predetermined period is adjusted to achieve zero voltage switching. In one embodiment, the specific ratio is related to the resonant frequency. In one embodiment, the first charging process has a first charging resonant frequency, the first discharging process has a first discharging resonant frequency, the second charging process has a second charging resonant frequency, and the second discharging process has a second discharging resonant frequency. In a preferred embodiment, the first charging resonant frequency is the same as the first discharging resonant frequency, and the second charging resonant frequency is the same as the second discharging resonant frequency.

In one embodiment, the power converter 60 may be a bidirectional power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the power converter 60 can be 4. In one embodiment, the first charging resonant frequency is

The first discharge resonant frequency is

The second charging resonance frequency is

The second discharge resonance frequency is

If C1= C2= C3= C4= C5= C6= Cr and fr6= fr7= fr8= fr9 is desired, the inductance values of L1 and L2 are required to be consistent

FIG. 7 is a circuit diagram of a power converter according to yet another embodiment of the invention. The power converter of the present embodiment is an interleaved power converter. As shown in fig. 7, the charging inductor of the present embodiment can be shifted between the input voltage Vin and the first switch Q1 and the second switch Q11, and the front-end inductor in the front-end converter 701 is used as the charging inductor L1, thereby further reducing the number of inductors. The power converter 70 of the present invention includes a first capacitor C1, a first capacitor C2, a first capacitor C3, a second capacitor C4, a second capacitor C5, a second capacitor C6, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a first switch Q8, a first switch Q9, a first switch Q10, a second switch Q11, a second switch Q12, a second switch Q13, a second switch Q14, a second switch Q15, a second switch Q16, a second switch Q17, a second switch Q18, a second switch Q19, a second switch Q20, a charging inductor L1, and a discharging inductor L2. The first switches Q1-Q3 are respectively connected in series with the corresponding first capacitors C1-C3, while the first switch Q4 is coupled to the output voltage Vout, the second switches Q11-Q13 are respectively connected in series with the corresponding second capacitors C4-C6, while the second switch Q14 is coupled to the output voltage Vout. The first switch Q1 is coupled to the charging inductor L1, the second switch Q11 is coupled to the charging inductor L1, and the other end of the charging inductor L1 is coupled to the input voltage Vin. It should be noted that the number of capacitors in the power converter of the present invention is not limited to six in the present embodiment, and may be four or more than six.

As shown in fig. 7, one end of the first switch Q5 is coupled to a node between the first switch Q1 and the first capacitor C1, one end of the first switch Q6 is coupled to a node between the first switch Q2 and the first capacitor C2, and one end of the first switch Q7 is coupled to a node between the first switch Q3 and the first capacitor C3. One terminal of the first switch Q8 is coupled to a node between the first capacitor C1 and the first switch Q2, one terminal of the first switch Q9 is coupled to a node between the first capacitor C2 and the first switch Q3, and one terminal of the first switch Q10 is coupled to a node between the first capacitor C3 and the first switch Q4. As shown in FIG. 7, the other terminals of the first switches Q5-Q7 are connected in series to the discharge inductor L2, and the other terminals of the first switches Q8-Q10 are coupled to the ground potential. The other end of the discharge inductor L2 is coupled to the output voltage Vout. Referring to fig. 7, a terminal of the second switch Q15 is coupled to a node between the second switch Q11 and the second capacitor C4, a terminal of the second switch Q16 is coupled to a node between the second switch Q12 and the second capacitor C5, and a terminal of the second switch Q17 is coupled to a node between the second switch Q13 and the second capacitor C6. One terminal of the second switch Q18 is coupled to the node between the second capacitor C4 and the second switch Q12, one terminal of the second switch Q19 is coupled to the node between the second capacitor C5 and the second switch Q13, and one terminal of the second switch Q20 is coupled to the node between the second capacitor C6 and the second switch Q14. The other terminals of the second switches Q15-Q17 are electrically connected to a node and then connected to the discharge inductor L2 in series, and the other terminals of the second switches Q18-Q20 are connected to the ground potential in series.

The first switches Q1-Q10 and the second switches Q11-Q20 can switch the electrical connection relationship between the corresponding first capacitors C1-C3 and second capacitors C4-C6 and the charging inductor L1 and the discharging inductor L2 according to the corresponding operation signals. In a first charging process, the first switches Q1-Q4 are turned on, and the first switches Q5-Q10 are turned off, so that the first capacitors C1-C3 are connected in series with the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a first charging path. In a first discharging procedure, the first switches Q5-Q10 are turned on, and the first switches Q1-Q4 are turned off, so that the first capacitor C1, the first capacitor C2 and the first capacitor C3 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of first discharging paths. Referring to fig. 7, in a second charging process, the second switches Q11-Q14 are turned on, and the second switches Q15-Q20 are turned off, so that the second capacitors C4-C6 are serially connected to the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a second charging path. In a second discharging process, the second switches Q15-Q20 are turned on, and the second switches Q11-Q14 are turned off, so that the second capacitor C4, the second capacitor C5 and the second capacitor C6 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of second discharging paths. It should be noted that the first charging process and the second discharging process are performed simultaneously, the first discharging process and the second charging process are performed simultaneously, the first charging process and the first discharging process are performed in different time periods, and the second charging process and the second discharging process are performed in different time periods. In the present embodiment, the dc bias voltages of each of the first capacitors C1-C3 and each of the second capacitors C4-C6 are Vo, so that the first capacitors C1-C3 and the second capacitors C4-C6 in the present embodiment need to withstand a lower rated voltage, and thus a smaller capacitor can be used.

In one embodiment, the duration of the first charging process is substantially a duty cycle (duty cycle) of a specific ratio, such as but not limited to substantially a fifty percent duty cycle; therefore, the first switch can be switched at the time point when the current flowing through the first switch is at a relatively low level of the positive half wave, so as to realize flexible switching. In a preferred embodiment, zero current switching is achieved.

In one embodiment, the duration of the second charging process is substantially a specific percentage of a duty cycle, such as but not limited to substantially fifty percent of the duty cycle; therefore, the second switch can be switched at the time point when the current flowing through the second switch is relatively low in the positive half wave, so that flexible switching is realized. In a preferred embodiment, zero current switching is achieved.

In one embodiment, the specific ratio is related to the resonant frequency. In one embodiment, the first charging process has a first charging resonant frequency, the first discharging process has a first discharging resonant frequency, the second charging process has a second charging resonant frequency, and the second discharging process has a second discharging resonant frequency. In a preferred embodiment, the first charging resonant frequency is the same as the first discharging resonant frequency, and the second charging resonant frequency is the same as the second discharging resonant frequency.

In one embodiment, the power converter 70 may be a bidirectional power converter. In one embodiment, the voltage conversion ratio between the input voltage Vin and the output voltage Vout of the power converter 70 can be 4. In one embodiment, the front-end converter 701 includes, but is not limited to, a buck converter, a boost converter, a buck-boost converter, and a buck-boost converter as shown in fig. 12A-12J.

Fig. 8 is a circuit diagram of a power converter according to yet another embodiment of the invention. The difference between this embodiment and the embodiment of fig. 4 is that the charging inductor L1 of the power converter 80 of this embodiment can be moved between the first switch Q3 and the first capacitor C3, and the rest of the elements are similar to those in fig. 4, and therefore are not described again. It should be noted that the number of capacitors in the power converter of the present invention is not limited to three in the present embodiment, and may be two or more than four.

FIG. 9 is a circuit diagram of a power converter according to yet another embodiment of the invention. The difference between the present embodiment and the embodiment shown in fig. 4 is that the charging inductor L1 of the power converter 90 of the present embodiment can be moved between the first switch Q1 and the first capacitor C1, the position of the discharging inductor L2 of the power converter 90 of the present embodiment is changed to be connected in series with the first switches Q8-Q10 connected in parallel, in other words, the first switches Q8-Q10 are connected in series to the discharging inductor L2 after being connected in parallel, the other end of the discharging inductor L2 is coupled to the ground potential, and the remaining elements are similar to those in fig. 4, and therefore are not described again. It should be noted that the number of capacitors in the power converter of the present invention is not limited to three in the present embodiment, and may be two or more than four.

Fig. 10 is a circuit diagram of a power converter according to yet another embodiment of the invention. The difference between the present embodiment and the embodiment shown in fig. 4A is that the charging inductor of the power converter 100 of the present embodiment can be moved between the first switch Q1 and the first capacitor C1, and the front end inductor in the front end converter 1001 is used as the charging inductor L1, and the switch in the front end converter 1001 is used as the first switch Q1, so as to further reduce the number of inductors, the position of the discharging inductor L2 of the power converter 100 of the present embodiment can be changed to be connected in series with the first switches Q6-Q7 connected in parallel, the first switches Q6-Q7 connected in parallel are connected in series to the discharging inductor L2, and the other end of the discharging inductor L2 is coupled to the ground potential. As shown in fig. 10, the power converter 100 of the present invention includes a first capacitor C1, a first capacitor C2, a first switch Q1, a first switch Q2, a first switch Q3, a first switch Q4, a first switch Q5, a first switch Q6, a first switch Q7, a charging inductor L1, and a discharging inductor L2. The first capacitors C1-C2 are respectively connected in series with the corresponding first switches Q2-Q3, and the first switch Q1 is connected in series with the charging inductor L1. It should be noted that the number of capacitors in the power converter of the present invention is not limited to two in the present embodiment, and may be three or more than four.

As shown in fig. 10, one end of the first switch Q4 is coupled to a node between the charging inductor L1 and the first capacitor C1, and one end of the first switch Q5 is coupled to a node between the first switch Q2 and the first capacitor C2. One end of the first switch Q6 is coupled to a node between the first capacitor C1 and the first switch Q2, and one end of the first switch Q7 is coupled to a node between the first capacitor C2 and the first switch Q3. The other ends of the first switches Q4-Q5 are commonly electrically connected to a node and then coupled to the output voltage Vout, the other ends of the first switches Q6-Q7 are commonly electrically connected to a node and then connected in series to the discharge inductor L2, and the other end of the discharge inductor L2 is coupled to the ground potential. The other end of the first switch Q1 is coupled to the input voltage Vin, the other end of the charging inductor L1 is coupled to the first capacitor C1, and the other end of the first switch Q3 is coupled to the output voltage Vout.

The first switches Q1 to Q7 can switch the electrical connection relationship between the corresponding first capacitors C1 to C2 and the charging inductor L1 and the discharging inductor L2 according to the corresponding operation signals. In a first charging process, the first switches Q1-Q3 are turned on and the first switches Q4-Q7 are turned off, so that the charging inductor L1 and the first capacitors C1-C2 connected in series are connected in series between the input voltage Vin and the output voltage Vout to form a first charging path. In a first discharging process, the first switches Q4-Q7 are turned on, and the first switches Q1-Q3 are turned off, so that the first capacitor C1, the first capacitor C2, and the first capacitor C3 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of first discharging paths. It should be noted that the first charging process and the first discharging process are performed alternately, not simultaneously, in different time periods. In the embodiment, the dc bias voltage of each of the first capacitors C1-C2 is Vo, so the first capacitors C1-C2 in the embodiment need to withstand a lower rated voltage, and thus a smaller capacitor can be used.

In one embodiment, the power converter 100 may be a bidirectional power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the power converter 100 may be 3. In one embodiment, the front-end converter 1001 includes, but is not limited to, the buck converter, the boost converter, the buck-boost converter, and the buck-boost converter shown in fig. 12A-12J.

Fig. 11A is a signal waveform diagram illustrating corresponding operation signals and corresponding inductor currents of a charging process and a discharging process according to an embodiment of the invention. Referring to fig. 4A, in the embodiment shown in fig. 11A, the operation signals G1 to G4 of the first switches Q1 to Q4 are at a high level during the charging process, and the operation signals G5 to G10 of the first switches Q5 to Q10 are at a high level during the discharging process. In the embodiment of FIG. 11A, the duration of the charging process is approximately fifty percent of the duty cycle; therefore, the first switch Q1 can be switched when the current flowing through the first switch is at a relatively low level in the positive half-wave, that is, when the current of the charging inductor L1 is zero, so as to realize flexible switching. In a preferred embodiment, zero current switching is achieved.

Fig. 11B and 11C are signal waveforms illustrating operation signals and inductor currents corresponding to a charging process and a discharging process according to another embodiment of the invention. Referring to fig. 4A, in the embodiment shown in fig. 11B, the operation signals G1 to G4 of the first switches Q1 to Q4 are at a high level during the first charging process, and the operation signals G5 to G10 of the first switches Q5 to Q10 are at a high level during the first discharging process. In the embodiment of fig. 11B, the duration of the first charging process is substantially less than fifty percent of the duty cycle for a predetermined period T1; therefore, after the first switches Q1 to Q4 are turned off in advance, a small current is still maintained to flow through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the first switch Q10 can be taken away through the parasitic diode of the first switch Q4, thereby reducing the voltage across the first switch Q10 and achieving flexible switching. In a preferred embodiment, the predetermined period T1 is adjusted to achieve zero voltage switching. Referring to fig. 4A, in the embodiment shown in fig. 11C, the operation signals G1 to G4 of the first switches Q1 to Q4 are at a high level during the first charging process, and the operation signals G5 to G10 of the first switches Q5 to Q10 are at a high level during the first discharging process. In the embodiment of fig. 11C, the duration of the first discharge process is substantially greater than fifty percent of the duty cycle for a predetermined period T2+ T3; therefore, after the first switches Q5 to Q10 are delayed to be turned off, the negative current of the discharging inductor L2 charges the parasitic capacitor of the first switch Q1 through the parasitic diode of the first switch Q5, and the voltage across the first switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the predetermined periods T2 and T2 are adjusted to achieve zero-voltage switching. In one embodiment, it should be noted that the embodiments of FIGS. 11B and 11C may be implemented together or only one of them. In addition, fig. 11D is a schematic diagram showing signal waveforms of an operation signal and a corresponding capacitor current corresponding to a charging process and a discharging process according to another embodiment of the invention. Referring to fig. 4A, as shown in fig. 11D, the duration of the charging process and the duration of the discharging process can be adjusted, such as adding the delay time Td, so as to more flexibly adjust the ratio of the input voltage Vin to the output voltage Vout.

Referring to fig. 13, a schematic diagram of a controller in a power converter is shown according to an embodiment of the invention. As shown in fig. 13, the power converter of the present invention may include a controller 1301 coupled to the first switches Q1 to 10 and/or the second switches Q11 to Q20 for generating operation signals G1 to G4, G5 to G10, G11 to 14, G15 to 20 to be respectively output to the first switches Q1 to Q4, Q5 to Q10 and/or the second switches Q11 to Q14, Q15 to 20, thereby respectively switching the first switches Q1 to Q4, Q5 to Q10 and/or the second switches Q11 to Q14, Q15 to 20.

The present invention provides a power converter, which can reduce the number of inductors, achieve resonant capacitance using a smaller-sized capacitor, reduce voltage stress, have better dynamic load transient response, have better current-voltage balance, have stable resonant frequency, be easier to control to achieve flexible switching with Zero Current Switching (ZCS) or Zero Voltage Switching (ZVS), more flexibly modulate the voltage conversion ratio, have a wider input voltage application range, and control the output voltage in a more precise range than the prior art, through a special circuit design.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. The embodiments described are not limited to single use, but may be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Therefore, the scope of the present invention should be construed to include all such and other equivalent variations.

Claims

1. A power converter for converting an input voltage to an output voltage, the power converter comprising:

a plurality of first capacitors;

a plurality of first switches, which are correspondingly coupled with the plurality of first capacitors and respectively switch the electrical connection relation of the corresponding first capacitors according to a corresponding first operating signal;

a plurality of second capacitors;

the second switches are correspondingly coupled with the second capacitors and respectively switch the electrical connection relation of the corresponding second capacitors according to a corresponding second operation signal;

at least one charging inductor which is correspondingly connected in series with at least one of the first capacitors; and

at least one discharge inductor connected in series with at least one of the first capacitors;

wherein, the at least one charging inductor is correspondingly connected in series with at least one of the plurality of second capacitors;

wherein, the at least one discharge inductor is correspondingly connected in series with at least one of the plurality of second capacitors;

in a first charging procedure, the plurality of first capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage through the switching of the plurality of first switches to form a first charging path;

in a first discharging procedure, each first capacitor and the corresponding discharging inductor are connected in series between the output voltage and a ground potential through the switching of the plurality of first switches to form a plurality of first discharging paths;

wherein, in a second charging procedure, the plurality of second capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage by switching the plurality of second switches to form a second charging path;

in a second discharging procedure, each second capacitor and the corresponding discharging inductor are connected in series between the output voltage and the grounding potential through the switching of the plurality of second switches, so as to form a plurality of second discharging paths;

wherein the first charging process and the first discharging process are repeatedly and alternately sequenced to convert the input voltage into the output voltage;

wherein the second charging process and the second discharging process are repeatedly and alternately sequenced to convert the input voltage into the output voltage;

wherein, the power converter executes the second discharging procedure during the first charging procedure;

the power converter executes the second charging procedure during the first discharging procedure.

2. The power converter as claimed in claim 1, wherein the at least one charging inductor is a plurality of charging inductors respectively connected in series with the first capacitors, and the first capacitors and the charging inductors are connected in series between the input voltage and the output voltage by switching the first switches during the first charging process to form the first charging path; in the first discharging procedure, the plurality of charging inductors are used as the plurality of discharging inductors, and the plurality of discharging inductors and the plurality of first capacitors are respectively connected in series between the output voltage and the grounding potential correspondingly through the switching of the plurality of first switches so as to form the plurality of first discharging paths, wherein the plurality of first discharging paths are connected in parallel with each other.

3. The power converter as claimed in claim 1, wherein the at least one charging inductor is a single charging inductor and the at least one discharging inductor is a single discharging inductor, and in the first discharging procedure, the plurality of first capacitors are connected in parallel to each other and then connected in series with the single discharging inductor by switching the plurality of first switches.

4. The power converter of claim 3 further comprising a front-end converter, wherein the front-end converter has a front-end inductor as the charging inductor.

5. The power converter of claim 4, wherein the front-end converter comprises a buck converter, a boost converter, a buck-boost converter, or a boost-buck converter.

6. The power converter of claim 1, 2, 3 or 4, wherein the first charging process has a first charging resonant frequency and the first discharging process has a first discharging resonant frequency, and the first charging resonant frequency is the same as the first discharging resonant frequency.

7. The power converter of claim 1, wherein the second charging process has a second charging resonant frequency, and the second discharging process has a second discharging resonant frequency, and the second charging resonant frequency is the same as the second discharging resonant frequency.

8. The power converter of claim 1, 2, 3 or 4, wherein the duration of the first charging process is equal to the duration of the first discharging process to achieve flexibly switched zero current switching.

9. The power converter of claim 1, wherein the second charging process is equal to the second discharging process to achieve soft switching zero current switching.

10. The power converter of claim 1, wherein the duration of the first charging process is adjusted to achieve soft-switching zero-voltage switching.

11. The power converter of claim 1, wherein the duration of the second charging process is adjusted to achieve soft-switching zero-voltage switching.

12. The power converter of claim 1, wherein the duration of the first discharging procedure is adjusted to achieve soft switching zero-voltage switching.

13. The power converter of claim 1, wherein the duration of the second discharging process is adjusted to achieve flexibly switched zero-voltage switching.

14. A power converter as claimed in any one of claims 1 to 3, wherein the power converter is a bidirectional power converter.

15. The power converter of any one of claims 1-3, wherein a voltage conversion ratio of the input voltage to the output voltage of the power converter is 4.

16. The power converter of claim 1, wherein the duration of the first charging process and the duration of the first discharging process do not overlap each other.

17. The power converter of claim 1, wherein the duration of the second charging process and the duration of the second discharging process do not overlap each other.

18. The power converter of claim 1, further comprising a controller coupled to the plurality of first switches for generating the first operating signal.