CN113541157A

CN113541157A - High-harmonic reactive compensation switching control method and device and computer equipment

Info

Publication number: CN113541157A
Application number: CN202110774145.7A
Authority: CN
Inventors: 黄海宇; 王莉; 马庆华; 李帮家; 李阳春; 赵国锋; 王伟胜; 王文涛
Original assignee: HANGZHOU DECHENG ELECTRIC POWER TECHNOLOGY CO LTD
Current assignee: HANGZHOU DECHENG ELECTRIC POWER TECHNOLOGY CO LTD
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2021-10-22
Anticipated expiration: 2041-07-08
Also published as: CN113541157B

Abstract

The embodiment of the invention discloses a high-harmonic reactive power compensation switching control method, a high-harmonic reactive power compensation switching control device and computer equipment. The method comprises the following steps: performing phase locking on hardware to obtain a phase-locked loop; acquiring a pulse signal of hardware; judging whether the pulse signal is a zero-crossing pulse signal; if the pulse signal is a zero-crossing pulse signal, acquiring an output angle of the phase-locked loop; judging whether the pulse signal is a real zero-crossing signal or not according to the output angle; and if the pulse signal is a real zero-crossing signal, performing signal detection and delay processing according to the pulse signal, and driving a relay to be controlled. By implementing the method provided by the embodiment of the invention, the zero-crossing judgment can be rapidly and accurately finished, the misjudgment can not occur, and the practicability is strong.

Description

High-harmonic reactive compensation switching control method and device and computer equipment

Technical Field

The invention relates to a switch control method, in particular to a high-harmonic reactive compensation switching control method, a high-harmonic reactive compensation switching control device and computer equipment.

Background

At present, in many power systems using ac power supply, the system circuit design often uses a large number of capacitive or inductive elements, and such electronic elements will be subjected to a large current impact if the input ac voltage is large at the moment the system is powered. In order to reduce the impact current of the capacitor and the inductor when the system circuit is powered, the time when the system circuit is powered needs to be accurately controlled, so that the alternating current power supply is switched on when the alternating current voltage crosses zero, and the impact of the power supply to the system circuit is reduced.

In order to control a system circuit to switch on external alternating current power supply when alternating current voltage crosses zero, a fling-cut switch is required to be arranged on the input side of an alternating current power supply of the system circuit, a voltage zero-crossing detection circuit is additionally arranged to accurately detect the voltage zero-crossing time of the external alternating current power supply, the fling-cut switch is further controlled to act near the voltage zero-crossing point, a power supply loop of the system circuit is switched on, the system circuit is safely powered on, and operation is started.

The high-order harmonics easily cause a plurality of signals during hardware zero-crossing detection, so that the problem of misjudgment easily occurs; the current zero-crossing switching feedback method mainly comprises two modes of voltage feedback and current feedback, wherein the current feedback mode is that an optical coupler influences the width of a zero-crossing pulse through parameters such as alternating current, different transmission ratios of the optical coupler, linearity and the like, the zero-crossing pulse is wide and inaccurate in zero crossing, and low-order harmonics such as 3, 5 and 7 have large influence on the width and precision of the zero-crossing pulse, so that the current feedback method is difficult to adapt to a power utilization environment mainly comprising 3-7-order harmonics generated by rectification inversion; the voltage feedback mode limits the zero-crossing voltage amplitude in a voltage stabilization mode, so that the zero-crossing pulse width is controlled, the zero-crossing comparison is accurate, the influence of 3, 5 and 7 harmonics on the zero-crossing pulse width is solved, the voltage feedback mode is difficult to adapt to the pollution of high-frequency harmonics more than 25 times to a power grid caused by new energy access such as photovoltaic power generation and the like, and the erroneous pulse is easily generated to cause the erroneous judgment.

Therefore, it is necessary to design a new method to achieve the zero-crossing judgment quickly and accurately, and the method is strong in practicability and does not cause misjudgment.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a high-harmonic reactive power compensation switching control method, a high-harmonic reactive power compensation switching control device and computer equipment.

In order to achieve the purpose, the invention adopts the following technical scheme: the high-harmonic reactive compensation switching control method comprises the following steps:

performing phase locking on hardware to obtain a phase-locked loop;

acquiring a pulse signal of hardware;

judging whether the pulse signal is a zero-crossing pulse signal;

if the pulse signal is a zero-crossing pulse signal, acquiring an output angle of the phase-locked loop;

judging whether the pulse signal is a real zero-crossing signal or not according to the output angle;

and if the pulse signal is a real zero-crossing signal, performing signal detection and delay processing according to the pulse signal, and driving a relay to be controlled.

The further technical scheme is as follows: after the determining whether the pulse signal is a zero-crossing pulse signal, the method further includes:

and if the pulse signal is not a zero-crossing pulse signal, executing the pulse signal of the acquisition hardware.

The further technical scheme is as follows: after the determining whether the pulse signal is a true zero-crossing signal according to the output angle, the method further includes:

and if the pulse signal is not a signal of a real zero crossing, discarding the pulse signal and executing the pulse signal of the acquisition hardware.

The further technical scheme is as follows: the phase locking of the hardware to obtain the phase-locked loop comprises:

and carrying out generalized integral phase locking on the voltage of the hardware to obtain the phase-locked loop.

The further technical scheme is as follows: the judging whether the pulse signal is a real zero-crossing signal according to the output angle includes:

judging whether the output angle is within a preset range;

if the output angle is within a preset range, the pulse signal is a real zero-crossing signal;

and if the output angle is not in the preset range, the pulse signal is not a real zero-crossing signal.

The further technical scheme is as follows: the signal detection and the time delay processing are carried out according to the pulse signal, and the relay is driven to be controlled, and the method comprises the following steps:

detecting a rising edge and a falling edge of the pulse signal to obtain the frequency of the pulse signal;

calculating the pulse width of the pulse signal;

calculating the theoretical zero crossing time of the next period according to the frequency and the pulse width;

carrying out time delay processing on the hardware and driving a relay to be put into operation;

and detecting a falling edge signal of the pulse signal, recording corresponding time, and setting the action time of the relay according to the time so as to realize the input control of the relay.

The invention also provides a high-harmonic reactive power compensation switching control device, which comprises:

the phase locking unit is used for locking the hardware to obtain a phase-locked loop;

the signal acquisition unit is used for acquiring a pulse signal of hardware;

the signal judging unit is used for judging whether the pulse signal is a zero-crossing pulse signal;

the angle acquisition unit is used for acquiring the output angle of the phase-locked loop if the pulse signal is a zero-crossing pulse signal;

the authenticity judging unit is used for judging whether the pulse signal is a real zero-crossing signal or not according to the output angle;

and the input control unit is used for carrying out signal detection and delay processing according to the pulse signal and driving the relay to be in input control if the pulse signal is a real zero-crossing signal.

The further technical scheme is as follows: further comprising:

and the discarding unit is used for discarding the pulse signal and executing the pulse signal of the acquisition hardware if the pulse signal is not a real zero-crossing signal.

The invention also provides computer equipment which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the method when executing the computer program.

The invention also provides a storage medium storing a computer program which, when executed by a processor, is operable to carry out the method as described above.

Compared with the prior art, the invention has the beneficial effects that: according to the invention, through setting a software phase lock, filtering out high-frequency harmonic influence, and combining a voltage feedback mode, zero crossing and authenticity judgment are carried out on a pulse signal of hardware, and when the pulse signal is a real zero crossing signal, a relay is driven to be controlled, so that zero crossing judgment can be completed quickly and accurately, no misjudgment occurs, and the practicability is strong.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flow chart of a high-harmonic reactive compensation switching control method according to an embodiment of the present invention;

fig. 2 is a sub-flow schematic diagram of a high-harmonic reactive compensation switching control method according to an embodiment of the present invention;

fig. 3 is a sub-flow schematic diagram of a high-harmonic reactive compensation switching control method according to an embodiment of the present invention;

fig. 4 is a schematic block diagram of a high-harmonic reactive power compensation switching control device provided in an embodiment of the present invention;

fig. 5 is a schematic block diagram of an input control unit of the high-harmonic reactive power compensation switching control device according to the embodiment of the present invention;

FIG. 6 is a schematic block diagram of a computer apparatus provided by an embodiment of the present invention;

fig. 7 is a schematic diagram of a zero-crossing pulse signal of the high-harmonic reactive compensation switching control method according to the embodiment of the present invention;

fig. 8 is a schematic circuit diagram of zero-crossing detection of the high-harmonic reactive power compensation switching control method according to the embodiment of the present invention;

fig. 9 is a schematic circuit diagram of voltage detection of the high-harmonic reactive power compensation switching control method according to the embodiment of the present invention;

fig. 10 is a schematic circuit diagram of current detection of the high-harmonic reactive compensation switching control method according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 1, fig. 1 is a schematic flow chart of a high-harmonic reactive power compensation switching control method according to an embodiment of the present invention. The high-harmonic reactive power compensation switching control method is applied to a server.

Fig. 1 is a schematic flow diagram of a high-harmonic reactive compensation switching control method provided by an embodiment of the present invention. As shown in fig. 1, the method includes the following steps S110 to S170.

And S110, performing phase locking on the hardware to obtain a phase-locked loop.

In this embodiment, the voltage of the hardware is subjected to the generalized integral phase locking to obtain the phase-locked loop.

In this embodiment, the phase-locked loop refers to a circuit obtained by performing generalized integral software phase-locking on a hardware voltage.

Specifically, a second-order generalized integrator, which is a solution based on 90 ° phase angle shift of the input sinusoidal signal, can be used to perform generalized integral phase locking on the voltage of the hardware. After an input voltage signal passes through an SOGI (Second-Order generalized Integrator), two-phase orthogonal signals can be generated, one output signal tracks the input voltage signal, and the other signal realizes 90-degree phase angle offset of the input voltage signal. On the basis of a voltage feedback scheme, software phase locking is combined, namely phase locking is performed by a sampling generalized integral method, so that the influence of high-frequency harmonic waves is filtered, and the phenomenon of misjudgment caused by multiple signals generated in hardware zero-crossing detection due to higher harmonic waves is avoided.

Specifically, the voltage of the hardware is subjected to generalized integral phase locking to obtain a phase-locked loop.

And S120, acquiring a pulse signal of hardware.

In the embodiment, the software phase lock follows the zero crossing point of the voltage frequency and collects the pulse signal of the hardware in real time.

In this embodiment, the pulse signal refers to a voltage signal of hardware.

And S130, judging whether the pulse signal is a zero-crossing pulse signal.

In the embodiment, the zero-crossing judgment of the pulse signal is performed in combination with a voltage feedback method.

If the pulse signal is not a zero-crossing pulse signal, the step S120 is executed.

And S140, if the pulse signal is a zero-crossing pulse signal, acquiring an output angle of the phase-locked loop.

In this embodiment, the output angle of the phase-locked loop is processed by the three-phase grid voltage phase.

And S150, judging whether the pulse signal is a real zero-crossing signal or not according to the output angle.

Software assists in judging zero-crossing and effective signals under the condition of high harmonic waves, and hardware detects the feedback of the action time of a switch so as to be put into a relay.

In an embodiment, referring to fig. 2, the step S150 may include steps S151 to S153.

S151, judging whether the output angle is in a preset range;

s152, if the output angle is within a preset range, the pulse signal is a real zero-crossing signal;

and S153, if the output angle is not in the preset range, the pulse signal is not a real zero-crossing signal.

In this embodiment, if the output angle is within the set 2 °, it is determined that the pulse signal is a signal of a true zero-crossing, and if the output angle is not within the set 2 °, it is determined that the pulse signal is not a signal of a true zero-crossing.

And S160, if the pulse signal is a real zero-crossing signal, performing signal detection and delay processing according to the pulse signal, and driving a relay to be controlled.

In an embodiment, referring to fig. 3, the step S160 may include steps S161 to S165.

S161, detecting the rising edge and the falling edge of the pulse signal to obtain the frequency of the pulse signal;

and S162, calculating the pulse width of the pulse signal.

In the present embodiment, the pulse width of the pulse signal is equal to the sum of the widths of the rising edge and the falling edge in one period.

And S163, calculating the theoretical zero-crossing time of the next period according to the frequency and the pulse width.

The time of the zero crossing point of the next cycle can be calculated according to the frequency and the pulse width of the pulse signal.

And S164, carrying out time delay processing on the hardware and driving a relay to be put into operation.

In the embodiment, the hardware is delayed for t1-t2, t2 is the action time of the relay, t1 is the theoretical zero-crossing time of the next period, and the relay is driven to be put into operation

And S165, detecting a falling edge signal of the pulse signal, recording corresponding time, and setting the action time of the relay according to the time so as to realize the input control of the relay.

And detecting a pulse falling edge signal, recording the corresponding time as t2, and finishing the input control, wherein t2 is the action time of the relay.

S170, if the pulse signal is not a real zero-crossing signal, discarding the pulse signal, and executing the step S120.

If the output angle of the phase-locked loop is not within the range of 2 degrees, the pulse signal is discarded, and the next zero-crossing pulse is generated.

In one embodiment, as shown in fig. 7, the pulse signal is a zero-crossing pulse signal, from time t1 to time t12, recording a time each time an interrupt is entered, if Abs ((t3-t2) - (t6-t7)) <150 us; abs ((t5-t4) - (t9-t8)) <150 us; 6ms < t7-t6<14 ms; 6ms < t9-t8<14 ms; 19.8ms < t9-t5<20.2ms, the relay can be driven to be controlled, if the formula is not satisfied, the related error flag is set to play a role of prompting. After the interruption at time t9, a delay ((t9-t5) -zero-cross pulse width/2-switching time), that is, a drive switch (i.e., a relay) is turned on, and the time tim1 of the turn-on is recorded.

Referring to fig. 8, the zero-crossing signal is divided by the ac voltage at the two ends of the relay through resistors, and the rectifier bridge converts the ac voltage into a dc voltage; when the voltage at two ends of the voltage-stabilizing diode D15 is higher than 6.2V, due to the voltage drop of the voltage-stabilizing diode D15, the voltage of an emitter of the PNP triode Q5 is lower than the voltage of a base electrode of the PNP triode Q1, at the moment, the PNP triode Q1 and the PNP triode Q5 are in a cut-off state, the optocoupler U11 is in a cut-off state, the zero-crossing signal is at a high level, and the capacitor C14 is in a charging state; when the voltage at the two ends of the voltage stabilizing diode D15 is lower than 6.2V, the voltage at the two ends of the capacitor C14 is 6.2V, therefore, the base voltage of the PNP triode Q1 is lower than the emitter voltage of the PNP triode Q5, the PNP triode Q1 and the PNP triode Q5 are in a conducting state, the collector of the PNP triode Q5 is at a high level, the optocoupler U11 is in a conducting state, the base voltage of the NPN triode Q6 is higher than the emitter voltage, and the zero-crossing signal is at a low level.

Referring to fig. 9 to 10, the voltage and current analog signals are sampled and calculated through an ADC port of the single chip microcomputer by following the signals.

According to the high-harmonic reactive compensation switching control method, the zero-crossing and authenticity judgment is carried out on the pulse signal of the hardware by setting the software phase lock, filtering out the high-frequency harmonic influence and combining the voltage feedback mode, when the pulse signal is the real zero-crossing signal, the relay is driven to be controlled, the zero-crossing judgment is completed quickly and accurately, the misjudgment cannot occur, and the practicability is high.

Fig. 4 is a schematic block diagram of a high-harmonic reactive power compensation switching control device 300 according to an embodiment of the present invention. As shown in fig. 4, the invention further provides a high-harmonic reactive power compensation switching control device 300 corresponding to the above high-harmonic reactive power compensation switching control method. The zero-crossing switching control device 300 includes a unit for executing the zero-crossing switching control method, and the device may be configured in a desktop computer, a tablet computer, a laptop computer, or the like. Specifically, referring to fig. 4, the high-harmonic reactive power compensation switching control device 300 includes a phase-locking unit 301, a signal obtaining unit 302, a signal determining unit 303, an angle obtaining unit 304, an authenticity determining unit 305, and an input control unit 306.

A phase-locking unit 301, configured to perform phase locking on hardware to obtain a phase-locked loop; a signal acquiring unit 302, configured to acquire a pulse signal of hardware; a signal judgment unit 303, configured to judge whether the pulse signal is a zero-crossing pulse signal; an angle obtaining unit 304, configured to obtain an output angle of the phase-locked loop if the pulse signal is a zero-crossing pulse signal; an authenticity judging unit 305 for judging whether the pulse signal is a true zero-crossing signal according to the output angle; and the input control unit 306 is used for performing signal detection and delay processing according to the pulse signal and driving the relay to be in control if the pulse signal is a real zero-crossing signal.

In an embodiment, as shown in fig. 4, the high-harmonic reactive power compensation switching control device 300 further includes:

a discarding unit 307, configured to discard the pulse signal and execute the pulse signal of the acquisition hardware if the pulse signal is not a signal of a true zero crossing.

In an embodiment, the phase locking unit 301 is configured to perform generalized integral phase locking on a voltage of the hardware to obtain a phase locked loop.

In an embodiment, the authenticity determining unit 305 is configured to determine whether the output angle is within a preset range; if the output angle is within a preset range, the pulse signal is a real zero-crossing signal; and if the output angle is not in the preset range, the pulse signal is not a real zero-crossing signal.

In one embodiment, as shown in fig. 5, the input control unit 306 includes a detection subunit 3061, a width calculation subunit 3062, a time calculation subunit 3063, a delay time processing subunit 3064, and a time setting subunit 3065.

A detecting subunit 3061, configured to detect a rising edge and a falling edge of the pulse signal to obtain a frequency of the pulse signal; a width calculation subunit 3062 for calculating a pulse width of the pulse signal; a time calculation subunit 3063, configured to calculate a theoretical zero-crossing time of the next cycle according to the frequency and the pulse width; the delay processing subunit 3064 is configured to perform delay processing on the hardware and drive the relay to be turned on; and a time setting subunit 3065, which is used for detecting the falling edge signal of the pulse signal, recording the corresponding time, and setting the action time of the relay according to the time so as to realize the input control of the relay.

It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation processes of the high-harmonic reactive power compensation switching control device 300 and each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is provided herein.

The high-harmonic reactive power compensation switching control device 300 may be implemented in the form of a computer program, and the computer program may be executed on a computer device as shown in fig. 6.

Referring to fig. 6, fig. 6 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 may be a server, wherein the server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 6, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 comprises program instructions that, when executed, cause the processor 502 to perform a method for high harmonic reactive compensation switching control.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for running the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 may be enabled to execute the high-harmonic reactive compensation switching control method.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 6 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:

performing phase locking on hardware to obtain a phase-locked loop;

acquiring a pulse signal of hardware; judging whether the pulse signal is a zero-crossing pulse signal; if the pulse signal is a zero-crossing pulse signal, acquiring an output angle of the phase-locked loop; judging whether the pulse signal is a real zero-crossing signal or not according to the output angle; and if the pulse signal is a real zero-crossing signal, performing signal detection and delay processing according to the pulse signal, and driving a relay to be controlled.

In one embodiment, after the step of determining whether the pulse signal is a zero-crossing pulse signal, the processor 502 further performs the following steps:

In an embodiment, after implementing the step of determining whether the pulse signal is a true zero crossing according to the output angle, the processor 502 further implements the following steps:

In an embodiment, when the processor 502 implements the step of performing phase locking on the hardware to obtain the phase-locked loop, the following steps are specifically implemented:

In an embodiment, when the step of determining whether the pulse signal is a true zero-crossing signal according to the output angle is implemented, the processor 502 specifically implements the following steps:

judging whether the output angle is within a preset range; if the output angle is within a preset range, the pulse signal is a real zero-crossing signal; and if the output angle is not in the preset range, the pulse signal is not a real zero-crossing signal.

In an embodiment, when the processor 502 implements the signal detection and the delay processing according to the pulse signal, and drives the relay to perform the control step, the following steps are specifically implemented:

detecting a rising edge and a falling edge of the pulse signal to obtain the frequency of the pulse signal; calculating the pulse width of the pulse signal; calculating the theoretical zero crossing time of the next period according to the frequency and the pulse width; carrying out time delay processing on the hardware and driving a relay to be put into operation; and detecting a falling edge signal of the pulse signal, recording corresponding time, and setting the action time of the relay according to the time so as to realize the input control of the relay.

It should be understood that in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program, when executed by a processor, causes the processor to perform the steps of:

performing phase locking on hardware to obtain a phase-locked loop; acquiring a pulse signal of hardware; judging whether the pulse signal is a zero-crossing pulse signal; if the pulse signal is a zero-crossing pulse signal, acquiring an output angle of the phase-locked loop; judging whether the pulse signal is a real zero-crossing signal or not according to the output angle; and if the pulse signal is a real zero-crossing signal, performing signal detection and delay processing according to the pulse signal, and driving a relay to be controlled.

In an embodiment, after the step of determining whether the pulse signal is a zero-crossing pulse signal is realized by the processor executing the computer program, the following steps are further realized:

In an embodiment, after the step of determining whether the pulse signal is a true zero crossing according to the output angle is implemented by the processor executing the computer program, the following steps are further implemented:

In an embodiment, when the processor executes the computer program to implement the step of performing phase locking on the hardware to obtain the phase-locked loop, the following steps are specifically implemented:

In an embodiment, when the processor executes the computer program to implement the step of determining whether the pulse signal is a true zero-crossing signal according to the output angle, the following steps are specifically implemented:

In an embodiment, when the processor executes the computer program to implement the signal detection and the delay processing according to the pulse signal, and drive the relay to switch into the control step, the following steps are specifically implemented:

The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The high-harmonic reactive compensation switching control method is characterized by comprising the following steps:

performing phase locking on hardware to obtain a phase-locked loop;

acquiring a pulse signal of hardware;

judging whether the pulse signal is a zero-crossing pulse signal;

2. The switching control method for high-harmonic reactive power compensation according to claim 1, wherein after determining whether the pulse signal is a zero-crossing pulse signal, the method further comprises:

3. The switching control method for high-harmonic reactive power compensation according to claim 1, wherein after determining whether the pulse signal is a true zero-crossing signal according to the output angle, the method further comprises:

4. The switching control method for high-harmonic reactive power compensation according to claim 1, wherein the phase-locking the hardware to obtain the phase-locked loop comprises:

5. The high-harmonic reactive power compensation switching control method according to claim 1, wherein the determining whether the pulse signal is a true zero-crossing signal according to the output angle comprises:

judging whether the output angle is within a preset range;

6. The high-harmonic reactive power compensation switching control method according to claim 1, wherein the performing signal detection and delay processing according to the pulse signal and driving a relay to be put into control comprises:

calculating the pulse width of the pulse signal;

7. High harmonic reactive compensation switching controlling means, its characterized in that includes:

the signal acquisition unit is used for acquiring a pulse signal of hardware;

8. The high-harmonic reactive power compensation switching control device according to claim 7, further comprising:

9. A computer device, characterized in that the computer device comprises a memory, on which a computer program is stored, and a processor, which when executing the computer program implements the method according to any of claims 1 to 6.

10. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 6.