CN113540228A

CN113540228A - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN113540228A
Application number: CN202010317069.2A
Authority: CN
Inventors: 周钰杰; 林琮翔
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2020-04-21
Filing date: 2020-04-21
Publication date: 2021-10-22

Abstract

The embodiment of the invention provides a semiconductor device. The semiconductor device includes: a substrate; a buffer layer on the substrate; a blocking layer located on the buffer layer, wherein the channel region is located in the buffer layer and adjacent to an interface of the buffer layer and the blocking layer; a doped compound semiconductor layer on a portion of the barrier layer; an undoped first cap layer on the doped compound semiconductor layer; a gate structure on the undoped first cap layer; and source/drain structures respectively located at two sides of the gate structure.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly, to a high electron mobility transistor and a method for forming the same.

Background

A High Electron Mobility Transistor (HEMT), also known as a Heterostructure Field Effect Transistor (HFET) or a modulation-doped FET (MODFET), is a Field Effect Transistor (FET) composed of semiconductor materials with different energy gaps (energy gaps), and a two-dimensional electron gas (2 DEG) layer is generated adjacent to an interface (interface) formed by the different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor has the advantages of high breakdown voltage, high electron mobility, low on-resistance, low input capacitance and the like, and is suitable for high-power elements.

An enhancement mode (E-mode) high electron mobility transistor is in an off state when a gate voltage is not applied. Conventionally, a P-type iii-v semiconductor is used in electrical connection with a gate as an energy band adjustment layer. With the demand of ultra high voltage applications, high electron mobility transistors are required to provide higher threshold voltages (Vt). However, before performing system testing, the high electron mobility transistor needs to have high stability and high reliability.

Although the conventional high electron mobility transistors have been generally satisfactory in many respects, it is desirable to further improve the process uniformity (device uniformity) and hysteresis (hysteresis effect) of the high electron mobility transistors.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device, including: a substrate; a buffer layer on the substrate; a barrier layer (barrier layer) on the buffer layer, wherein the channel region is in the buffer layer and adjacent to an interface of the buffer layer and the barrier layer; a doped compound semiconductor layer on a portion of the barrier layer; an undoped first cap layer (capping layer) on the doped compound semiconductor layer; a gate structure on the undoped first cap layer; and source/drain structures respectively located at two sides of the gate structure.

The present invention also provides a method for forming a conductor device, comprising: forming a buffer layer on a substrate; forming a blocking layer on the buffer layer, wherein the channel region is positioned in the buffer layer and is adjacent to an interface between the buffer layer and the blocking layer; forming a layer stack on a portion of the barrier layer, sequentially from bottom to top: a doped compound semiconductor layer, an undoped first cover layer and a grid structure; and forming source/drain structures on two sides of the gate structure respectively.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

Fig. 1-9 and 10A are cross-sectional views illustrating various stages in the process of forming a semiconductor device, in accordance with some embodiments of the present invention.

FIG. 10B is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[ notation ] to show

100 substrate

102 buffer layer

104 barrier layer

106 channel region

108 doped compound semiconductor layer

110 undoped first cap layer

111 second cap layer

112 gate electrode

114 passivation layer

115a,115b, openings

116 gate metal layer

118 gate structure

120 source/drain structure

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below" … …, "below," "lower," "above … …," "above," "upper," and the like, may be used herein to facilitate describing one element(s) or feature(s) of the figure(s) relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".

Although the steps in some of the described embodiments are performed in a particular order, these steps may be performed in other logical orders. In various embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and/or after the described steps in embodiments of the invention. Other features may be added to the high electron mobility transistors of embodiments of the present invention. Some features may be replaced or omitted in different embodiments.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the semiconductor device provided by the embodiment of the invention, the undoped cover layer is arranged between the grid structure and the doped compound semiconductor layer below the grid structure, so that the doped compound semiconductor layer below the grid structure is protected from being damaged due to high temperature and high energy of the subsequent process. The use of the cap layer to protect the doped compound semiconductor layer can improve the process uniformity (device uniformity) and the hysteresis of the semiconductor device, and the semiconductor device can provide a higher saturation current (Isat) and a higher breakdown voltage (breakdown voltage).

Fig. 1-9 and 10A are cross-sectional views illustrating various stages in the process of forming a semiconductor device, in accordance with some embodiments of the present invention. Referring to fig. 1, a substrate 100 is provided. In some embodiments, the substrate 100 may be a bulk semiconductor substrate or the like, which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. Other substrates, such as multi-layered or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may be an elemental semiconductor including silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide (silicon carbide), gallium arsenide (gallium arsenic), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), or indium antimonide (indium antimonide); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination of the foregoing. In other embodiments, the substrate 100 may also be a glass substrate, a silicon-on-insulator substrate, a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Sapphire (Sapphire) substrate. In one embodiment, the ceramic substrate may be coated with an insulating layer.

Next, referring to fig. 2, a buffer layer 102 is formed on the substrate 100. In some embodiments, the buffer layer 102 may include a group III-V semiconductor, such as gallium nitride (GaN). In other embodiments, the buffer layer 102 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V semiconductor materials, or combinations of the foregoing. The thickness of the buffer layer 102 may be between about 1000nm and about 10000 nm. The buffer layer 102 may be formed by molecular-beam epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or a combination thereof.

Next, referring to fig. 3, a barrier layer 104 is formed on the buffer layer 102. The barrier layer 104 is a different material than the buffer layer 102. In some embodiments, barrier layer 104 may include barrier layer 106 may include a group III-V semiconductor, such as Al_xGa_1-xN, wherein 0<x<1. In other embodiments, the barrier layer 104 may also comprise GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations of the foregoing. The thickness of the barrier layer 104 may be between about 5nm and about 50 nm. The barrier layer 104 may be formed using molecular beam epitaxy, metal organic vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the foregoing.

The buffer layer 102 and the barrier layer 104 are made of different materials and have different band gaps (bandgaps), so that a heterojunction is formed at the interface between the buffer layer 102 and the barrier layer 104. Since the energy band at the heterojunction bends, the depth of the conduction band bending can form a quantum well (quantum well) that confines electrons generated by the piezoelectric effect (piezoelectric) to the quantum well. Thus, a two-dimensional electron gas (2 DEG) is formed at the interface of the buffer layer 104 and the barrier layer 106, thereby forming an on-state current. As shown in fig. 3, a channel region 106 is formed at the interface of the buffer layer 102 and the barrier layer 104, and the channel region 106 is a place where the two-dimensional electron gas forms an on-current.

Next, referring to fig. 4 to 10A, a layer stack is formed on the barrier layer 104, the layer stack including the doped compound semiconductor layer 108, the undoped first cap layer 110 and the gate structure 118 to be formed subsequently. First, as illustrated in fig. 4, a doped compound semiconductor layer 108 is formed on the barrier layer 104. In some embodiments, the doped compound semiconductor layer 108 may comprise a p-type doped group III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. In some other embodiments, the doped compound semiconductor layer 108 may comprise a p-type doped II-VI semiconductor, such as CdSCdTe, or ZnS. In some embodiments, the doped compound semiconductor layer 108 may Be doped with magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li), or sodium (Na) to make the doped compound semiconductor layer 108 p-type doped with a doping concentration between about 1x10¹⁵cm^-3To about 1x10²⁵cm^-3And (3) removing the solvent.

Next, as illustrated in fig. 5, an undoped first cap layer 110 is formed on the doped compound semiconductor layer 108. Although undoped first cap layer 110 is referred to herein as an "undoped" first cap layer, it should be understood that there is a minimum or baseline level of dopants due to the inevitable introduction of some extraneous material during other intrinsic epitaxial processes. Generally, the undoped first cap layer 110 has a thickness of less than 5x10¹⁷cm^-3The doping concentration of (c). However, it is still desirable that the first cap layer 110 remain in an undoped state. In one embodiment, the "undoped" first cap layer 110 refers to the first cap layer 110 that is not implanted with other elements, such as group iii-v semiconductors, using Diffusion and Ion Implantation (Ion Implantation).

High temperature environments and high energy plasma sources are typically required in subsequent processes for forming gate structures and source/drain structures. However, in the high temperature and high energy process, the bonds of the doped compound semiconductor on the surface of the doped compound semiconductor layer 108 are easily broken, and many charged defects (traps) are generated, thereby affecting the performance of the manufactured semiconductor device. Therefore, the undoped first cap layer 110 is disposed above the doped compound semiconductor layer 108, so as to protect the doped compound semiconductor layer 108 therebelow from being damaged due to high temperature and high energy of the subsequent process, thereby improving process uniformity and hysteresis of the semiconductor device and enabling the semiconductor device to provide a higher saturation current.

In some embodiments, the undoped first cap layer 110 comprises a silicon-containing material. In embodiments where the undoped first cap layer 110 comprises a Silicon-containing material, the Silicon-containing material may be a Silicon-containing semiconductor material, such as Silicon or Silicon carbide, which may be single crystal (si crystal), polycrystalline (Poly crystal), or amorphous (amorphous), and in a preferred embodiment, may be Low Temperature polysilicon (Low Temperature Poly-Silicon). In some other embodiments, the silicon-containing material may also include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, or combinations of the foregoing.

In the p-type doping process for forming the doped compound semiconductor layer 108, since the dopant is doped with a low activation rate, the non-activated dopant may generate many charged defects in the doped compound semiconductor layer 108, thereby affecting the performance of the manufactured semiconductor device. Therefore, if the undoped first cap layer 110 comprises a silicon-containing semiconductor material, the silicon-containing semiconductor material can compensate the above-mentioned inactive dopants in addition to protecting the underlying doped compound semiconductor layer 108 from being damaged by the high temperature and high energy of the subsequent processes, thereby further improving the process uniformity and hysteresis of the semiconductor device and enabling the semiconductor device to provide a higher saturation current. In addition, the semiconductor material containing silicon in the undoped first cap layer 110 is an n-type semiconductor material compared to the p-type doping of the doped compound semiconductor layer 108, so that the undoped first cap layer 110 may form an NP junction (NP junction) with the doped compound semiconductor layer 108. The NP junction is reverse biased (reverse bias) when the semiconductor device is turned on (on-state, i.e. when the gate voltage is greater than 0), which can reduce the gate leakage current of the semiconductor device and increase the breakdown voltage of the gate.

In some embodiments, the thickness of the undoped first cap layer 110 is between about 1nm and 100 nm. The undoped first capping layer 110 may be formed using a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, any other suitable method, or a combination of the foregoing. For example, the chemical vapor deposition process may include a low-pressure chemical vapor deposition (LPCVD) process, a low-temperature chemical vapor deposition (LTCVD) process, a Rapid Thermal CVD (RTCVD) process, a Plasma Enhanced CVD (PECVD) process, or an Atomic Layer Deposition (ALD) process. For example, the physical vapor deposition process may include a sputtering (sputtering) process, an evaporation (evaporation) process, or a Pulsed Laser Deposition (PLD) process.

Next, as shown in fig. 6, a gate electrode 112 is formed on the undoped first cap layer 110. In some embodiments, the material of the gate electrode 112 may be a conductive material such as a metal, a metal nitride, a semiconductor material, or other suitable conductive material. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), or the like, or a combination thereof, and the semiconductor material may be polysilicon or poly-germanium. The gate electrode 112 may be formed using a chemical vapor deposition process, a physical vapor deposition process, any other suitable method, or a combination of the foregoing. For example, the chemical vapor deposition process can include a low pressure chemical vapor deposition process, a low temperature chemical vapor deposition process, a rapid thermal chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition process. For example, the physical vapor deposition process may include a sputtering process, an evaporation process, or a pulsed laser deposition process.

Next, referring to fig. 7, the doped compound semiconductor layer 108, the undoped first cap layer 110 and the gate electrode 112 are patterned to expose a portion of the barrier layer 104. The patterning process includes a photolithography process and an etching process. In some embodiments, the photolithography process may include photoresist coating (photoresist coating), soft baking (soft baking), hard baking (hard baking), mask alignment (mask alignment), exposure (exposure), post-exposure baking, developing (leveling) photoresist, rinsing (rinsing), drying (drying), or other suitable processes. In some embodiments, the etching process may comprise a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process may include a Reactive Ion Etch (RIE) process or a plasma etching process.

After patterning the layers, as shown in fig. 8, a passivation layer 114 is formed on the exposed barrier layer 104 to cover the patterned doped compound semiconductor layer 108, the undoped first cap layer 110 and the gate electrode 112. In some embodiments, the passivation layer may include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, Fluorinated Silicate Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon doped silicon oxide, fluorinated carbon (fluorocarbon), parylene (parylene), Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), other insulating materials, or combinations of the foregoing. Passivation layer 114 may be formed using a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, other suitable processes, or a combination of the foregoing.

For example, in some embodiments, a passivation layer 114 may be blanket formed over the barrier layer 104, the doped compound semiconductor layer 108, the undoped first cap layer 110, and the gate electrode 112, and then excess material of the passivation layer 114 may be removed by an appropriate planarization process to provide a planar upper surface of the passivation layer 114. In some embodiments, the planarization process may include a Chemical Mechanical Polishing (CMP) process, a mechanical polishing process, a grinding process, an etching process, or a combination thereof.

Next, as shown in fig. 9, an opening 115a exposing the gate electrode 112 and an opening 115b exposing the barrier layer 104 are formed in the passivation layer by a patterning process, wherein the openings 115b are located at two sides of the opening 115 a.

Openings

115a and 115b will be used for subsequently formed gate metal layers and source/drain structures. Referring to fig. 10A, a gate metal layer 116 is formed in the opening 115a through the passivation layer 114 and directly contacting the gate electrode 112, and a source/drain structure 120 is formed in the opening 115b through the passivation layer 114 and directly contacting the barrier layer 104. In some embodiments, the gate electrode layer 112 and the source/drain structure 120 are formed together in the same process, but not limited thereto. In other embodiments, the gate electrode layer 112 and the source/drain structures 120 may be formed separately in different processes.

In some embodiments, the gate metal layer 116 may include a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), a metal oxide, a metal alloy, other suitable conductive material, or a combination of the foregoing. The gate metal layer 116 and the gate electrode 112 are referred to herein as a gate structure 118, as shown in fig. 10A. The materials and processes for forming the source/drain structures 120 may be similar or identical to the gate electrode 112, and will not be repeated herein.

As illustrated in fig. 10A, the semiconductor device according to the embodiment of the invention includes a substrate 100, a buffer layer 102 on the substrate 100, a barrier layer 104 on the buffer layer 102, a doped compound semiconductor layer 108 on a portion of the barrier layer 104, an undoped first cap layer 110 on the doped compound semiconductor layer 108, a passivation layer 114 on the barrier layer 104, a gate structure 118 on the undoped first cap layer 110, and source/drain structures 120 on both sides of the gate structure 118, wherein the source/drain structures 120 pass through the passivation layer 104 and directly contact the barrier layer 104. In addition, the semiconductor device further includes a channel region 106 in the buffer layer 102 and adjacent to the interface between the buffer layer 102 and the barrier layer 104. In these embodiments, the gate structure 118 includes a gate electrode 112 and a gate electrode layer 116, wherein the gate electrode 112 is located on the undoped first cap layer 110, and the gate electrode layer 116 is located on the gate electrode 112.

In the embodiments shown in fig. 1 to 9 and 10A, by disposing the undoped first cap layer between the gate structure of the semiconductor device and the doped compound semiconductor layer thereunder, the doped compound semiconductor layer thereunder can be protected from many charged defects due to high temperature and high energy in the subsequent processes. In addition, in the above embodiments, the undoped first cap layer includes a silicon-containing semiconductor material, which can compensate for the inactive dopants in the doped compound semiconductor layer in addition to protecting the underlying doped compound semiconductor layer. Experiments prove that the process uniformity of the semiconductor device can be improved by about 2 to 5 times, the hysteresis of the semiconductor device can be reduced by about 10 times, and the semiconductor device can provide more than 2 times of saturation current by arranging the cover layer with the silicon-containing semiconductor on the doped compound semiconductor layer. Furthermore, the silicon-containing semiconductor material is an n-type semiconductor compared to the doped compound semiconductor layer, so that the undoped first cap layer can form an NP junction with the doped compound semiconductor layer. The NP junction is reverse biased when the semiconductor device is turned on (i.e. when the gate voltage is greater than 0), so that the gate leakage current of the semiconductor device can be reduced, and the breakdown voltage of the gate can be increased.

FIG. 10B is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. In these embodiments, the layer stack formed by the doped compound semiconductor 108, the undoped first cap layer 110 and the gate structure 118 further includes the second cap layer 111. The second cap layer 111 is located between the undoped first cap layer 110 and the gate structure 118. More specifically, an undoped first cap layer 110 is formed on the doped compound semiconductor layer 108, and a second cap layer 111 is formed on the undoped first cap layer 110. In a preferred embodiment, the doped compound semiconductor 108, the undoped first cap layer 110 and the second cap layer 111 are patterned simultaneously, such that the vertical projection areas of the doped compound semiconductor 108, the undoped first cap layer 110 and the second cap layer 111 are the same. Compared with the undoped first cap layer 110, the second cap layer 111 not only can further protect the doped compound semiconductor layer 108 during the process, but also can compensate the defects of electrons or holes generated by the post-process, and a reverse diode is formed at the interface of the first cap layer 110 and the doped compound semiconductor layer 108, thereby reducing the gate leakage current of the semiconductor device and increasing the breakdown voltage of the gate.

In some embodiments, the second cap layer 111 and the undoped first cap layer 110 are formed of different materials. For example, according to some embodiments of the present invention, the material of the second capping layer 111 comprises aluminum oxide, aluminum nitride, or a combination of the foregoing. Second cap layer 111 may be formed using a chemical vapor deposition process, a physical vapor deposition process, any other suitable method, or a combination of the foregoing. In some embodiments, the thickness of the second cap layer 111 is between about 1nm and 100 nm.

In summary, in the semiconductor device provided by the embodiments of the present invention, the undoped cap layer is disposed between the gate structure and the doped compound semiconductor layer therebelow, so that the doped compound semiconductor layer is protected from being damaged due to the high temperature and the high energy of the process in the high temperature and high energy process, the process uniformity and the hysteresis of the semiconductor device are improved, and the semiconductor device provides a higher saturation current. In addition, the silicon-containing semiconductor material in the cap layer not only compensates for the charge defects in the doped compound semiconductor layer, but also causes the cap layer and the doped compound semiconductor layer to form an NP junction, thereby reducing the gate leakage current of the semiconductor device and increasing the breakdown voltage of the gate.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

the buffer layer is positioned on the substrate;

a barrier layer on the buffer layer, wherein a channel region is in the buffer layer and adjacent to an interface of the buffer layer and the barrier layer;

a doped compound semiconductor layer on a portion of the barrier layer;

an undoped first cap layer on the doped compound semiconductor layer;

a gate structure on the undoped first cap layer; and

and the source electrode/drain electrode structures are respectively positioned at two sides of the grid electrode structure.

2. The semiconductor device of claim 1, wherein the gate structure further comprises a gate electrode and a gate metal layer, the gate electrode being on the undoped first cap layer and the gate metal layer being on the gate electrode.

3. The semiconductor device of claim 1, further comprising a passivation layer on the barrier layer, wherein the source/drain structure passes through the passivation layer and directly contacts the barrier layer.

4. The semiconductor device of claim 1, wherein said undoped first cap layer comprises a silicon-containing material.

5. The semiconductor device of claim 4, wherein the undoped first cap layer comprises a silicon-containing semiconductor material.

6. The semiconductor device according to claim 4, wherein the silicon-containing material comprises silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, or a combination thereof.

7. The semiconductor device of claim 1, wherein the thickness of the undoped first cap layer is between 1nm and 100 nm.

8. The semiconductor device of claim 1, further comprising a second cap layer between the undoped first cap layer and the gate structure, wherein the second cap layer and the undoped first cap layer are formed of different materials.

9. The semiconductor device according to claim 8, wherein a material of the second cap layer comprises aluminum oxide or aluminum nitride.

10. The semiconductor device of claim 8, wherein the thickness of the second cap layer is between 1nm and 100 nm.